utils/cmsis/same70/include/component/spi.h

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/*
 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
 */

#ifndef _SAME70_SPI_COMPONENT_
#define _SAME70_SPI_COMPONENT_

/* ============================================================================= */
/* ============================================================================= */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {
  __O  uint32_t SPI_CR;        
  __IO uint32_t SPI_MR;        
  __I  uint32_t SPI_RDR;       
  __O  uint32_t SPI_TDR;       
  __I  uint32_t SPI_SR;        
  __O  uint32_t SPI_IER;       
  __O  uint32_t SPI_IDR;       
  __I  uint32_t SPI_IMR;       
  __I  uint32_t Reserved1[4];
  __IO uint32_t SPI_CSR[4];    
  __I  uint32_t Reserved2[41];
  __IO uint32_t SPI_WPMR;      
  __I  uint32_t SPI_WPSR;      
  __I  uint32_t Reserved3[4];
  __I  uint32_t SPI_VERSION;   
} Spi;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
#define SPI_CR_SPIEN (0x1u << 0) 
#define SPI_CR_SPIDIS (0x1u << 1) 
#define SPI_CR_SWRST (0x1u << 7) 
#define SPI_CR_REQCLR (0x1u << 12) 
#define SPI_CR_TXFCLR (0x1u << 16) 
#define SPI_CR_RXFCLR (0x1u << 17) 
#define SPI_CR_LASTXFER (0x1u << 24) 
#define SPI_CR_FIFOEN (0x1u << 30) 
#define SPI_CR_FIFODIS (0x1u << 31) 
/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
#define SPI_MR_MSTR (0x1u << 0) 
#define SPI_MR_PS (0x1u << 1) 
#define SPI_MR_PCSDEC (0x1u << 2) 
#define SPI_MR_MODFDIS (0x1u << 4) 
#define SPI_MR_WDRBT (0x1u << 5) 
#define SPI_MR_LLB (0x1u << 7) 
#define SPI_MR_PCS_Pos 16
#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) 
#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
#define SPI_MR_DLYBCS_Pos 24
#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) 
#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
#define SPI_RDR_RD_Pos 0
#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) 
#define SPI_RDR_PCS_Pos 16
#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) 
/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
#define SPI_TDR_TD_Pos 0
#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) 
#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
#define SPI_TDR_PCS_Pos 16
#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) 
#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
#define SPI_TDR_LASTXFER (0x1u << 24) 
/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
#define SPI_SR_RDRF (0x1u << 0) 
#define SPI_SR_TDRE (0x1u << 1) 
#define SPI_SR_MODF (0x1u << 2) 
#define SPI_SR_OVRES (0x1u << 3) 
#define SPI_SR_NSSR (0x1u << 8) 
#define SPI_SR_TXEMPTY (0x1u << 9) 
#define SPI_SR_UNDES (0x1u << 10) 
#define SPI_SR_SPIENS (0x1u << 16) 
/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
#define SPI_IER_RDRF (0x1u << 0) 
#define SPI_IER_TDRE (0x1u << 1) 
#define SPI_IER_MODF (0x1u << 2) 
#define SPI_IER_OVRES (0x1u << 3) 
#define SPI_IER_NSSR (0x1u << 8) 
#define SPI_IER_TXEMPTY (0x1u << 9) 
#define SPI_IER_UNDES (0x1u << 10) 
/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
#define SPI_IDR_RDRF (0x1u << 0) 
#define SPI_IDR_TDRE (0x1u << 1) 
#define SPI_IDR_MODF (0x1u << 2) 
#define SPI_IDR_OVRES (0x1u << 3) 
#define SPI_IDR_NSSR (0x1u << 8) 
#define SPI_IDR_TXEMPTY (0x1u << 9) 
#define SPI_IDR_UNDES (0x1u << 10) 
/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
#define SPI_IMR_RDRF (0x1u << 0) 
#define SPI_IMR_TDRE (0x1u << 1) 
#define SPI_IMR_MODF (0x1u << 2) 
#define SPI_IMR_OVRES (0x1u << 3) 
#define SPI_IMR_NSSR (0x1u << 8) 
#define SPI_IMR_TXEMPTY (0x1u << 9) 
#define SPI_IMR_UNDES (0x1u << 10) 
/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register (CS_number = 0) -------- */
#define SPI_CSR_CPOL (0x1u << 0) 
#define SPI_CSR_NCPHA (0x1u << 1) 
#define SPI_CSR_CSNAAT (0x1u << 2) 
#define SPI_CSR_CSAAT (0x1u << 3) 
#define SPI_CSR_BITS_Pos 4
#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) 
#define SPI_CSR_BITS(value) ((SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos)))
#define   SPI_CSR_BITS_8_BIT (0x0u << 4) 
#define   SPI_CSR_BITS_9_BIT (0x1u << 4) 
#define   SPI_CSR_BITS_10_BIT (0x2u << 4) 
#define   SPI_CSR_BITS_11_BIT (0x3u << 4) 
#define   SPI_CSR_BITS_12_BIT (0x4u << 4) 
#define   SPI_CSR_BITS_13_BIT (0x5u << 4) 
#define   SPI_CSR_BITS_14_BIT (0x6u << 4) 
#define   SPI_CSR_BITS_15_BIT (0x7u << 4) 
#define   SPI_CSR_BITS_16_BIT (0x8u << 4) 
#define SPI_CSR_SCBR_Pos 8
#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) 
#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
#define SPI_CSR_DLYBS_Pos 16
#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) 
#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
#define SPI_CSR_DLYBCT_Pos 24
#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) 
#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Mode Register -------- */
#define SPI_WPMR_WPEN (0x1u << 0) 
#define SPI_WPMR_WPKEY_Pos 8
#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) 
#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)))
#define   SPI_WPMR_WPKEY_PASSWD (0x535049u << 8) 
/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
#define SPI_WPSR_WPVS (0x1u << 0) 
#define SPI_WPSR_WPVSRC_Pos 8
#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) 
/* -------- SPI_VERSION : (SPI Offset: 0xFC) Version Register -------- */
#define SPI_VERSION_VERSION_Pos 0
#define SPI_VERSION_VERSION_Msk (0xfffu << SPI_VERSION_VERSION_Pos) 
#define SPI_VERSION_MFN_Pos 16
#define SPI_VERSION_MFN_Msk (0x7u << SPI_VERSION_MFN_Pos) 


#endif /* _SAME70_SPI_COMPONENT_ */