utils/cmsis/same70/include/component/spi.h
Go to the documentation of this file.
1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_SPI_COMPONENT_
36 #define _SAME70_SPI_COMPONENT_
37 
38 /* ============================================================================= */
40 /* ============================================================================= */
43 
44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
45 
46 typedef struct {
47  __O uint32_t SPI_CR;
48  __IO uint32_t SPI_MR;
49  __I uint32_t SPI_RDR;
50  __O uint32_t SPI_TDR;
51  __I uint32_t SPI_SR;
52  __O uint32_t SPI_IER;
53  __O uint32_t SPI_IDR;
54  __I uint32_t SPI_IMR;
55  __I uint32_t Reserved1[4];
56  __IO uint32_t SPI_CSR[4];
57  __I uint32_t Reserved2[41];
58  __IO uint32_t SPI_WPMR;
59  __I uint32_t SPI_WPSR;
60  __I uint32_t Reserved3[4];
61  __I uint32_t SPI_VERSION;
62 } Spi;
63 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
64 /* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
65 #define SPI_CR_SPIEN (0x1u << 0)
66 #define SPI_CR_SPIDIS (0x1u << 1)
67 #define SPI_CR_SWRST (0x1u << 7)
68 #define SPI_CR_REQCLR (0x1u << 12)
69 #define SPI_CR_TXFCLR (0x1u << 16)
70 #define SPI_CR_RXFCLR (0x1u << 17)
71 #define SPI_CR_LASTXFER (0x1u << 24)
72 #define SPI_CR_FIFOEN (0x1u << 30)
73 #define SPI_CR_FIFODIS (0x1u << 31)
74 /* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
75 #define SPI_MR_MSTR (0x1u << 0)
76 #define SPI_MR_PS (0x1u << 1)
77 #define SPI_MR_PCSDEC (0x1u << 2)
78 #define SPI_MR_MODFDIS (0x1u << 4)
79 #define SPI_MR_WDRBT (0x1u << 5)
80 #define SPI_MR_LLB (0x1u << 7)
81 #define SPI_MR_PCS_Pos 16
82 #define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos)
83 #define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
84 #define SPI_MR_DLYBCS_Pos 24
85 #define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos)
86 #define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
87 /* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
88 #define SPI_RDR_RD_Pos 0
89 #define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos)
90 #define SPI_RDR_PCS_Pos 16
91 #define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos)
92 /* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
93 #define SPI_TDR_TD_Pos 0
94 #define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos)
95 #define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
96 #define SPI_TDR_PCS_Pos 16
97 #define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos)
98 #define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
99 #define SPI_TDR_LASTXFER (0x1u << 24)
100 /* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
101 #define SPI_SR_RDRF (0x1u << 0)
102 #define SPI_SR_TDRE (0x1u << 1)
103 #define SPI_SR_MODF (0x1u << 2)
104 #define SPI_SR_OVRES (0x1u << 3)
105 #define SPI_SR_NSSR (0x1u << 8)
106 #define SPI_SR_TXEMPTY (0x1u << 9)
107 #define SPI_SR_UNDES (0x1u << 10)
108 #define SPI_SR_SPIENS (0x1u << 16)
109 /* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
110 #define SPI_IER_RDRF (0x1u << 0)
111 #define SPI_IER_TDRE (0x1u << 1)
112 #define SPI_IER_MODF (0x1u << 2)
113 #define SPI_IER_OVRES (0x1u << 3)
114 #define SPI_IER_NSSR (0x1u << 8)
115 #define SPI_IER_TXEMPTY (0x1u << 9)
116 #define SPI_IER_UNDES (0x1u << 10)
117 /* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
118 #define SPI_IDR_RDRF (0x1u << 0)
119 #define SPI_IDR_TDRE (0x1u << 1)
120 #define SPI_IDR_MODF (0x1u << 2)
121 #define SPI_IDR_OVRES (0x1u << 3)
122 #define SPI_IDR_NSSR (0x1u << 8)
123 #define SPI_IDR_TXEMPTY (0x1u << 9)
124 #define SPI_IDR_UNDES (0x1u << 10)
125 /* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
126 #define SPI_IMR_RDRF (0x1u << 0)
127 #define SPI_IMR_TDRE (0x1u << 1)
128 #define SPI_IMR_MODF (0x1u << 2)
129 #define SPI_IMR_OVRES (0x1u << 3)
130 #define SPI_IMR_NSSR (0x1u << 8)
131 #define SPI_IMR_TXEMPTY (0x1u << 9)
132 #define SPI_IMR_UNDES (0x1u << 10)
133 /* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register (CS_number = 0) -------- */
134 #define SPI_CSR_CPOL (0x1u << 0)
135 #define SPI_CSR_NCPHA (0x1u << 1)
136 #define SPI_CSR_CSNAAT (0x1u << 2)
137 #define SPI_CSR_CSAAT (0x1u << 3)
138 #define SPI_CSR_BITS_Pos 4
139 #define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos)
140 #define SPI_CSR_BITS(value) ((SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos)))
141 #define SPI_CSR_BITS_8_BIT (0x0u << 4)
142 #define SPI_CSR_BITS_9_BIT (0x1u << 4)
143 #define SPI_CSR_BITS_10_BIT (0x2u << 4)
144 #define SPI_CSR_BITS_11_BIT (0x3u << 4)
145 #define SPI_CSR_BITS_12_BIT (0x4u << 4)
146 #define SPI_CSR_BITS_13_BIT (0x5u << 4)
147 #define SPI_CSR_BITS_14_BIT (0x6u << 4)
148 #define SPI_CSR_BITS_15_BIT (0x7u << 4)
149 #define SPI_CSR_BITS_16_BIT (0x8u << 4)
150 #define SPI_CSR_SCBR_Pos 8
151 #define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos)
152 #define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
153 #define SPI_CSR_DLYBS_Pos 16
154 #define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos)
155 #define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
156 #define SPI_CSR_DLYBCT_Pos 24
157 #define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos)
158 #define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
159 /* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Mode Register -------- */
160 #define SPI_WPMR_WPEN (0x1u << 0)
161 #define SPI_WPMR_WPKEY_Pos 8
162 #define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos)
163 #define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)))
164 #define SPI_WPMR_WPKEY_PASSWD (0x535049u << 8)
165 /* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
166 #define SPI_WPSR_WPVS (0x1u << 0)
167 #define SPI_WPSR_WPVSRC_Pos 8
168 #define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos)
169 /* -------- SPI_VERSION : (SPI Offset: 0xFC) Version Register -------- */
170 #define SPI_VERSION_VERSION_Pos 0
171 #define SPI_VERSION_VERSION_Msk (0xfffu << SPI_VERSION_VERSION_Pos)
172 #define SPI_VERSION_MFN_Pos 16
173 #define SPI_VERSION_MFN_Msk (0x7u << SPI_VERSION_MFN_Pos)
176 
177 
178 #endif /* _SAME70_SPI_COMPONENT_ */
__I uint32_t SPI_SR
(Spi Offset: 0x10) Status Register
__I uint32_t SPI_IMR
(Spi Offset: 0x1C) Interrupt Mask Register
__I uint32_t SPI_RDR
(Spi Offset: 0x08) Receive Data Register
#define __IO
Definition: core_cm7.h:266
#define __O
Definition: core_cm7.h:265
Spi hardware registers.
__O uint32_t SPI_IER
(Spi Offset: 0x14) Interrupt Enable Register
__IO uint32_t SPI_WPMR
(Spi Offset: 0xE4) Write Protection Mode Register
__O uint32_t SPI_TDR
(Spi Offset: 0x0C) Transmit Data Register
__O uint32_t SPI_IDR
(Spi Offset: 0x18) Interrupt Disable Register
__I uint32_t SPI_WPSR
(Spi Offset: 0xE8) Write Protection Status Register
__O uint32_t SPI_CR
(Spi Offset: 0x00) Control Register
__IO uint32_t SPI_MR
(Spi Offset: 0x04) Mode Register
#define __I
Definition: core_cm7.h:263
__I uint32_t SPI_VERSION
(Spi Offset: 0xFC) Version Register


inertial_sense_ros
Author(s):
autogenerated on Sat Sep 19 2020 03:19:05