component/icm.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_ICM_COMPONENT_
36 #define _SAME70_ICM_COMPONENT_
37 
38 /* ============================================================================= */
40 /* ============================================================================= */
43 
44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
45 
46 typedef struct {
47  __IO uint32_t ICM_CFG;
48  __O uint32_t ICM_CTRL;
49  __I uint32_t ICM_SR;
50  __I uint32_t Reserved1[1];
51  __O uint32_t ICM_IER;
52  __O uint32_t ICM_IDR;
53  __I uint32_t ICM_IMR;
54  __I uint32_t ICM_ISR;
55  __I uint32_t ICM_UASR;
56  __I uint32_t Reserved2[3];
57  __IO uint32_t ICM_DSCR;
58  __IO uint32_t ICM_HASH;
59  __O uint32_t ICM_UIHVAL[8];
60  __I uint32_t Reserved3[37];
61  __I uint32_t ICM_ADDRSIZE;
62  __I uint32_t ICM_IPNAME[2];
63  __I uint32_t ICM_FEATURES;
64  __I uint32_t ICM_VERSION;
65 } Icm;
66 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
67 /* -------- ICM_CFG : (ICM Offset: 0x00) Configuration Register -------- */
68 #define ICM_CFG_WBDIS (0x1u << 0)
69 #define ICM_CFG_EOMDIS (0x1u << 1)
70 #define ICM_CFG_SLBDIS (0x1u << 2)
71 #define ICM_CFG_BBC_Pos 4
72 #define ICM_CFG_BBC_Msk (0xfu << ICM_CFG_BBC_Pos)
73 #define ICM_CFG_BBC(value) ((ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos)))
74 #define ICM_CFG_ASCD (0x1u << 8)
75 #define ICM_CFG_DUALBUFF (0x1u << 9)
76 #define ICM_CFG_UIHASH (0x1u << 12)
77 #define ICM_CFG_UALGO_Pos 13
78 #define ICM_CFG_UALGO_Msk (0x7u << ICM_CFG_UALGO_Pos)
79 #define ICM_CFG_UALGO(value) ((ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos)))
80 #define ICM_CFG_UALGO_SHA1 (0x0u << 13)
81 #define ICM_CFG_UALGO_SHA256 (0x1u << 13)
82 #define ICM_CFG_UALGO_SHA224 (0x4u << 13)
83 #define ICM_CFG_HAPROT_Pos 16
84 #define ICM_CFG_HAPROT_Msk (0x3fu << ICM_CFG_HAPROT_Pos)
85 #define ICM_CFG_HAPROT(value) ((ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos)))
86 #define ICM_CFG_DAPROT_Pos 24
87 #define ICM_CFG_DAPROT_Msk (0x3fu << ICM_CFG_DAPROT_Pos)
88 #define ICM_CFG_DAPROT(value) ((ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos)))
89 /* -------- ICM_CTRL : (ICM Offset: 0x04) Control Register -------- */
90 #define ICM_CTRL_ENABLE (0x1u << 0)
91 #define ICM_CTRL_DISABLE (0x1u << 1)
92 #define ICM_CTRL_SWRST (0x1u << 2)
93 #define ICM_CTRL_REHASH_Pos 4
94 #define ICM_CTRL_REHASH_Msk (0xfu << ICM_CTRL_REHASH_Pos)
95 #define ICM_CTRL_REHASH(value) ((ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos)))
96 #define ICM_CTRL_RMDIS_Pos 8
97 #define ICM_CTRL_RMDIS_Msk (0xfu << ICM_CTRL_RMDIS_Pos)
98 #define ICM_CTRL_RMDIS(value) ((ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos)))
99 #define ICM_CTRL_RMEN_Pos 12
100 #define ICM_CTRL_RMEN_Msk (0xfu << ICM_CTRL_RMEN_Pos)
101 #define ICM_CTRL_RMEN(value) ((ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos)))
102 /* -------- ICM_SR : (ICM Offset: 0x08) Status Register -------- */
103 #define ICM_SR_ENABLE (0x1u << 0)
104 #define ICM_SR_RAWRMDIS_Pos 8
105 #define ICM_SR_RAWRMDIS_Msk (0xfu << ICM_SR_RAWRMDIS_Pos)
106 #define ICM_SR_RAWRMDIS(value) ((ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos)))
107 #define ICM_SR_RMDIS_Pos 12
108 #define ICM_SR_RMDIS_Msk (0xfu << ICM_SR_RMDIS_Pos)
109 #define ICM_SR_RMDIS(value) ((ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos)))
110 /* -------- ICM_IER : (ICM Offset: 0x10) Interrupt Enable Register -------- */
111 #define ICM_IER_RHC_Pos 0
112 #define ICM_IER_RHC_Msk (0xfu << ICM_IER_RHC_Pos)
113 #define ICM_IER_RHC(value) ((ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos)))
114 #define ICM_IER_RDM_Pos 4
115 #define ICM_IER_RDM_Msk (0xfu << ICM_IER_RDM_Pos)
116 #define ICM_IER_RDM(value) ((ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos)))
117 #define ICM_IER_RBE_Pos 8
118 #define ICM_IER_RBE_Msk (0xfu << ICM_IER_RBE_Pos)
119 #define ICM_IER_RBE(value) ((ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos)))
120 #define ICM_IER_RWC_Pos 12
121 #define ICM_IER_RWC_Msk (0xfu << ICM_IER_RWC_Pos)
122 #define ICM_IER_RWC(value) ((ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos)))
123 #define ICM_IER_REC_Pos 16
124 #define ICM_IER_REC_Msk (0xfu << ICM_IER_REC_Pos)
125 #define ICM_IER_REC(value) ((ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos)))
126 #define ICM_IER_RSU_Pos 20
127 #define ICM_IER_RSU_Msk (0xfu << ICM_IER_RSU_Pos)
128 #define ICM_IER_RSU(value) ((ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos)))
129 #define ICM_IER_URAD (0x1u << 24)
130 /* -------- ICM_IDR : (ICM Offset: 0x14) Interrupt Disable Register -------- */
131 #define ICM_IDR_RHC_Pos 0
132 #define ICM_IDR_RHC_Msk (0xfu << ICM_IDR_RHC_Pos)
133 #define ICM_IDR_RHC(value) ((ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos)))
134 #define ICM_IDR_RDM_Pos 4
135 #define ICM_IDR_RDM_Msk (0xfu << ICM_IDR_RDM_Pos)
136 #define ICM_IDR_RDM(value) ((ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos)))
137 #define ICM_IDR_RBE_Pos 8
138 #define ICM_IDR_RBE_Msk (0xfu << ICM_IDR_RBE_Pos)
139 #define ICM_IDR_RBE(value) ((ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos)))
140 #define ICM_IDR_RWC_Pos 12
141 #define ICM_IDR_RWC_Msk (0xfu << ICM_IDR_RWC_Pos)
142 #define ICM_IDR_RWC(value) ((ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos)))
143 #define ICM_IDR_REC_Pos 16
144 #define ICM_IDR_REC_Msk (0xfu << ICM_IDR_REC_Pos)
145 #define ICM_IDR_REC(value) ((ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos)))
146 #define ICM_IDR_RSU_Pos 20
147 #define ICM_IDR_RSU_Msk (0xfu << ICM_IDR_RSU_Pos)
148 #define ICM_IDR_RSU(value) ((ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos)))
149 #define ICM_IDR_URAD (0x1u << 24)
150 /* -------- ICM_IMR : (ICM Offset: 0x18) Interrupt Mask Register -------- */
151 #define ICM_IMR_RHC_Pos 0
152 #define ICM_IMR_RHC_Msk (0xfu << ICM_IMR_RHC_Pos)
153 #define ICM_IMR_RDM_Pos 4
154 #define ICM_IMR_RDM_Msk (0xfu << ICM_IMR_RDM_Pos)
155 #define ICM_IMR_RBE_Pos 8
156 #define ICM_IMR_RBE_Msk (0xfu << ICM_IMR_RBE_Pos)
157 #define ICM_IMR_RWC_Pos 12
158 #define ICM_IMR_RWC_Msk (0xfu << ICM_IMR_RWC_Pos)
159 #define ICM_IMR_REC_Pos 16
160 #define ICM_IMR_REC_Msk (0xfu << ICM_IMR_REC_Pos)
161 #define ICM_IMR_RSU_Pos 20
162 #define ICM_IMR_RSU_Msk (0xfu << ICM_IMR_RSU_Pos)
163 #define ICM_IMR_URAD (0x1u << 24)
164 /* -------- ICM_ISR : (ICM Offset: 0x1C) Interrupt Status Register -------- */
165 #define ICM_ISR_RHC_Pos 0
166 #define ICM_ISR_RHC_Msk (0xfu << ICM_ISR_RHC_Pos)
167 #define ICM_ISR_RDM_Pos 4
168 #define ICM_ISR_RDM_Msk (0xfu << ICM_ISR_RDM_Pos)
169 #define ICM_ISR_RBE_Pos 8
170 #define ICM_ISR_RBE_Msk (0xfu << ICM_ISR_RBE_Pos)
171 #define ICM_ISR_RWC_Pos 12
172 #define ICM_ISR_RWC_Msk (0xfu << ICM_ISR_RWC_Pos)
173 #define ICM_ISR_REC_Pos 16
174 #define ICM_ISR_REC_Msk (0xfu << ICM_ISR_REC_Pos)
175 #define ICM_ISR_RSU_Pos 20
176 #define ICM_ISR_RSU_Msk (0xfu << ICM_ISR_RSU_Pos)
177 #define ICM_ISR_URAD (0x1u << 24)
178 /* -------- ICM_UASR : (ICM Offset: 0x20) Undefined Access Status Register -------- */
179 #define ICM_UASR_URAT_Pos 0
180 #define ICM_UASR_URAT_Msk (0x7u << ICM_UASR_URAT_Pos)
181 #define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (0x0u << 0)
182 #define ICM_UASR_URAT_ICM_CFG_MODIFIED (0x1u << 0)
183 #define ICM_UASR_URAT_ICM_DSCR_MODIFIED (0x2u << 0)
184 #define ICM_UASR_URAT_ICM_HASH_MODIFIED (0x3u << 0)
185 #define ICM_UASR_URAT_READ_ACCESS (0x4u << 0)
186 /* -------- ICM_DSCR : (ICM Offset: 0x30) Region Descriptor Area Start Address Register -------- */
187 #define ICM_DSCR_DASA_Pos 6
188 #define ICM_DSCR_DASA_Msk (0x3ffffffu << ICM_DSCR_DASA_Pos)
189 #define ICM_DSCR_DASA(value) ((ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos)))
190 /* -------- ICM_HASH : (ICM Offset: 0x34) Region Hash Area Start Address Register -------- */
191 #define ICM_HASH_HASA_Pos 7
192 #define ICM_HASH_HASA_Msk (0x1ffffffu << ICM_HASH_HASA_Pos)
193 #define ICM_HASH_HASA(value) ((ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos)))
194 /* -------- ICM_UIHVAL[8] : (ICM Offset: 0x38) User Initial Hash Value 0 Register -------- */
195 #define ICM_UIHVAL_VAL_Pos 0
196 #define ICM_UIHVAL_VAL_Msk (0xffffffffu << ICM_UIHVAL_VAL_Pos)
197 #define ICM_UIHVAL_VAL(value) ((ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos)))
198 /* -------- ICM_ADDRSIZE : (ICM Offset: 0xEC) Address Size Register -------- */
199 #define ICM_ADDRSIZE_ADDRSIZE_Pos 0
200 #define ICM_ADDRSIZE_ADDRSIZE_Msk (0xffffu << ICM_ADDRSIZE_ADDRSIZE_Pos)
201 /* -------- ICM_IPNAME[2] : (ICM Offset: 0xF0) IP Name 1 Register -------- */
202 #define ICM_IPNAME_IPNAME_Pos 0
203 #define ICM_IPNAME_IPNAME_Msk (0xffffffffu << ICM_IPNAME_IPNAME_Pos)
204 /* -------- ICM_FEATURES : (ICM Offset: 0xF8) Feature Register -------- */
205 #define ICM_FEATURES_CFGALGO (0x1u << 0)
206 #define ICM_FEATURES_RFU (0x1u << 1)
207 #define ICM_FEATURES_CFGPP (0x1u << 2)
208 #define ICM_FEATURES_HDPP (0x1u << 3)
209 #define ICM_FEATURES_PDC (0x1u << 4)
210 #define ICM_FEATURES_NAIS (0x1u << 5)
211 #define ICM_FEATURES_EF (0x1u << 6)
212 #define ICM_FEATURES_SI (0x1u << 7)
213 #define ICM_FEATURES_BTYP (0x1u << 8)
214 #define ICM_FEATURES_PDCOFF0C (0x1u << 9)
215 #define ICM_FEATURES_HSHA1 (0x1u << 16)
216 #define ICM_FEATURES_HSHA224 (0x1u << 17)
217 #define ICM_FEATURES_HSHA256 (0x1u << 18)
218 #define ICM_FEATURES_HSHA384 (0x1u << 19)
219 #define ICM_FEATURES_HSHA512 (0x1u << 20)
220 /* -------- ICM_VERSION : (ICM Offset: 0xFC) Version Register -------- */
221 #define ICM_VERSION_VERSION_Pos 0
222 #define ICM_VERSION_VERSION_Msk (0xfffu << ICM_VERSION_VERSION_Pos)
223 #define ICM_VERSION_MFN_Pos 16
224 #define ICM_VERSION_MFN_Msk (0x7u << ICM_VERSION_MFN_Pos)
227 
228 
229 #endif /* _SAME70_ICM_COMPONENT_ */
#define __IO
Definition: core_cm7.h:266
#define __O
Definition: core_cm7.h:265
__I uint32_t ICM_SR
(Icm Offset: 0x08) Status Register
Definition: component/icm.h:49
__IO uint32_t ICM_HASH
(Icm Offset: 0x34) Region Hash Area Start Address Register
Definition: component/icm.h:58
__I uint32_t ICM_UASR
(Icm Offset: 0x20) Undefined Access Status Register
Definition: component/icm.h:55
__IO uint32_t ICM_CFG
(Icm Offset: 0x00) Configuration Register
Definition: component/icm.h:47
__IO uint32_t ICM_DSCR
(Icm Offset: 0x30) Region Descriptor Area Start Address Register
Definition: component/icm.h:57
__I uint32_t ICM_IMR
(Icm Offset: 0x18) Interrupt Mask Register
Definition: component/icm.h:53
__O uint32_t ICM_IDR
(Icm Offset: 0x14) Interrupt Disable Register
Definition: component/icm.h:52
__O uint32_t ICM_CTRL
(Icm Offset: 0x04) Control Register
Definition: component/icm.h:48
__I uint32_t ICM_VERSION
(Icm Offset: 0xFC) Version Register
Definition: component/icm.h:64
__O uint32_t ICM_IER
(Icm Offset: 0x10) Interrupt Enable Register
Definition: component/icm.h:51
__I uint32_t ICM_ISR
(Icm Offset: 0x1C) Interrupt Status Register
Definition: component/icm.h:54
__I uint32_t ICM_FEATURES
(Icm Offset: 0xF8) Feature Register
Definition: component/icm.h:63
Icm hardware registers.
Definition: component/icm.h:46
#define __I
Definition: core_cm7.h:263
__I uint32_t ICM_ADDRSIZE
(Icm Offset: 0xEC) Address Size Register
Definition: component/icm.h:61


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autogenerated on Sat Sep 19 2020 03:19:04