25 #if defined ( __ICCARM__ )
26 #pragma system_include
27 #elif defined (__clang__)
28 #pragma clang system_header
31 #ifndef __CORE_SC300_H_GENERIC
32 #define __CORE_SC300_H_GENERIC
66 #define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
67 #define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
68 #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
69 __SC300_CMSIS_VERSION_SUB )
71 #define __CORTEX_SC (300U)
78 #if defined ( __CC_ARM )
79 #if defined __TARGET_FPU_VFP
80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
88 #elif defined ( __GNUC__ )
89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
93 #elif defined ( __ICCARM__ )
94 #if defined __ARMVFP__
95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
98 #elif defined ( __TI_ARM__ )
99 #if defined __TI_VFP_SUPPORT__
100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
103 #elif defined ( __TASKING__ )
104 #if defined __FPU_VFP__
105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
108 #elif defined ( __CSMC__ )
109 #if ( __CSMC__ & 0x400U)
110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
124 #ifndef __CMSIS_GENERIC
126 #ifndef __CORE_SC300_H_DEPENDANT
127 #define __CORE_SC300_H_DEPENDANT
134 #if defined __CHECK_DEVICE_DEFINES
136 #define __SC300_REV 0x0000U
137 #warning "__SC300_REV not defined in device header file; using default!"
140 #ifndef __MPU_PRESENT
141 #define __MPU_PRESENT 0U
142 #warning "__MPU_PRESENT not defined in device header file; using default!"
145 #ifndef __NVIC_PRIO_BITS
146 #define __NVIC_PRIO_BITS 3U
147 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
150 #ifndef __Vendor_SysTickConfig
151 #define __Vendor_SysTickConfig 0U
152 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
167 #define __I volatile const
170 #define __IO volatile
173 #define __IM volatile const
174 #define __OM volatile
175 #define __IOM volatile
221 #define APSR_N_Pos 31U
222 #define APSR_N_Msk (1UL << APSR_N_Pos)
224 #define APSR_Z_Pos 30U
225 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
227 #define APSR_C_Pos 29U
228 #define APSR_C_Msk (1UL << APSR_C_Pos)
230 #define APSR_V_Pos 28U
231 #define APSR_V_Msk (1UL << APSR_V_Pos)
233 #define APSR_Q_Pos 27U
234 #define APSR_Q_Msk (1UL << APSR_Q_Pos)
251 #define IPSR_ISR_Pos 0U
252 #define IPSR_ISR_Msk (0x1FFUL )
278 #define xPSR_N_Pos 31U
279 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
281 #define xPSR_Z_Pos 30U
282 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
284 #define xPSR_C_Pos 29U
285 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
287 #define xPSR_V_Pos 28U
288 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
290 #define xPSR_Q_Pos 27U
291 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
293 #define xPSR_ICI_IT_2_Pos 25U
294 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)
296 #define xPSR_T_Pos 24U
297 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
299 #define xPSR_ICI_IT_1_Pos 10U
300 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)
302 #define xPSR_ISR_Pos 0U
303 #define xPSR_ISR_Msk (0x1FFUL )
321 #define CONTROL_SPSEL_Pos 1U
322 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
324 #define CONTROL_nPRIV_Pos 0U
325 #define CONTROL_nPRIV_Msk (1UL )
342 __IOM uint32_t ISER[8U];
343 uint32_t RESERVED0[24U];
344 __IOM uint32_t ICER[8U];
345 uint32_t RESERVED1[24U];
346 __IOM uint32_t ISPR[8U];
347 uint32_t RESERVED2[24U];
348 __IOM uint32_t ICPR[8U];
349 uint32_t RESERVED3[24U];
350 __IOM uint32_t IABR[8U];
351 uint32_t RESERVED4[56U];
352 __IOM uint8_t IP[240U];
353 uint32_t RESERVED5[644U];
358 #define NVIC_STIR_INTID_Pos 0U
359 #define NVIC_STIR_INTID_Msk (0x1FFUL )
379 __IOM uint32_t AIRCR;
382 __IOM uint8_t SHP[12U];
383 __IOM uint32_t SHCSR;
387 __IOM uint32_t MMFAR;
390 __IM uint32_t PFR[2U];
393 __IM uint32_t MMFR[4U];
394 __IM uint32_t ISAR[5U];
395 uint32_t RESERVED0[5U];
396 __IOM uint32_t CPACR;
397 uint32_t RESERVED1[129U];
402 #define SCB_CPUID_IMPLEMENTER_Pos 24U
403 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
405 #define SCB_CPUID_VARIANT_Pos 20U
406 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
408 #define SCB_CPUID_ARCHITECTURE_Pos 16U
409 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
411 #define SCB_CPUID_PARTNO_Pos 4U
412 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
414 #define SCB_CPUID_REVISION_Pos 0U
415 #define SCB_CPUID_REVISION_Msk (0xFUL )
418 #define SCB_ICSR_NMIPENDSET_Pos 31U
419 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
421 #define SCB_ICSR_PENDSVSET_Pos 28U
422 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
424 #define SCB_ICSR_PENDSVCLR_Pos 27U
425 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
427 #define SCB_ICSR_PENDSTSET_Pos 26U
428 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
430 #define SCB_ICSR_PENDSTCLR_Pos 25U
431 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
433 #define SCB_ICSR_ISRPREEMPT_Pos 23U
434 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
436 #define SCB_ICSR_ISRPENDING_Pos 22U
437 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
439 #define SCB_ICSR_VECTPENDING_Pos 12U
440 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
442 #define SCB_ICSR_RETTOBASE_Pos 11U
443 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
445 #define SCB_ICSR_VECTACTIVE_Pos 0U
446 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL )
449 #define SCB_VTOR_TBLBASE_Pos 29U
450 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos)
452 #define SCB_VTOR_TBLOFF_Pos 7U
453 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)
456 #define SCB_AIRCR_VECTKEY_Pos 16U
457 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
459 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
460 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
462 #define SCB_AIRCR_ENDIANESS_Pos 15U
463 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
465 #define SCB_AIRCR_PRIGROUP_Pos 8U
466 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
468 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
469 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
471 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
472 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
474 #define SCB_AIRCR_VECTRESET_Pos 0U
475 #define SCB_AIRCR_VECTRESET_Msk (1UL )
478 #define SCB_SCR_SEVONPEND_Pos 4U
479 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
481 #define SCB_SCR_SLEEPDEEP_Pos 2U
482 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
484 #define SCB_SCR_SLEEPONEXIT_Pos 1U
485 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
488 #define SCB_CCR_STKALIGN_Pos 9U
489 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
491 #define SCB_CCR_BFHFNMIGN_Pos 8U
492 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
494 #define SCB_CCR_DIV_0_TRP_Pos 4U
495 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
497 #define SCB_CCR_UNALIGN_TRP_Pos 3U
498 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
500 #define SCB_CCR_USERSETMPEND_Pos 1U
501 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
503 #define SCB_CCR_NONBASETHRDENA_Pos 0U
504 #define SCB_CCR_NONBASETHRDENA_Msk (1UL )
507 #define SCB_SHCSR_USGFAULTENA_Pos 18U
508 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
510 #define SCB_SHCSR_BUSFAULTENA_Pos 17U
511 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
513 #define SCB_SHCSR_MEMFAULTENA_Pos 16U
514 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
516 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
517 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
519 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
520 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
522 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
523 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
525 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U
526 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
528 #define SCB_SHCSR_SYSTICKACT_Pos 11U
529 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
531 #define SCB_SHCSR_PENDSVACT_Pos 10U
532 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
534 #define SCB_SHCSR_MONITORACT_Pos 8U
535 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
537 #define SCB_SHCSR_SVCALLACT_Pos 7U
538 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
540 #define SCB_SHCSR_USGFAULTACT_Pos 3U
541 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
543 #define SCB_SHCSR_BUSFAULTACT_Pos 1U
544 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
546 #define SCB_SHCSR_MEMFAULTACT_Pos 0U
547 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL )
550 #define SCB_CFSR_USGFAULTSR_Pos 16U
551 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
553 #define SCB_CFSR_BUSFAULTSR_Pos 8U
554 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
556 #define SCB_CFSR_MEMFAULTSR_Pos 0U
557 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL )
560 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
561 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)
563 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
564 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)
566 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
567 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)
569 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
570 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)
572 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
573 #define SCB_CFSR_IACCVIOL_Msk (1UL )
576 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)
577 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)
579 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)
580 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)
582 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)
583 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)
585 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)
586 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)
588 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)
589 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)
591 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)
592 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)
595 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)
596 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)
598 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)
599 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)
601 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)
602 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)
604 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)
605 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)
607 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)
608 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)
610 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)
611 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)
614 #define SCB_HFSR_DEBUGEVT_Pos 31U
615 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
617 #define SCB_HFSR_FORCED_Pos 30U
618 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
620 #define SCB_HFSR_VECTTBL_Pos 1U
621 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
624 #define SCB_DFSR_EXTERNAL_Pos 4U
625 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
627 #define SCB_DFSR_VCATCH_Pos 3U
628 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
630 #define SCB_DFSR_DWTTRAP_Pos 2U
631 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
633 #define SCB_DFSR_BKPT_Pos 1U
634 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
636 #define SCB_DFSR_HALTED_Pos 0U
637 #define SCB_DFSR_HALTED_Msk (1UL )
654 uint32_t RESERVED0[1U];
656 __IOM uint32_t ACTLR;
660 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U
661 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL )
664 #define SCnSCB_ACTLR_DISFOLD_Pos 2U
665 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
667 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U
668 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)
670 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U
671 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL )
695 #define SysTick_CTRL_COUNTFLAG_Pos 16U
696 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
698 #define SysTick_CTRL_CLKSOURCE_Pos 2U
699 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
701 #define SysTick_CTRL_TICKINT_Pos 1U
702 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
704 #define SysTick_CTRL_ENABLE_Pos 0U
705 #define SysTick_CTRL_ENABLE_Msk (1UL )
708 #define SysTick_LOAD_RELOAD_Pos 0U
709 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )
712 #define SysTick_VAL_CURRENT_Pos 0U
713 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL )
716 #define SysTick_CALIB_NOREF_Pos 31U
717 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
719 #define SysTick_CALIB_SKEW_Pos 30U
720 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
722 #define SysTick_CALIB_TENMS_Pos 0U
723 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL )
746 uint32_t RESERVED0[864U];
748 uint32_t RESERVED1[15U];
750 uint32_t RESERVED2[15U];
752 uint32_t RESERVED3[32U];
753 uint32_t RESERVED4[43U];
756 uint32_t RESERVED5[6U];
772 #define ITM_TPR_PRIVMASK_Pos 0U
773 #define ITM_TPR_PRIVMASK_Msk (0xFUL )
776 #define ITM_TCR_BUSY_Pos 23U
777 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
779 #define ITM_TCR_TraceBusID_Pos 16U
780 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)
782 #define ITM_TCR_GTSFREQ_Pos 10U
783 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
785 #define ITM_TCR_TSPrescale_Pos 8U
786 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)
788 #define ITM_TCR_SWOENA_Pos 4U
789 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
791 #define ITM_TCR_DWTENA_Pos 3U
792 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
794 #define ITM_TCR_SYNCENA_Pos 2U
795 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
797 #define ITM_TCR_TSENA_Pos 1U
798 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
800 #define ITM_TCR_ITMENA_Pos 0U
801 #define ITM_TCR_ITMENA_Msk (1UL )
804 #define ITM_LSR_ByteAcc_Pos 2U
805 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
807 #define ITM_LSR_Access_Pos 1U
808 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
810 #define ITM_LSR_Present_Pos 0U
811 #define ITM_LSR_Present_Msk (1UL )
829 __IOM uint32_t CYCCNT;
830 __IOM uint32_t CPICNT;
831 __IOM uint32_t EXCCNT;
832 __IOM uint32_t SLEEPCNT;
833 __IOM uint32_t LSUCNT;
834 __IOM uint32_t FOLDCNT;
836 __IOM uint32_t COMP0;
837 __IOM uint32_t MASK0;
838 __IOM uint32_t FUNCTION0;
839 uint32_t RESERVED0[1U];
841 __IOM uint32_t MASK1;
842 __IOM uint32_t FUNCTION1;
843 uint32_t RESERVED1[1U];
845 __IOM uint32_t MASK2;
846 __IOM uint32_t FUNCTION2;
847 uint32_t RESERVED2[1U];
848 __IOM uint32_t COMP3;
849 __IOM uint32_t MASK3;
850 __IOM uint32_t FUNCTION3;
854 #define DWT_CTRL_NUMCOMP_Pos 28U
855 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
857 #define DWT_CTRL_NOTRCPKT_Pos 27U
858 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
860 #define DWT_CTRL_NOEXTTRIG_Pos 26U
861 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
863 #define DWT_CTRL_NOCYCCNT_Pos 25U
864 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
866 #define DWT_CTRL_NOPRFCNT_Pos 24U
867 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
869 #define DWT_CTRL_CYCEVTENA_Pos 22U
870 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
872 #define DWT_CTRL_FOLDEVTENA_Pos 21U
873 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
875 #define DWT_CTRL_LSUEVTENA_Pos 20U
876 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
878 #define DWT_CTRL_SLEEPEVTENA_Pos 19U
879 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
881 #define DWT_CTRL_EXCEVTENA_Pos 18U
882 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
884 #define DWT_CTRL_CPIEVTENA_Pos 17U
885 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
887 #define DWT_CTRL_EXCTRCENA_Pos 16U
888 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
890 #define DWT_CTRL_PCSAMPLENA_Pos 12U
891 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
893 #define DWT_CTRL_SYNCTAP_Pos 10U
894 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
896 #define DWT_CTRL_CYCTAP_Pos 9U
897 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
899 #define DWT_CTRL_POSTINIT_Pos 5U
900 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
902 #define DWT_CTRL_POSTPRESET_Pos 1U
903 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
905 #define DWT_CTRL_CYCCNTENA_Pos 0U
906 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL )
909 #define DWT_CPICNT_CPICNT_Pos 0U
910 #define DWT_CPICNT_CPICNT_Msk (0xFFUL )
913 #define DWT_EXCCNT_EXCCNT_Pos 0U
914 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL )
917 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
918 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL )
921 #define DWT_LSUCNT_LSUCNT_Pos 0U
922 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL )
925 #define DWT_FOLDCNT_FOLDCNT_Pos 0U
926 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL )
929 #define DWT_MASK_MASK_Pos 0U
930 #define DWT_MASK_MASK_Msk (0x1FUL )
933 #define DWT_FUNCTION_MATCHED_Pos 24U
934 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
936 #define DWT_FUNCTION_DATAVADDR1_Pos 16U
937 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
939 #define DWT_FUNCTION_DATAVADDR0_Pos 12U
940 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
942 #define DWT_FUNCTION_DATAVSIZE_Pos 10U
943 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
945 #define DWT_FUNCTION_LNK1ENA_Pos 9U
946 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
948 #define DWT_FUNCTION_DATAVMATCH_Pos 8U
949 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
951 #define DWT_FUNCTION_CYCMATCH_Pos 7U
952 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
954 #define DWT_FUNCTION_EMITRANGE_Pos 5U
955 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
957 #define DWT_FUNCTION_FUNCTION_Pos 0U
958 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL )
976 __IOM uint32_t CSPSR;
977 uint32_t RESERVED0[2U];
979 uint32_t RESERVED1[55U];
981 uint32_t RESERVED2[131U];
985 uint32_t RESERVED3[759U];
986 __IM uint32_t TRIGGER;
988 __IM uint32_t ITATBCTR2;
989 uint32_t RESERVED4[1U];
990 __IM uint32_t ITATBCTR0;
992 __IOM uint32_t ITCTRL;
993 uint32_t RESERVED5[39U];
994 __IOM uint32_t CLAIMSET;
995 __IOM uint32_t CLAIMCLR;
996 uint32_t RESERVED7[8U];
998 __IM uint32_t DEVTYPE;
1002 #define TPI_ACPR_PRESCALER_Pos 0U
1003 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL )
1006 #define TPI_SPPR_TXMODE_Pos 0U
1007 #define TPI_SPPR_TXMODE_Msk (0x3UL )
1010 #define TPI_FFSR_FtNonStop_Pos 3U
1011 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1013 #define TPI_FFSR_TCPresent_Pos 2U
1014 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1016 #define TPI_FFSR_FtStopped_Pos 1U
1017 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1019 #define TPI_FFSR_FlInProg_Pos 0U
1020 #define TPI_FFSR_FlInProg_Msk (0x1UL )
1023 #define TPI_FFCR_TrigIn_Pos 8U
1024 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1026 #define TPI_FFCR_EnFCont_Pos 1U
1027 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1030 #define TPI_TRIGGER_TRIGGER_Pos 0U
1031 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL )
1034 #define TPI_FIFO0_ITM_ATVALID_Pos 29U
1035 #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)
1037 #define TPI_FIFO0_ITM_bytecount_Pos 27U
1038 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
1040 #define TPI_FIFO0_ETM_ATVALID_Pos 26U
1041 #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)
1043 #define TPI_FIFO0_ETM_bytecount_Pos 24U
1044 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
1046 #define TPI_FIFO0_ETM2_Pos 16U
1047 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
1049 #define TPI_FIFO0_ETM1_Pos 8U
1050 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
1052 #define TPI_FIFO0_ETM0_Pos 0U
1053 #define TPI_FIFO0_ETM0_Msk (0xFFUL )
1056 #define TPI_ITATBCTR2_ATREADY2_Pos 0U
1057 #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL )
1059 #define TPI_ITATBCTR2_ATREADY1_Pos 0U
1060 #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL )
1063 #define TPI_FIFO1_ITM_ATVALID_Pos 29U
1064 #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)
1066 #define TPI_FIFO1_ITM_bytecount_Pos 27U
1067 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
1069 #define TPI_FIFO1_ETM_ATVALID_Pos 26U
1070 #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)
1072 #define TPI_FIFO1_ETM_bytecount_Pos 24U
1073 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
1075 #define TPI_FIFO1_ITM2_Pos 16U
1076 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
1078 #define TPI_FIFO1_ITM1_Pos 8U
1079 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
1081 #define TPI_FIFO1_ITM0_Pos 0U
1082 #define TPI_FIFO1_ITM0_Msk (0xFFUL )
1085 #define TPI_ITATBCTR0_ATREADY2_Pos 0U
1086 #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL )
1088 #define TPI_ITATBCTR0_ATREADY1_Pos 0U
1089 #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL )
1092 #define TPI_ITCTRL_Mode_Pos 0U
1093 #define TPI_ITCTRL_Mode_Msk (0x3UL )
1096 #define TPI_DEVID_NRZVALID_Pos 11U
1097 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1099 #define TPI_DEVID_MANCVALID_Pos 10U
1100 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1102 #define TPI_DEVID_PTINVALID_Pos 9U
1103 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1105 #define TPI_DEVID_MinBufSz_Pos 6U
1106 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
1108 #define TPI_DEVID_AsynClkIn_Pos 5U
1109 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
1111 #define TPI_DEVID_NrTraceInput_Pos 0U
1112 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL )
1115 #define TPI_DEVTYPE_SubType_Pos 4U
1116 #define TPI_DEVTYPE_SubType_Msk (0xFUL )
1118 #define TPI_DEVTYPE_MajorType_Pos 0U
1119 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
1124 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1138 __IOM uint32_t CTRL;
1140 __IOM uint32_t RBAR;
1141 __IOM uint32_t RASR;
1142 __IOM uint32_t RBAR_A1;
1143 __IOM uint32_t RASR_A1;
1144 __IOM uint32_t RBAR_A2;
1145 __IOM uint32_t RASR_A2;
1146 __IOM uint32_t RBAR_A3;
1147 __IOM uint32_t RASR_A3;
1151 #define MPU_TYPE_IREGION_Pos 16U
1152 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1154 #define MPU_TYPE_DREGION_Pos 8U
1155 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1157 #define MPU_TYPE_SEPARATE_Pos 0U
1158 #define MPU_TYPE_SEPARATE_Msk (1UL )
1161 #define MPU_CTRL_PRIVDEFENA_Pos 2U
1162 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1164 #define MPU_CTRL_HFNMIENA_Pos 1U
1165 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1167 #define MPU_CTRL_ENABLE_Pos 0U
1168 #define MPU_CTRL_ENABLE_Msk (1UL )
1171 #define MPU_RNR_REGION_Pos 0U
1172 #define MPU_RNR_REGION_Msk (0xFFUL )
1175 #define MPU_RBAR_ADDR_Pos 5U
1176 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
1178 #define MPU_RBAR_VALID_Pos 4U
1179 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
1181 #define MPU_RBAR_REGION_Pos 0U
1182 #define MPU_RBAR_REGION_Msk (0xFUL )
1185 #define MPU_RASR_ATTRS_Pos 16U
1186 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
1188 #define MPU_RASR_XN_Pos 28U
1189 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
1191 #define MPU_RASR_AP_Pos 24U
1192 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
1194 #define MPU_RASR_TEX_Pos 19U
1195 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
1197 #define MPU_RASR_S_Pos 18U
1198 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
1200 #define MPU_RASR_C_Pos 17U
1201 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
1203 #define MPU_RASR_B_Pos 16U
1204 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
1206 #define MPU_RASR_SRD_Pos 8U
1207 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
1209 #define MPU_RASR_SIZE_Pos 1U
1210 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
1212 #define MPU_RASR_ENABLE_Pos 0U
1213 #define MPU_RASR_ENABLE_Msk (1UL )
1231 __IOM uint32_t DHCSR;
1232 __OM uint32_t DCRSR;
1233 __IOM uint32_t DCRDR;
1234 __IOM uint32_t DEMCR;
1238 #define CoreDebug_DHCSR_DBGKEY_Pos 16U
1239 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1241 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1242 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1244 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1245 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1247 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1248 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1250 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1251 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1253 #define CoreDebug_DHCSR_S_HALT_Pos 17U
1254 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1256 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1257 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1259 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
1260 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1262 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1263 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1265 #define CoreDebug_DHCSR_C_STEP_Pos 2U
1266 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1268 #define CoreDebug_DHCSR_C_HALT_Pos 1U
1269 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1271 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1272 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL )
1275 #define CoreDebug_DCRSR_REGWnR_Pos 16U
1276 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1278 #define CoreDebug_DCRSR_REGSEL_Pos 0U
1279 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL )
1282 #define CoreDebug_DEMCR_TRCENA_Pos 24U
1283 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1285 #define CoreDebug_DEMCR_MON_REQ_Pos 19U
1286 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1288 #define CoreDebug_DEMCR_MON_STEP_Pos 18U
1289 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1291 #define CoreDebug_DEMCR_MON_PEND_Pos 17U
1292 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1294 #define CoreDebug_DEMCR_MON_EN_Pos 16U
1295 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1297 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1298 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1300 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U
1301 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1303 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U
1304 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1306 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U
1307 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1309 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U
1310 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1312 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
1313 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1315 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U
1316 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1318 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1319 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL )
1337 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1345 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1358 #define SCS_BASE (0xE000E000UL)
1359 #define ITM_BASE (0xE0000000UL)
1360 #define DWT_BASE (0xE0001000UL)
1361 #define TPI_BASE (0xE0040000UL)
1362 #define CoreDebug_BASE (0xE000EDF0UL)
1363 #define SysTick_BASE (SCS_BASE + 0x0010UL)
1364 #define NVIC_BASE (SCS_BASE + 0x0100UL)
1365 #define SCB_BASE (SCS_BASE + 0x0D00UL)
1367 #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
1368 #define SCB ((SCB_Type *) SCB_BASE )
1369 #define SysTick ((SysTick_Type *) SysTick_BASE )
1370 #define NVIC ((NVIC_Type *) NVIC_BASE )
1371 #define ITM ((ITM_Type *) ITM_BASE )
1372 #define DWT ((DWT_Type *) DWT_BASE )
1373 #define TPI ((TPI_Type *) TPI_BASE )
1374 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
1376 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1377 #define MPU_BASE (SCS_BASE + 0x0D90UL)
1378 #define MPU ((MPU_Type *) MPU_BASE )
1407 #ifdef CMSIS_NVIC_VIRTUAL
1408 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1409 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1411 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1413 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1414 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1415 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1416 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1417 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1418 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1419 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1420 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1421 #define NVIC_GetActive __NVIC_GetActive
1422 #define NVIC_SetPriority __NVIC_SetPriority
1423 #define NVIC_GetPriority __NVIC_GetPriority
1424 #define NVIC_SystemReset __NVIC_SystemReset
1427 #ifdef CMSIS_VECTAB_VIRTUAL
1428 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1429 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1431 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1433 #define NVIC_SetVector __NVIC_SetVector
1434 #define NVIC_GetVector __NVIC_GetVector
1437 #define NVIC_USER_IRQ_OFFSET 16
1441 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL)
1442 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL)
1443 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL)
1458 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
1460 reg_value =
SCB->AIRCR;
1462 reg_value = (reg_value |
1465 SCB->AIRCR = reg_value;
1488 if ((int32_t)(
IRQn) >= 0)
1491 NVIC->ISER[(((uint32_t)
IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)
IRQn) & 0x1FUL));
1507 if ((int32_t)(
IRQn) >= 0)
1509 return((uint32_t)(((
NVIC->ISER[(((uint32_t)
IRQn) >> 5UL)] & (1UL << (((uint32_t)
IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1526 if ((int32_t)(
IRQn) >= 0)
1528 NVIC->ICER[(((uint32_t)
IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)
IRQn) & 0x1FUL));
1545 if ((int32_t)(
IRQn) >= 0)
1547 return((uint32_t)(((
NVIC->ISPR[(((uint32_t)
IRQn) >> 5UL)] & (1UL << (((uint32_t)
IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1564 if ((int32_t)(
IRQn) >= 0)
1566 NVIC->ISPR[(((uint32_t)
IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)
IRQn) & 0x1FUL));
1579 if ((int32_t)(
IRQn) >= 0)
1581 NVIC->ICPR[(((uint32_t)
IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)
IRQn) & 0x1FUL));
1596 if ((int32_t)(
IRQn) >= 0)
1598 return((uint32_t)(((
NVIC->IABR[(((uint32_t)
IRQn) >> 5UL)] & (1UL << (((uint32_t)
IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1618 if ((int32_t)(
IRQn) >= 0)
1624 SCB->SHP[(((uint32_t)
IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U -
__NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1641 if ((int32_t)(
IRQn) >= 0)
1665 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
1666 uint32_t PreemptPriorityBits;
1667 uint32_t SubPriorityBits;
1670 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(
__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(
__NVIC_PRIO_BITS));
1673 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1674 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1692 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
1693 uint32_t PreemptPriorityBits;
1694 uint32_t SubPriorityBits;
1697 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(
__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(
__NVIC_PRIO_BITS));
1699 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1700 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1715 uint32_t vectors = (uint32_t )
SCB->VTOR;
1731 uint32_t vectors = (uint32_t )
SCB->VTOR;
1792 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1812 SysTick->LOAD = (uint32_t)(ticks - 1UL);
1836 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
1847 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1850 ((
ITM->TER & 1UL ) != 0UL) )
1852 while (
ITM->PORT[0U].u32 == 0UL)
1856 ITM->PORT[0U].u8 = (uint8_t)ch;