Type definitions for the Trace Port Interface (TPI) More...

Collaboration diagram for Trace Port Interface (TPI):

Modules
	Floating Point Unit (FPU)
	Type definitions for the Floating Point Unit (FPU)

Classes
struct	TPI_Type
	Structure type to access the Trace Port Interface Register (TPI). More...

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_SWOSCALER_Pos 0U

#define	TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_PSCR_PSCount_Pos 0U

#define	TPI_PSCR_PSCount_Msk (0x1FUL /<< TPI_PSCR_PSCount_Pos/)

#define	TPI_LSR_nTT_Pos 1U

#define	TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)

#define	TPI_LSR_SLK_Pos 1U

#define	TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)

#define	TPI_LSR_SLI_Pos 0U

#define	TPI_LSR_SLI_Msk (0x1UL /<< TPI_LSR_SLI_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_SWOSCALER_Pos 0U

#define	TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_PSCR_PSCount_Pos 0U

#define	TPI_PSCR_PSCount_Msk (0x1FUL /<< TPI_PSCR_PSCount_Pos/)

#define	TPI_LSR_nTT_Pos 1U

#define	TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)

#define	TPI_LSR_SLK_Pos 1U

#define	TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)

#define	TPI_LSR_SLI_Pos 0U

#define	TPI_LSR_SLI_Msk (0x1UL /<< TPI_LSR_SLI_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data2_Pos 16U

#define	TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data1_Pos 8U

#define	TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data0_Pos 0U

#define	TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /<< TPI_ITFTTD0_ATB_IF1_data0_Pos/)

#define	TPI_ITATBCTR2_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)

#define	TPI_ITATBCTR2_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)

#define	TPI_ITATBCTR2_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2S_Pos/)

#define	TPI_ITATBCTR2_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1S_Pos/)

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data2_Pos 16U

#define	TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data1_Pos 8U

#define	TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data0_Pos 0U

#define	TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /<< TPI_ITFTTD1_ATB_IF2_data0_Pos/)

#define	TPI_ITATBCTR0_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)

#define	TPI_ITATBCTR0_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)

#define	TPI_ITATBCTR0_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2S_Pos/)

#define	TPI_ITATBCTR0_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1S_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x3FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data2_Pos 16U

#define	TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data1_Pos 8U

#define	TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data0_Pos 0U

#define	TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /<< TPI_ITFTTD0_ATB_IF1_data0_Pos/)

#define	TPI_ITATBCTR2_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)

#define	TPI_ITATBCTR2_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)

#define	TPI_ITATBCTR2_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2S_Pos/)

#define	TPI_ITATBCTR2_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1S_Pos/)

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data2_Pos 16U

#define	TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data1_Pos 8U

#define	TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data0_Pos 0U

#define	TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /<< TPI_ITFTTD1_ATB_IF2_data0_Pos/)

#define	TPI_ITATBCTR0_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)

#define	TPI_ITATBCTR0_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)

#define	TPI_ITATBCTR0_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2S_Pos/)

#define	TPI_ITATBCTR0_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1S_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x3FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_SWOSCALER_Pos 0U

#define	TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_PSCR_PSCount_Pos 0U

#define	TPI_PSCR_PSCount_Msk (0x1FUL /<< TPI_PSCR_PSCount_Pos/)

#define	TPI_LSR_nTT_Pos 1U

#define	TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)

#define	TPI_LSR_SLK_Pos 1U

#define	TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)

#define	TPI_LSR_SLI_Pos 0U

#define	TPI_LSR_SLI_Msk (0x1UL /<< TPI_LSR_SLI_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_SWOSCALER_Pos 0U

#define	TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_PSCR_PSCount_Pos 0U

#define	TPI_PSCR_PSCount_Msk (0x1FUL /<< TPI_PSCR_PSCount_Pos/)

#define	TPI_LSR_nTT_Pos 1U

#define	TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)

#define	TPI_LSR_SLK_Pos 1U

#define	TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)

#define	TPI_LSR_SLI_Pos 0U

#define	TPI_LSR_SLI_Msk (0x1UL /<< TPI_LSR_SLI_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data2_Pos 16U

#define	TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data1_Pos 8U

#define	TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data0_Pos 0U

#define	TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /<< TPI_ITFTTD0_ATB_IF1_data0_Pos/)

#define	TPI_ITATBCTR2_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)

#define	TPI_ITATBCTR2_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)

#define	TPI_ITATBCTR2_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2S_Pos/)

#define	TPI_ITATBCTR2_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1S_Pos/)

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data2_Pos 16U

#define	TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data1_Pos 8U

#define	TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data0_Pos 0U

#define	TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /<< TPI_ITFTTD1_ATB_IF2_data0_Pos/)

#define	TPI_ITATBCTR0_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)

#define	TPI_ITATBCTR0_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)

#define	TPI_ITATBCTR0_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2S_Pos/)

#define	TPI_ITATBCTR0_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1S_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x3FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data2_Pos 16U

#define	TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data1_Pos 8U

#define	TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data0_Pos 0U

#define	TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /<< TPI_ITFTTD0_ATB_IF1_data0_Pos/)

#define	TPI_ITATBCTR2_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)

#define	TPI_ITATBCTR2_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)

#define	TPI_ITATBCTR2_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2S_Pos/)

#define	TPI_ITATBCTR2_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1S_Pos/)

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data2_Pos 16U

#define	TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data1_Pos 8U

#define	TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data0_Pos 0U

#define	TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /<< TPI_ITFTTD1_ATB_IF2_data0_Pos/)

#define	TPI_ITATBCTR0_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)

#define	TPI_ITATBCTR0_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)

#define	TPI_ITATBCTR0_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2S_Pos/)

#define	TPI_ITATBCTR0_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1S_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x3FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_SWOSCALER_Pos 0U

#define	TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_PSCR_PSCount_Pos 0U

#define	TPI_PSCR_PSCount_Msk (0x1FUL /<< TPI_PSCR_PSCount_Pos/)

#define	TPI_LSR_nTT_Pos 1U

#define	TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)

#define	TPI_LSR_SLK_Pos 1U

#define	TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)

#define	TPI_LSR_SLI_Pos 0U

#define	TPI_LSR_SLI_Msk (0x1UL /<< TPI_LSR_SLI_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_SWOSCALER_Pos 0U

#define	TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_PSCR_PSCount_Pos 0U

#define	TPI_PSCR_PSCount_Msk (0x1FUL /<< TPI_PSCR_PSCount_Pos/)

#define	TPI_LSR_nTT_Pos 1U

#define	TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)

#define	TPI_LSR_SLK_Pos 1U

#define	TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)

#define	TPI_LSR_SLI_Pos 0U

#define	TPI_LSR_SLI_Msk (0x1UL /<< TPI_LSR_SLI_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data2_Pos 16U

#define	TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data1_Pos 8U

#define	TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data0_Pos 0U

#define	TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /<< TPI_ITFTTD0_ATB_IF1_data0_Pos/)

#define	TPI_ITATBCTR2_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)

#define	TPI_ITATBCTR2_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)

#define	TPI_ITATBCTR2_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2S_Pos/)

#define	TPI_ITATBCTR2_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1S_Pos/)

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data2_Pos 16U

#define	TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data1_Pos 8U

#define	TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data0_Pos 0U

#define	TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /<< TPI_ITFTTD1_ATB_IF2_data0_Pos/)

#define	TPI_ITATBCTR0_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)

#define	TPI_ITATBCTR0_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)

#define	TPI_ITATBCTR0_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2S_Pos/)

#define	TPI_ITATBCTR0_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1S_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x3FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data2_Pos 16U

#define	TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data1_Pos 8U

#define	TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data0_Pos 0U

#define	TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /<< TPI_ITFTTD0_ATB_IF1_data0_Pos/)

#define	TPI_ITATBCTR2_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)

#define	TPI_ITATBCTR2_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)

#define	TPI_ITATBCTR2_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2S_Pos/)

#define	TPI_ITATBCTR2_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1S_Pos/)

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data2_Pos 16U

#define	TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data1_Pos 8U

#define	TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data0_Pos 0U

#define	TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /<< TPI_ITFTTD1_ATB_IF2_data0_Pos/)

#define	TPI_ITATBCTR0_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)

#define	TPI_ITATBCTR0_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)

#define	TPI_ITATBCTR0_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2S_Pos/)

#define	TPI_ITATBCTR0_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1S_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x3FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY_Pos 0U

#define	TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY_Pos 0U

#define	TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 4U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_DEVTYPE_SubType_Pos 0U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_ACPR_SWOSCALER_Pos 0U

#define	TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_PSCR_PSCount_Pos 0U

#define	TPI_PSCR_PSCount_Msk (0x1FUL /<< TPI_PSCR_PSCount_Pos/)

#define	TPI_LSR_nTT_Pos 1U

#define	TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)

#define	TPI_LSR_SLK_Pos 1U

#define	TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)

#define	TPI_LSR_SLI_Pos 0U

#define	TPI_LSR_SLI_Msk (0x1UL /<< TPI_LSR_SLI_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_SWOSCALER_Pos 0U

#define	TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_PSCR_PSCount_Pos 0U

#define	TPI_PSCR_PSCount_Msk (0x1FUL /<< TPI_PSCR_PSCount_Pos/)

#define	TPI_LSR_nTT_Pos 1U

#define	TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)

#define	TPI_LSR_SLK_Pos 1U

#define	TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)

#define	TPI_LSR_SLI_Pos 0U

#define	TPI_LSR_SLI_Msk (0x1UL /<< TPI_LSR_SLI_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data2_Pos 16U

#define	TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data1_Pos 8U

#define	TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data0_Pos 0U

#define	TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /<< TPI_ITFTTD0_ATB_IF1_data0_Pos/)

#define	TPI_ITATBCTR2_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)

#define	TPI_ITATBCTR2_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)

#define	TPI_ITATBCTR2_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2S_Pos/)

#define	TPI_ITATBCTR2_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1S_Pos/)

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data2_Pos 16U

#define	TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data1_Pos 8U

#define	TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data0_Pos 0U

#define	TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /<< TPI_ITFTTD1_ATB_IF2_data0_Pos/)

#define	TPI_ITATBCTR0_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)

#define	TPI_ITATBCTR0_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)

#define	TPI_ITATBCTR0_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2S_Pos/)

#define	TPI_ITATBCTR0_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1S_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x3FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data2_Pos 16U

#define	TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data1_Pos 8U

#define	TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data0_Pos 0U

#define	TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /<< TPI_ITFTTD0_ATB_IF1_data0_Pos/)

#define	TPI_ITATBCTR2_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)

#define	TPI_ITATBCTR2_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)

#define	TPI_ITATBCTR2_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2S_Pos/)

#define	TPI_ITATBCTR2_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1S_Pos/)

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data2_Pos 16U

#define	TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data1_Pos 8U

#define	TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data0_Pos 0U

#define	TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /<< TPI_ITFTTD1_ATB_IF2_data0_Pos/)

#define	TPI_ITATBCTR0_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)

#define	TPI_ITATBCTR0_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)

#define	TPI_ITATBCTR0_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2S_Pos/)

#define	TPI_ITATBCTR0_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1S_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x3FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data2_Pos 16U

#define	TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data1_Pos 8U

#define	TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data0_Pos 0U

#define	TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /<< TPI_ITFTTD0_ATB_IF1_data0_Pos/)

#define	TPI_ITATBCTR2_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)

#define	TPI_ITATBCTR2_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)

#define	TPI_ITATBCTR2_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2S_Pos/)

#define	TPI_ITATBCTR2_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1S_Pos/)

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data2_Pos 16U

#define	TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data1_Pos 8U

#define	TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data0_Pos 0U

#define	TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /<< TPI_ITFTTD1_ATB_IF2_data0_Pos/)

#define	TPI_ITATBCTR0_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)

#define	TPI_ITATBCTR0_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)

#define	TPI_ITATBCTR0_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2S_Pos/)

#define	TPI_ITATBCTR0_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1S_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x3FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

Detailed Description

Type definitions for the Trace Port Interface (TPI)

Macro Definition Documentation

◆ TPI_ACPR_PRESCALER_Msk [1/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 755 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_ACPR_PRESCALER_Msk [2/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 755 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_ACPR_PRESCALER_Msk [3/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 755 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_ACPR_PRESCALER_Msk [4/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 755 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_ACPR_PRESCALER_Msk [5/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1003 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_ACPR_PRESCALER_Msk [6/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1008 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_ACPR_PRESCALER_Msk [7/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1008 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_ACPR_PRESCALER_Msk [8/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1008 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_ACPR_PRESCALER_Msk [9/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1018 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_ACPR_PRESCALER_Msk [10/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1026 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_ACPR_PRESCALER_Msk [11/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1026 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_ACPR_PRESCALER_Msk [12/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1026 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_ACPR_PRESCALER_Msk [13/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1076 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_ACPR_PRESCALER_Msk [14/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1091 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_ACPR_PRESCALER_Msk [15/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1091 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_ACPR_PRESCALER_Msk [16/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1091 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_ACPR_PRESCALER_Msk [17/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1091 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_ACPR_PRESCALER_Msk [18/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1091 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_ACPR_PRESCALER_Msk [19/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1296 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_ACPR_PRESCALER_Msk [20/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1296 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_ACPR_PRESCALER_Msk [21/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1296 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_ACPR_PRESCALER_Msk [22/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1296 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_ACPR_PRESCALER_Msk [23/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1299 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_ACPR_PRESCALER_Msk [24/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1299 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ TPI_ACPR_PRESCALER_Msk [25/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1322 of file core_cm35p.h.

◆ TPI_ACPR_PRESCALER_Msk [26/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1322 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_ACPR_PRESCALER_Msk [27/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1417 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_ACPR_PRESCALER_Msk [28/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1417 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_ACPR_PRESCALER_Msk [29/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1417 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_ACPR_PRESCALER_Msk [30/30]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1418 of file core_armv81mml.h.

◆ TPI_ACPR_PRESCALER_Pos [1/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 754 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_ACPR_PRESCALER_Pos [2/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 754 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_ACPR_PRESCALER_Pos [3/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 754 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_ACPR_PRESCALER_Pos [4/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 754 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_ACPR_PRESCALER_Pos [5/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1002 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_ACPR_PRESCALER_Pos [6/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1007 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_ACPR_PRESCALER_Pos [7/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1007 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_ACPR_PRESCALER_Pos [8/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1007 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_ACPR_PRESCALER_Pos [9/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1017 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_ACPR_PRESCALER_Pos [10/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1025 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_ACPR_PRESCALER_Pos [11/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1025 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_ACPR_PRESCALER_Pos [12/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1025 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_ACPR_PRESCALER_Pos [13/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1075 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_ACPR_PRESCALER_Pos [14/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1090 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_ACPR_PRESCALER_Pos [15/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1090 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_ACPR_PRESCALER_Pos [16/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1090 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_ACPR_PRESCALER_Pos [17/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1090 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_ACPR_PRESCALER_Pos [18/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1090 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_ACPR_PRESCALER_Pos [19/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1295 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_ACPR_PRESCALER_Pos [20/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1295 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_ACPR_PRESCALER_Pos [21/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1295 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_ACPR_PRESCALER_Pos [22/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1295 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_ACPR_PRESCALER_Pos [23/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1298 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_ACPR_PRESCALER_Pos [24/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1298 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ TPI_ACPR_PRESCALER_Pos [25/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1321 of file core_cm35p.h.

◆ TPI_ACPR_PRESCALER_Pos [26/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1321 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_ACPR_PRESCALER_Pos [27/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1416 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_ACPR_PRESCALER_Pos [28/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1416 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_ACPR_PRESCALER_Pos [29/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1416 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_ACPR_PRESCALER_Pos [30/30]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1417 of file core_armv81mml.h.

◆ TPI_ACPR_SWOSCALER_Msk [1/8]

#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

Definition at line 747 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_ACPR_SWOSCALER_Msk [2/8]

#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

Definition at line 747 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_ACPR_SWOSCALER_Msk [3/8]

#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

Definition at line 747 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_ACPR_SWOSCALER_Msk [4/8]

#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

Definition at line 747 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_ACPR_SWOSCALER_Msk [5/8]

#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

Definition at line 1314 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_ACPR_SWOSCALER_Msk [6/8]

#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

Definition at line 1409 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_ACPR_SWOSCALER_Msk [7/8]

#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

Definition at line 1409 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_ACPR_SWOSCALER_Msk [8/8]

#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

Definition at line 1409 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_ACPR_SWOSCALER_Pos [1/8]

#define TPI_ACPR_SWOSCALER_Pos 0U

TPI ACPR: SWOSCALER Position

Definition at line 746 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_ACPR_SWOSCALER_Pos [2/8]

#define TPI_ACPR_SWOSCALER_Pos 0U

TPI ACPR: SWOSCALER Position

Definition at line 746 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_ACPR_SWOSCALER_Pos [3/8]

#define TPI_ACPR_SWOSCALER_Pos 0U

TPI ACPR: SWOSCALER Position

Definition at line 746 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_ACPR_SWOSCALER_Pos [4/8]

#define TPI_ACPR_SWOSCALER_Pos 0U

TPI ACPR: SWOSCALER Position

Definition at line 746 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_ACPR_SWOSCALER_Pos [5/8]

#define TPI_ACPR_SWOSCALER_Pos 0U

TPI ACPR: SWOSCALER Position

Definition at line 1313 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_ACPR_SWOSCALER_Pos [6/8]

#define TPI_ACPR_SWOSCALER_Pos 0U

TPI ACPR: SWOSCALER Position

Definition at line 1408 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_ACPR_SWOSCALER_Pos [7/8]

#define TPI_ACPR_SWOSCALER_Pos 0U

TPI ACPR: SWOSCALER Position

Definition at line 1408 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_ACPR_SWOSCALER_Pos [8/8]

#define TPI_ACPR_SWOSCALER_Pos 0U

TPI ACPR: SWOSCALER Position

Definition at line 1408 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_AsynClkIn_Msk [1/21]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1109 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_AsynClkIn_Msk [2/21]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1114 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_AsynClkIn_Msk [3/21]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1114 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_AsynClkIn_Msk [4/21]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1114 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_AsynClkIn_Msk [5/21]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1124 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_AsynClkIn_Msk [6/21]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1132 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_AsynClkIn_Msk [7/21]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1132 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_AsynClkIn_Msk [8/21]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1132 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_AsynClkIn_Msk [9/21]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1182 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_AsynClkIn_Msk [10/21]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1197 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_AsynClkIn_Msk [11/21]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1197 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_AsynClkIn_Msk [12/21]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1197 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_AsynClkIn_Msk [13/21]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1197 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_AsynClkIn_Msk [14/21]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1197 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_AsynClkIn_Msk [15/21]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1402 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_AsynClkIn_Msk [16/21]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1402 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_AsynClkIn_Msk [17/21]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1402 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_AsynClkIn_Msk [18/21]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1402 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_AsynClkIn_Msk [19/21]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1405 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_AsynClkIn_Msk [20/21]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1405 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ TPI_DEVID_AsynClkIn_Msk [21/21]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1518 of file core_armv81mml.h.

◆ TPI_DEVID_AsynClkIn_Pos [1/21]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1108 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_AsynClkIn_Pos [2/21]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1113 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_AsynClkIn_Pos [3/21]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1113 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_AsynClkIn_Pos [4/21]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1113 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_AsynClkIn_Pos [5/21]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1123 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_AsynClkIn_Pos [6/21]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1131 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_AsynClkIn_Pos [7/21]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1131 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_AsynClkIn_Pos [8/21]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1131 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_AsynClkIn_Pos [9/21]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1181 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_AsynClkIn_Pos [10/21]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1196 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_AsynClkIn_Pos [11/21]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1196 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_AsynClkIn_Pos [12/21]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1196 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_AsynClkIn_Pos [13/21]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1196 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_AsynClkIn_Pos [14/21]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1196 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_AsynClkIn_Pos [15/21]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1401 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_AsynClkIn_Pos [16/21]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1401 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_AsynClkIn_Pos [17/21]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1401 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_AsynClkIn_Pos [18/21]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1401 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_AsynClkIn_Pos [19/21]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1404 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ TPI_DEVID_AsynClkIn_Pos [20/21]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1404 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_AsynClkIn_Pos [21/21]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1517 of file core_armv81mml.h.

◆ TPI_DEVID_FIFOSZ_Msk [1/17]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask

Definition at line 801 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_FIFOSZ_Msk [2/17]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask

Definition at line 801 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_FIFOSZ_Msk [3/17]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask

Definition at line 801 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_FIFOSZ_Msk [4/17]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask

Definition at line 801 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_FIFOSZ_Msk [5/17]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFOSZ Mask

Definition at line 873 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_FIFOSZ_Msk [6/17]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFOSZ Mask

Definition at line 873 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_FIFOSZ_Msk [7/17]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFOSZ Mask

Definition at line 873 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_FIFOSZ_Msk [8/17]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFOSZ Mask

Definition at line 873 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_FIFOSZ_Msk [9/17]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask

Definition at line 1368 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_FIFOSZ_Msk [10/17]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFOSZ Mask

Definition at line 1440 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_FIFOSZ_Msk [11/17]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFOSZ Mask

Definition at line 1440 of file core_cm35p.h.

◆ TPI_DEVID_FIFOSZ_Msk [12/17]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask

Definition at line 1463 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_FIFOSZ_Msk [13/17]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask

Definition at line 1463 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_FIFOSZ_Msk [14/17]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask

Definition at line 1463 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_FIFOSZ_Msk [15/17]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFOSZ Mask

Definition at line 1535 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_FIFOSZ_Msk [16/17]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFOSZ Mask

Definition at line 1535 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_FIFOSZ_Msk [17/17]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFOSZ Mask

Definition at line 1535 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_FIFOSZ_Pos [1/17]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFO depth Position

Definition at line 800 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_FIFOSZ_Pos [2/17]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFO depth Position

Definition at line 800 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_FIFOSZ_Pos [3/17]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFO depth Position

Definition at line 800 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_FIFOSZ_Pos [4/17]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFO depth Position

Definition at line 800 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_FIFOSZ_Pos [5/17]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFOSZ Position

Definition at line 872 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_FIFOSZ_Pos [6/17]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFOSZ Position

Definition at line 872 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_FIFOSZ_Pos [7/17]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFOSZ Position

Definition at line 872 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_FIFOSZ_Pos [8/17]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFOSZ Position

Definition at line 872 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_FIFOSZ_Pos [9/17]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFO depth Position

Definition at line 1367 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_FIFOSZ_Pos [10/17]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFOSZ Position

Definition at line 1439 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_FIFOSZ_Pos [11/17]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFOSZ Position

Definition at line 1439 of file core_cm35p.h.

◆ TPI_DEVID_FIFOSZ_Pos [12/17]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFO depth Position

Definition at line 1462 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_FIFOSZ_Pos [13/17]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFO depth Position

Definition at line 1462 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_FIFOSZ_Pos [14/17]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFO depth Position

Definition at line 1462 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_FIFOSZ_Pos [15/17]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFOSZ Position

Definition at line 1534 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_FIFOSZ_Pos [16/17]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFOSZ Position

Definition at line 1534 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_FIFOSZ_Pos [17/17]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFOSZ Position

Definition at line 1534 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_MANCVALID_Msk [1/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 795 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_MANCVALID_Msk [2/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 795 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_MANCVALID_Msk [3/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 795 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_MANCVALID_Msk [4/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 795 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_MANCVALID_Msk [5/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 867 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_MANCVALID_Msk [6/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 867 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_MANCVALID_Msk [7/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 867 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_MANCVALID_Msk [8/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 867 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_MANCVALID_Msk [9/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1100 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_MANCVALID_Msk [10/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1105 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_MANCVALID_Msk [11/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1105 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_MANCVALID_Msk [12/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1105 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_MANCVALID_Msk [13/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1115 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_MANCVALID_Msk [14/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1123 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_MANCVALID_Msk [15/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1123 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_MANCVALID_Msk [16/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1123 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_MANCVALID_Msk [17/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1173 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_MANCVALID_Msk [18/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1188 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_MANCVALID_Msk [19/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1188 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_MANCVALID_Msk [20/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1188 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_MANCVALID_Msk [21/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1188 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_MANCVALID_Msk [22/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1188 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_MANCVALID_Msk [23/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1362 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_MANCVALID_Msk [24/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1393 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_MANCVALID_Msk [25/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1393 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_MANCVALID_Msk [26/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1393 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_MANCVALID_Msk [27/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1393 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_MANCVALID_Msk [28/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1396 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_MANCVALID_Msk [29/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1396 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ TPI_DEVID_MANCVALID_Msk [30/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1434 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_MANCVALID_Msk [31/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1434 of file core_cm35p.h.

◆ TPI_DEVID_MANCVALID_Msk [32/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1457 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_MANCVALID_Msk [33/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1457 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_MANCVALID_Msk [34/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1457 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_MANCVALID_Msk [35/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1509 of file core_armv81mml.h.

◆ TPI_DEVID_MANCVALID_Msk [36/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1529 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_MANCVALID_Msk [37/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1529 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_MANCVALID_Msk [38/38]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1529 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_MANCVALID_Pos [1/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 794 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_MANCVALID_Pos [2/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 794 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_MANCVALID_Pos [3/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 794 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_MANCVALID_Pos [4/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 794 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_MANCVALID_Pos [5/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 866 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_MANCVALID_Pos [6/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 866 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_MANCVALID_Pos [7/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 866 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_MANCVALID_Pos [8/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 866 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_MANCVALID_Pos [9/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1099 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_MANCVALID_Pos [10/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1104 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_MANCVALID_Pos [11/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1104 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_MANCVALID_Pos [12/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1104 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_MANCVALID_Pos [13/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1114 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_MANCVALID_Pos [14/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1122 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_MANCVALID_Pos [15/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1122 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_MANCVALID_Pos [16/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1122 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_MANCVALID_Pos [17/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1172 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_MANCVALID_Pos [18/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1187 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_MANCVALID_Pos [19/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1187 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_MANCVALID_Pos [20/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1187 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_MANCVALID_Pos [21/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1187 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_MANCVALID_Pos [22/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1187 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_MANCVALID_Pos [23/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1361 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_MANCVALID_Pos [24/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1392 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_MANCVALID_Pos [25/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1392 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_MANCVALID_Pos [26/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1392 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_MANCVALID_Pos [27/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1392 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_MANCVALID_Pos [28/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1395 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_MANCVALID_Pos [29/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1395 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ TPI_DEVID_MANCVALID_Pos [30/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1433 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_MANCVALID_Pos [31/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1433 of file core_cm35p.h.

◆ TPI_DEVID_MANCVALID_Pos [32/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1456 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_MANCVALID_Pos [33/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1456 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_MANCVALID_Pos [34/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1456 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_MANCVALID_Pos [35/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1508 of file core_armv81mml.h.

◆ TPI_DEVID_MANCVALID_Pos [36/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1528 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_MANCVALID_Pos [37/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1528 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_MANCVALID_Pos [38/38]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1528 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_MinBufSz_Msk [1/21]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1106 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_MinBufSz_Msk [2/21]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1111 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_MinBufSz_Msk [3/21]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1111 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_MinBufSz_Msk [4/21]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1111 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_MinBufSz_Msk [5/21]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1121 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_MinBufSz_Msk [6/21]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1129 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_MinBufSz_Msk [7/21]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1129 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_MinBufSz_Msk [8/21]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1129 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_MinBufSz_Msk [9/21]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1179 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_MinBufSz_Msk [10/21]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1194 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_MinBufSz_Msk [11/21]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1194 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_MinBufSz_Msk [12/21]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1194 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_MinBufSz_Msk [13/21]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1194 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_MinBufSz_Msk [14/21]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1194 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_MinBufSz_Msk [15/21]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1399 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_MinBufSz_Msk [16/21]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1399 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_MinBufSz_Msk [17/21]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1399 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_MinBufSz_Msk [18/21]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1399 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_MinBufSz_Msk [19/21]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1402 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ TPI_DEVID_MinBufSz_Msk [20/21]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1402 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_MinBufSz_Msk [21/21]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1515 of file core_armv81mml.h.

◆ TPI_DEVID_MinBufSz_Pos [1/21]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1105 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_MinBufSz_Pos [2/21]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1110 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_MinBufSz_Pos [3/21]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1110 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_MinBufSz_Pos [4/21]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1110 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_MinBufSz_Pos [5/21]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1120 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_MinBufSz_Pos [6/21]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1128 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_MinBufSz_Pos [7/21]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1128 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_MinBufSz_Pos [8/21]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1128 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_MinBufSz_Pos [9/21]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1178 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_MinBufSz_Pos [10/21]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1193 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_MinBufSz_Pos [11/21]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1193 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_MinBufSz_Pos [12/21]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1193 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_MinBufSz_Pos [13/21]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1193 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_MinBufSz_Pos [14/21]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1193 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_MinBufSz_Pos [15/21]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1398 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_MinBufSz_Pos [16/21]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1398 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_MinBufSz_Pos [17/21]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1398 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_MinBufSz_Pos [18/21]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1398 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_MinBufSz_Pos [19/21]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1401 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_MinBufSz_Pos [20/21]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1401 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ TPI_DEVID_MinBufSz_Pos [21/21]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1514 of file core_armv81mml.h.

◆ TPI_DEVID_NrTraceInput_Msk [1/30]

#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 876 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_NrTraceInput_Msk [2/30]

#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 876 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_NrTraceInput_Msk [3/30]

#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 876 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_NrTraceInput_Msk [4/30]

#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 876 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_NrTraceInput_Msk [5/30]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1112 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_NrTraceInput_Msk [6/30]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1117 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_NrTraceInput_Msk [7/30]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1117 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_NrTraceInput_Msk [8/30]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1117 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_NrTraceInput_Msk [9/30]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1127 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_NrTraceInput_Msk [10/30]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1135 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_NrTraceInput_Msk [11/30]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1135 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_NrTraceInput_Msk [12/30]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1135 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_NrTraceInput_Msk [13/30]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1185 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_NrTraceInput_Msk [14/30]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1200 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_NrTraceInput_Msk [15/30]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1200 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_NrTraceInput_Msk [16/30]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1200 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_NrTraceInput_Msk [17/30]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1200 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_NrTraceInput_Msk [18/30]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1200 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_NrTraceInput_Msk [19/30]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1405 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_NrTraceInput_Msk [20/30]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1405 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_NrTraceInput_Msk [21/30]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1405 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_NrTraceInput_Msk [22/30]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1405 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_NrTraceInput_Msk [23/30]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1408 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ TPI_DEVID_NrTraceInput_Msk [24/30]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1408 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_NrTraceInput_Msk [25/30]

#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1443 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_NrTraceInput_Msk [26/30]

#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1443 of file core_cm35p.h.

◆ TPI_DEVID_NrTraceInput_Msk [27/30]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1521 of file core_armv81mml.h.

◆ TPI_DEVID_NrTraceInput_Msk [28/30]

#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1538 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_NrTraceInput_Msk [29/30]

#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1538 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_NrTraceInput_Msk [30/30]

#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1538 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_NrTraceInput_Pos [1/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 875 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_NrTraceInput_Pos [2/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 875 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_NrTraceInput_Pos [3/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 875 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_NrTraceInput_Pos [4/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 875 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_NrTraceInput_Pos [5/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1111 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_NrTraceInput_Pos [6/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1116 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_NrTraceInput_Pos [7/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1116 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_NrTraceInput_Pos [8/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1116 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_NrTraceInput_Pos [9/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1126 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_NrTraceInput_Pos [10/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1134 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_NrTraceInput_Pos [11/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1134 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_NrTraceInput_Pos [12/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1134 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_NrTraceInput_Pos [13/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1184 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_NrTraceInput_Pos [14/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1199 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_NrTraceInput_Pos [15/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1199 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_NrTraceInput_Pos [16/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1199 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_NrTraceInput_Pos [17/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1199 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_NrTraceInput_Pos [18/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1199 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_NrTraceInput_Pos [19/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1404 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_NrTraceInput_Pos [20/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1404 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_NrTraceInput_Pos [21/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1404 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_NrTraceInput_Pos [22/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1404 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_NrTraceInput_Pos [23/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1407 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ TPI_DEVID_NrTraceInput_Pos [24/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1407 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_NrTraceInput_Pos [25/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1442 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_NrTraceInput_Pos [26/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1442 of file core_cm35p.h.

◆ TPI_DEVID_NrTraceInput_Pos [27/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1520 of file core_armv81mml.h.

◆ TPI_DEVID_NrTraceInput_Pos [28/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1537 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_NrTraceInput_Pos [29/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1537 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_NrTraceInput_Pos [30/30]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1537 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_NRZVALID_Msk [1/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 792 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_NRZVALID_Msk [2/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 792 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_NRZVALID_Msk [3/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 792 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_NRZVALID_Msk [4/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 792 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_NRZVALID_Msk [5/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 864 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_NRZVALID_Msk [6/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 864 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_NRZVALID_Msk [7/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 864 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_NRZVALID_Msk [8/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 864 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_NRZVALID_Msk [9/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1097 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_NRZVALID_Msk [10/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1102 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_NRZVALID_Msk [11/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1102 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_NRZVALID_Msk [12/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1102 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_NRZVALID_Msk [13/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1112 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_NRZVALID_Msk [14/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1120 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_NRZVALID_Msk [15/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1120 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_NRZVALID_Msk [16/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1120 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_NRZVALID_Msk [17/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1170 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_NRZVALID_Msk [18/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1185 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_NRZVALID_Msk [19/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1185 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_NRZVALID_Msk [20/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1185 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_NRZVALID_Msk [21/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1185 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_NRZVALID_Msk [22/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1185 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_NRZVALID_Msk [23/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1359 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_NRZVALID_Msk [24/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1390 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_NRZVALID_Msk [25/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1390 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_NRZVALID_Msk [26/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1390 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_NRZVALID_Msk [27/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1390 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_NRZVALID_Msk [28/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1393 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_NRZVALID_Msk [29/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1393 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ TPI_DEVID_NRZVALID_Msk [30/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1431 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_NRZVALID_Msk [31/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1431 of file core_cm35p.h.

◆ TPI_DEVID_NRZVALID_Msk [32/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1454 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_NRZVALID_Msk [33/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1454 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_NRZVALID_Msk [34/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1454 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_NRZVALID_Msk [35/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1506 of file core_armv81mml.h.

◆ TPI_DEVID_NRZVALID_Msk [36/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1526 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_NRZVALID_Msk [37/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1526 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_NRZVALID_Msk [38/38]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1526 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_NRZVALID_Pos [1/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 791 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_NRZVALID_Pos [2/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 791 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_NRZVALID_Pos [3/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 791 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_NRZVALID_Pos [4/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 791 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_NRZVALID_Pos [5/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 863 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_NRZVALID_Pos [6/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 863 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_NRZVALID_Pos [7/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 863 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_NRZVALID_Pos [8/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 863 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_NRZVALID_Pos [9/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1096 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_NRZVALID_Pos [10/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1101 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_NRZVALID_Pos [11/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1101 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_NRZVALID_Pos [12/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1101 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_NRZVALID_Pos [13/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1111 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_NRZVALID_Pos [14/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1119 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_NRZVALID_Pos [15/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1119 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_NRZVALID_Pos [16/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1119 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_NRZVALID_Pos [17/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1169 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_NRZVALID_Pos [18/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1184 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_NRZVALID_Pos [19/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1184 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_NRZVALID_Pos [20/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1184 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_NRZVALID_Pos [21/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1184 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_NRZVALID_Pos [22/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1184 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_NRZVALID_Pos [23/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1358 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_NRZVALID_Pos [24/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1389 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_NRZVALID_Pos [25/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1389 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_NRZVALID_Pos [26/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1389 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_NRZVALID_Pos [27/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1389 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_NRZVALID_Pos [28/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1392 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_NRZVALID_Pos [29/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1392 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ TPI_DEVID_NRZVALID_Pos [30/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1430 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_NRZVALID_Pos [31/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1430 of file core_cm35p.h.

◆ TPI_DEVID_NRZVALID_Pos [32/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1453 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_NRZVALID_Pos [33/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1453 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_NRZVALID_Pos [34/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1453 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_NRZVALID_Pos [35/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1505 of file core_armv81mml.h.

◆ TPI_DEVID_NRZVALID_Pos [36/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1525 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_NRZVALID_Pos [37/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1525 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_NRZVALID_Pos [38/38]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1525 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_PTINVALID_Msk [1/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 798 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_PTINVALID_Msk [2/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 798 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_PTINVALID_Msk [3/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 798 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_PTINVALID_Msk [4/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 798 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_PTINVALID_Msk [5/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 870 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_PTINVALID_Msk [6/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 870 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_PTINVALID_Msk [7/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 870 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_PTINVALID_Msk [8/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 870 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_PTINVALID_Msk [9/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1103 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_PTINVALID_Msk [10/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1108 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_PTINVALID_Msk [11/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1108 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_PTINVALID_Msk [12/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1108 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_PTINVALID_Msk [13/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1118 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_PTINVALID_Msk [14/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1126 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_PTINVALID_Msk [15/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1126 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_PTINVALID_Msk [16/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1126 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_PTINVALID_Msk [17/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1176 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_PTINVALID_Msk [18/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1191 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_PTINVALID_Msk [19/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1191 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_PTINVALID_Msk [20/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1191 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_PTINVALID_Msk [21/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1191 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_PTINVALID_Msk [22/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1191 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_PTINVALID_Msk [23/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1365 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_PTINVALID_Msk [24/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1396 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_PTINVALID_Msk [25/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1396 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_PTINVALID_Msk [26/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1396 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_PTINVALID_Msk [27/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1396 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_PTINVALID_Msk [28/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1399 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_PTINVALID_Msk [29/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1399 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ TPI_DEVID_PTINVALID_Msk [30/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1437 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_PTINVALID_Msk [31/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1437 of file core_cm35p.h.

◆ TPI_DEVID_PTINVALID_Msk [32/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1460 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_PTINVALID_Msk [33/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1460 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_PTINVALID_Msk [34/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1460 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_PTINVALID_Msk [35/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1512 of file core_armv81mml.h.

◆ TPI_DEVID_PTINVALID_Msk [36/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1532 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_PTINVALID_Msk [37/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1532 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_PTINVALID_Msk [38/38]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1532 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_PTINVALID_Pos [1/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 797 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_PTINVALID_Pos [2/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 797 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_PTINVALID_Pos [3/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 797 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_PTINVALID_Pos [4/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 797 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVID_PTINVALID_Pos [5/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 869 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_PTINVALID_Pos [6/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 869 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_PTINVALID_Pos [7/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 869 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_PTINVALID_Pos [8/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 869 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVID_PTINVALID_Pos [9/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1102 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_PTINVALID_Pos [10/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1107 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_PTINVALID_Pos [11/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1107 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_PTINVALID_Pos [12/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1107 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVID_PTINVALID_Pos [13/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1117 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_PTINVALID_Pos [14/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1125 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_PTINVALID_Pos [15/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1125 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_PTINVALID_Pos [16/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1125 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVID_PTINVALID_Pos [17/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1175 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_PTINVALID_Pos [18/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1190 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_PTINVALID_Pos [19/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1190 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_PTINVALID_Pos [20/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1190 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_PTINVALID_Pos [21/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1190 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_PTINVALID_Pos [22/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1190 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVID_PTINVALID_Pos [23/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1364 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_PTINVALID_Pos [24/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1395 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_PTINVALID_Pos [25/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1395 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_PTINVALID_Pos [26/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1395 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_PTINVALID_Pos [27/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1395 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_PTINVALID_Pos [28/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1398 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVID_PTINVALID_Pos [29/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1398 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ TPI_DEVID_PTINVALID_Pos [30/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1436 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_PTINVALID_Pos [31/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1436 of file core_cm35p.h.

◆ TPI_DEVID_PTINVALID_Pos [32/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1459 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_PTINVALID_Pos [33/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1459 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_PTINVALID_Pos [34/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1459 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVID_PTINVALID_Pos [35/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1511 of file core_armv81mml.h.

◆ TPI_DEVID_PTINVALID_Pos [36/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1531 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_PTINVALID_Pos [37/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1531 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVID_PTINVALID_Pos [38/38]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1531 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVTYPE_MajorType_Msk [1/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 808 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVTYPE_MajorType_Msk [2/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 808 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVTYPE_MajorType_Msk [3/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 808 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVTYPE_MajorType_Msk [4/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 808 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mbl.h.

◆ TPI_DEVTYPE_MajorType_Msk [5/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 883 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVTYPE_MajorType_Msk [6/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 883 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVTYPE_MajorType_Msk [7/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 883 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVTYPE_MajorType_Msk [8/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 883 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm23.h.

◆ TPI_DEVTYPE_MajorType_Msk [9/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1119 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVTYPE_MajorType_Msk [10/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1124 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVTYPE_MajorType_Msk [11/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1124 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVTYPE_MajorType_Msk [12/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1124 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_sc300.h.

◆ TPI_DEVTYPE_MajorType_Msk [13/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1134 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVTYPE_MajorType_Msk [14/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1142 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVTYPE_MajorType_Msk [15/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1142 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVTYPE_MajorType_Msk [16/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1142 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm3.h.

◆ TPI_DEVTYPE_MajorType_Msk [17/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1192 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVTYPE_MajorType_Msk [18/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1207 of file stm32f469/stm32f469i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVTYPE_MajorType_Msk [19/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1207 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVTYPE_MajorType_Msk [20/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1207 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVTYPE_MajorType_Msk [21/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1207 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVTYPE_MajorType_Msk [22/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1207 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm4.h.

◆ TPI_DEVTYPE_MajorType_Msk [23/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1375 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVTYPE_MajorType_Msk [24/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1412 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVTYPE_MajorType_Msk [25/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1412 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVTYPE_MajorType_Msk [26/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1412 of file stm32h747/stm32h747i-disco/CM7/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVTYPE_MajorType_Msk [27/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1412 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVTYPE_MajorType_Msk [28/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1415 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm7.h.

◆ TPI_DEVTYPE_MajorType_Msk [29/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1415 of file imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h.

◆ TPI_DEVTYPE_MajorType_Msk [30/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1450 of file stm32h735/stm32h735g-dk/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVTYPE_MajorType_Msk [31/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1450 of file core_cm35p.h.

◆ TPI_DEVTYPE_MajorType_Msk [32/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1470 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVTYPE_MajorType_Msk [33/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1470 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVTYPE_MajorType_Msk [34/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1470 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_armv8mml.h.

◆ TPI_DEVTYPE_MajorType_Msk [35/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1525 of file core_armv81mml.h.

◆ TPI_DEVTYPE_MajorType_Msk [36/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1545 of file stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVTYPE_MajorType_Msk [37/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1545 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/core_cm33.h.

◆ TPI_DEVTYPE_MajorType_Msk [38/38]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1545 of file stm32f411/stm32f411e-disco/Drivers/CMSIS/Include/core_cm33.h.