Collaboration diagram for RCC_Exported_Constants:

Modules
	RCC_HSE_configuration

	RCC_LSE_Dual_Mode_Selection

	RCC_PLLSAIDivR_Factor

	RCC_PLL_Clock_Source

	RCC_System_Clock_Source

	RCC_AHB_Clock_Source

	RCC_APB1_APB2_Clock_Source

	RCC_Interrupt_Source

	RCC_LSE_Configuration

	RCC_RTC_Clock_Source

	RCC_TIM_PRescaler_Selection

	RCC_AHB1_Peripherals

	RCC_AHB2_Peripherals

	RCC_AHB3_Peripherals

	RCC_APB1_Peripherals

	RCC_APB2_Peripherals

	RCC_MCO1_Clock_Source_Prescaler

	RCC_MCO2_Clock_Source_Prescaler

	RCC_Flag

	RCC_I2S_Clock_Source

	HSE_configuration

	PLL_entry_clock_source

	PLL_multiplication_factor

	PREDIV1_division_factor

	PREDIV1_clock_source

	System_clock_source

	AHB_clock_source

	APB1_APB2_clock_source

	RCC_Interrupt_source

	USB_Device_clock_source

	ADC_clock_source

	LSE_configuration

	RTC_clock_source

	AHB_peripheral

	APB2_peripheral

	APB1_peripheral

	Clock_source_to_output_on_MCO_pin

	RCC_PLL_Multiplication_Factor

	RCC_PREDIV1_division_factor

	RCC_APB1_APB2_clock_source

	RCC_ADC_clock_source

	RCC_TIM_clock_source

	RCC_HRTIM_clock_source

	RCC_I2C_clock_source

	RCC_USART_clock_source

	RCC_LSE_configuration

Functions
void	RCC_ADCCLKConfig (uint32_t RCC_PLLCLK)
	Configures the ADC clock (ADCCLK). More...

void	RCC_AdjustHSICalibrationValue (uint8_t HSICalibrationValue)
	Adjusts the Internal High Speed oscillator (HSI) calibration value. More...

void	RCC_AHBPeriphClockCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
	Enables or disables the AHB peripheral clock. More...

void	RCC_AHBPeriphResetCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
	Forces or releases AHB peripheral reset. More...

void	RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
	Enables or disables the Low Speed APB (APB1) peripheral clock. More...

void	RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
	Forces or releases Low Speed APB (APB1) peripheral reset. More...

void	RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
	Enables or disables the High Speed APB (APB2) peripheral clock. More...

void	RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
	Forces or releases High Speed APB (APB2) peripheral reset. More...

void	RCC_BackupResetCmd (FunctionalState NewState)
	Forces or releases the Backup domain reset. More...

void	RCC_ClearFlag (void)
	Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST. More...

void	RCC_ClearITPendingBit (uint8_t RCC_IT)
	Clears the RCC's interrupt pending bits. More...

void	RCC_ClockSecuritySystemCmd (FunctionalState NewState)
	Enables or disables the Clock Security System. More...

void	RCC_DeInit (void)
	Resets the RCC clock configuration to the default reset state. More...

void	RCC_GetClocksFreq (RCC_ClocksTypeDef *RCC_Clocks)
	Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2. More...

FlagStatus	RCC_GetFlagStatus (uint8_t RCC_FLAG)
	Checks whether the specified RCC flag is set or not. More...

ITStatus	RCC_GetITStatus (uint8_t RCC_IT)
	Checks whether the specified RCC interrupt has occurred or not. More...

uint8_t	RCC_GetSYSCLKSource (void)
	Returns the clock source used as system clock. More...

void	RCC_HCLKConfig (uint32_t RCC_SYSCLK)
	Configures the AHB clock (HCLK). More...

void	RCC_HRTIM1CLKConfig (uint32_t RCC_HRTIMCLK)
	Configures the HRTIM1 clock sources(HRTIM1CLK). More...

void	RCC_HSEConfig (uint8_t RCC_HSE)
	Configures the External High Speed oscillator (HSE). More...

void	RCC_HSICmd (FunctionalState NewState)
	Enables or disables the Internal High Speed oscillator (HSI). More...

void	RCC_I2CCLKConfig (uint32_t RCC_I2CCLK)
	Configures the I2C clock (I2CCLK). More...

void	RCC_I2SCLKConfig (uint32_t RCC_I2SCLKSource)
	Configures the I2S clock source (I2SCLK). More...

void	RCC_ITConfig (uint8_t RCC_IT, FunctionalState NewState)
	Enables or disables the specified RCC interrupts. More...

void	RCC_LSEConfig (uint32_t RCC_LSE)
	Configures the External Low Speed oscillator (LSE). More...

void	RCC_LSEDriveConfig (uint32_t RCC_LSEDrive)
	Configures the External Low Speed oscillator (LSE) drive capability. More...

void	RCC_LSICmd (FunctionalState NewState)
	Enables or disables the Internal Low Speed oscillator (LSI). More...

void	RCC_MCOConfig (uint8_t RCC_MCOSource, uint32_t RCC_MCOPrescaler)
	Selects the clock source to output on MCO pin (PA8) and the corresponding prescsaler. More...

void	RCC_PCLK1Config (uint32_t RCC_HCLK)
	Configures the Low Speed APB clock (PCLK1). More...

void	RCC_PCLK2Config (uint32_t RCC_HCLK)
	Configures the High Speed APB clock (PCLK2). More...

void	RCC_PLLCmd (FunctionalState NewState)
	Enables or disables the main PLL. More...

void	RCC_PLLConfig (uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
	Configures the PLL clock source and multiplication factor. More...

void	RCC_PREDIV1Config (uint32_t RCC_PREDIV1_Div)
	Configures the PREDIV1 division factor. More...

void	RCC_RTCCLKCmd (FunctionalState NewState)
	Enables or disables the RTC clock. More...

void	RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource)
	Configures the RTC clock (RTCCLK). More...

void	RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource)
	Configures the system clock (SYSCLK). More...

void	RCC_TIMCLKConfig (uint32_t RCC_TIMCLK)
	Configures the TIMx clock sources(TIMCLK). More...

void	RCC_USARTCLKConfig (uint32_t RCC_USARTCLK)
	Configures the USART clock (USARTCLK). More...

void	RCC_USBCLKConfig (uint32_t RCC_USBCLKSource)
	Configures the USB clock (USBCLK). More...

ErrorStatus	RCC_WaitForHSEStartUp (void)
	Waits for HSE start-up. More...

Detailed Description

Function Documentation

void RCC_ADCCLKConfig ( uint32_t RCC_PLLCLK )

Configures the ADC clock (ADCCLK).

Parameters

RCC_PCLK2

defines the ADC clock divider. This clock is derived from the APB2 clock (PCLK2). This parameter can be one of the following values:

RCC_PCLK2_Div2: ADC clock = PCLK2/2
RCC_PCLK2_Div4: ADC clock = PCLK2/4
RCC_PCLK2_Div6: ADC clock = PCLK2/6
RCC_PCLK2_Div8: ADC clock = PCLK2/8

Return values

None

Parameters

RCC_PLLCLK

defines the ADC clock divider. This clock is derived from the PLL Clock. This parameter can be one of the following values:

RCC_ADC12PLLCLK_OFF: ADC12 clock disabled
RCC_ADC12PLLCLK_Div1: ADC12 clock = PLLCLK/1
RCC_ADC12PLLCLK_Div2: ADC12 clock = PLLCLK/2
RCC_ADC12PLLCLK_Div4: ADC12 clock = PLLCLK/4
RCC_ADC12PLLCLK_Div6: ADC12 clock = PLLCLK/6
RCC_ADC12PLLCLK_Div8: ADC12 clock = PLLCLK/8
RCC_ADC12PLLCLK_Div10: ADC12 clock = PLLCLK/10
RCC_ADC12PLLCLK_Div12: ADC12 clock = PLLCLK/12
RCC_ADC12PLLCLK_Div16: ADC12 clock = PLLCLK/16
RCC_ADC12PLLCLK_Div32: ADC12 clock = PLLCLK/32
RCC_ADC12PLLCLK_Div64: ADC12 clock = PLLCLK/64
RCC_ADC12PLLCLK_Div128: ADC12 clock = PLLCLK/128
RCC_ADC12PLLCLK_Div256: ADC12 clock = PLLCLK/256
RCC_ADC34PLLCLK_OFF: ADC34 clock disabled
RCC_ADC34PLLCLK_Div1: ADC34 clock = PLLCLK/1
RCC_ADC34PLLCLK_Div2: ADC34 clock = PLLCLK/2
RCC_ADC34PLLCLK_Div4: ADC34 clock = PLLCLK/4
RCC_ADC34PLLCLK_Div6: ADC34 clock = PLLCLK/6
RCC_ADC34PLLCLK_Div8: ADC34 clock = PLLCLK/8
RCC_ADC34PLLCLK_Div10: ADC34 clock = PLLCLK/10
RCC_ADC34PLLCLK_Div12: ADC34 clock = PLLCLK/12
RCC_ADC34PLLCLK_Div16: ADC34 clock = PLLCLK/16
RCC_ADC34PLLCLK_Div32: ADC34 clock = PLLCLK/32
RCC_ADC34PLLCLK_Div64: ADC34 clock = PLLCLK/64
RCC_ADC34PLLCLK_Div128: ADC34 clock = PLLCLK/128
RCC_ADC34PLLCLK_Div256: ADC34 clock = PLLCLK/256

Return values

None

Definition at line 767 of file stm32f10x_rcc.c.

void RCC_AdjustHSICalibrationValue ( uint8_t HSICalibrationValue )

Adjusts the Internal High Speed oscillator (HSI) calibration value.

Note: The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC.

Parameters

HSICalibrationValue specifies the calibration trimming value. This parameter must be a number between 0 and 0x1F.

Return values

None

Note: The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC. Refer to the Application Note AN3300 for more details on how to calibrate the HSI.

Parameters

HSICalibrationValue specifies the HSI calibration trimming value. This parameter must be a number between 0 and 0x1F.

Return values

None

Parameters

HSICalibrationValue specifies the calibration trimming value. This parameter must be a number between 0 and 0x1F.

Return values

None

Definition at line 339 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_AHBPeriphClockCmd	(	uint32_t	RCC_AHBPeriph,
		FunctionalState	NewState
	)

Enables or disables the AHB peripheral clock.

Parameters

RCC_AHBPeriph specifies the AHB peripheral to gates its clock.

For STM32_Connectivity_line_devices, this parameter can be any combination of the following values:

RCC_AHBPeriph_DMA1
RCC_AHBPeriph_DMA2
RCC_AHBPeriph_SRAM
RCC_AHBPeriph_FLITF
RCC_AHBPeriph_CRC
RCC_AHBPeriph_OTG_FS
RCC_AHBPeriph_ETH_MAC
RCC_AHBPeriph_ETH_MAC_Tx
RCC_AHBPeriph_ETH_MAC_Rx

For other_STM32_devices, this parameter can be any combination of the following values:

RCC_AHBPeriph_DMA1
RCC_AHBPeriph_DMA2
RCC_AHBPeriph_SRAM
RCC_AHBPeriph_FLITF
RCC_AHBPeriph_CRC
RCC_AHBPeriph_FSMC
RCC_AHBPeriph_SDIO

Note: SRAM and FLITF clock can be disabled only during sleep mode.

Parameters

NewState new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values

None

Note: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Parameters

RCC_AHBPeriph

specifies the AHB peripheral to gates its clock. This parameter can be any combination of the following values:

RCC_AHBPeriph_GPIOA
RCC_AHBPeriph_GPIOB
RCC_AHBPeriph_GPIOC
RCC_AHBPeriph_GPIOD
RCC_AHBPeriph_GPIOE
RCC_AHBPeriph_GPIOF
RCC_AHBPeriph_TS
RCC_AHBPeriph_CRC
RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)
RCC_AHBPeriph_SRAM
RCC_AHBPeriph_DMA2
RCC_AHBPeriph_DMA1
RCC_AHBPeriph_ADC34
RCC_AHBPeriph_ADC12

NewState new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values

None

Definition at line 1065 of file stm32f10x_rcc.c.

void RCC_AHBPeriphResetCmd	(	uint32_t	RCC_AHBPeriph,
		FunctionalState	NewState
	)

Forces or releases AHB peripheral reset.

Parameters

RCC_AHBPeriph	specifies the AHB peripheral to reset. This parameter can be any combination of the following values: RCC_AHBPeriph_GPIOA RCC_AHBPeriph_GPIOB RCC_AHBPeriph_GPIOC RCC_AHBPeriph_GPIOD RCC_AHBPeriph_GPIOE RCC_AHBPeriph_GPIOF RCC_AHBPeriph_TS RCC_AHBPeriph_ADC34 RCC_AHBPeriph_ADC12
NewState	new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.

Return values

None

Definition at line 1660 of file stm32f30x_rcc.c.

void RCC_APB1PeriphClockCmd	(	uint32_t	RCC_APB1Periph,
		FunctionalState	NewState
	)

Enables or disables the Low Speed APB (APB1) peripheral clock.

Note: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Parameters

RCC_APB1Periph

specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:

RCC_APB1Periph_TIM2: TIM2 clock
RCC_APB1Periph_TIM3: TIM3 clock
RCC_APB1Periph_TIM4: TIM4 clock
RCC_APB1Periph_TIM5: TIM5 clock
RCC_APB1Periph_TIM6: TIM6 clock
RCC_APB1Periph_TIM7: TIM7 clock
RCC_APB1Periph_TIM12: TIM12 clock
RCC_APB1Periph_TIM13: TIM13 clock
RCC_APB1Periph_TIM14: TIM14 clock
RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx devices)
RCC_APB1Periph_WWDG: WWDG clock
RCC_APB1Periph_SPI2: SPI2 clock
RCC_APB1Periph_SPI3: SPI3 clock
RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices)
RCC_APB1Periph_USART2: USART2 clock
RCC_APB1Periph_USART3: USART3 clock
RCC_APB1Periph_UART4: UART4 clock
RCC_APB1Periph_UART5: UART5 clock
RCC_APB1Periph_I2C1: I2C1 clock
RCC_APB1Periph_I2C2: I2C2 clock
RCC_APB1Periph_I2C3: I2C3 clock
RCC_APB1Periph_FMPI2C1: FMPI2C1 clock
RCC_APB1Periph_CAN1: CAN1 clock
RCC_APB1Periph_CAN2: CAN2 clock
RCC_APB1Periph_CEC: CEC clock (STM32F446xx devices)
RCC_APB1Periph_PWR: PWR clock
RCC_APB1Periph_DAC: DAC clock
RCC_APB1Periph_UART7: UART7 clock
RCC_APB1Periph_UART8: UART8 clock

NewState new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values

None

Note: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Parameters

RCC_APB1Periph

specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:

RCC_APB1Periph_TIM2: TIM2 clock
RCC_APB1Periph_TIM3: TIM3 clock
RCC_APB1Periph_TIM4: TIM4 clock
RCC_APB1Periph_TIM5: TIM5 clock
RCC_APB1Periph_TIM6: TIM6 clock
RCC_APB1Periph_TIM7: TIM7 clock
RCC_APB1Periph_TIM12: TIM12 clock
RCC_APB1Periph_TIM13: TIM13 clock
RCC_APB1Periph_TIM14: TIM14 clock
RCC_APB1Periph_WWDG: WWDG clock
RCC_APB1Periph_SPI2: SPI2 clock
RCC_APB1Periph_SPI3: SPI3 clock
RCC_APB1Periph_USART2: USART2 clock
RCC_APB1Periph_USART3: USART3 clock
RCC_APB1Periph_UART4: UART4 clock
RCC_APB1Periph_UART5: UART5 clock
RCC_APB1Periph_I2C1: I2C1 clock
RCC_APB1Periph_I2C2: I2C2 clock
RCC_APB1Periph_I2C3: I2C3 clock
RCC_APB1Periph_CAN1: CAN1 clock
RCC_APB1Periph_CAN2: CAN2 clock
RCC_APB1Periph_PWR: PWR clock
RCC_APB1Periph_DAC: DAC clock
RCC_APB1Periph_UART7: UART7 clock
RCC_APB1Periph_UART8: UART8 clock

NewState new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values

None

Note: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Parameters

RCC_APB1Periph

specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:

RCC_APB1Periph_TIM2
RCC_APB1Periph_TIM3
RCC_APB1Periph_TIM4
RCC_APB1Periph_TIM6
RCC_APB1Periph_TIM7
RCC_APB1Periph_WWDG
RCC_APB1Periph_SPI2
RCC_APB1Periph_SPI3
RCC_APB1Periph_USART2
RCC_APB1Periph_USART3
RCC_APB1Periph_UART4
RCC_APB1Periph_UART5
RCC_APB1Periph_I2C1
RCC_APB1Periph_I2C2
RCC_APB1Periph_USB
RCC_APB1Periph_CAN1
RCC_APB1Periph_PWR
RCC_APB1Periph_DAC1
RCC_APB1Periph_DAC2

NewState new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values

None

Parameters

RCC_APB1Periph

specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:

RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14

NewState new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values

None

Definition at line 2004 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_APB1PeriphResetCmd	(	uint32_t	RCC_APB1Periph,
		FunctionalState	NewState
	)

Forces or releases Low Speed APB (APB1) peripheral reset.

Parameters

RCC_APB1Periph

specifies the APB1 peripheral to reset. This parameter can be any combination of the following values:

RCC_APB1Periph_TIM2: TIM2 clock
RCC_APB1Periph_TIM3: TIM3 clock
RCC_APB1Periph_TIM4: TIM4 clock
RCC_APB1Periph_TIM5: TIM5 clock
RCC_APB1Periph_TIM6: TIM6 clock
RCC_APB1Periph_TIM7: TIM7 clock
RCC_APB1Periph_TIM12: TIM12 clock
RCC_APB1Periph_TIM13: TIM13 clock
RCC_APB1Periph_TIM14: TIM14 clock
RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx devices)
RCC_APB1Periph_WWDG: WWDG clock
RCC_APB1Periph_SPI2: SPI2 clock
RCC_APB1Periph_SPI3: SPI3 clock
RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices)
RCC_APB1Periph_USART2: USART2 clock
RCC_APB1Periph_USART3: USART3 clock
RCC_APB1Periph_UART4: UART4 clock
RCC_APB1Periph_UART5: UART5 clock
RCC_APB1Periph_I2C1: I2C1 clock
RCC_APB1Periph_I2C2: I2C2 clock
RCC_APB1Periph_I2C3: I2C3 clock
RCC_APB1Periph_FMPI2C1: FMPI2C1 clock
RCC_APB1Periph_CAN1: CAN1 clock
RCC_APB1Periph_CAN2: CAN2 clock
RCC_APB1Periph_CEC: CEC clock(STM32F446xx devices)
RCC_APB1Periph_PWR: PWR clock
RCC_APB1Periph_DAC: DAC clock
RCC_APB1Periph_UART7: UART7 clock
RCC_APB1Periph_UART8: UART8 clock

NewState new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.

Return values

None

Parameters

RCC_APB1Periph

specifies the APB1 peripheral to reset. This parameter can be any combination of the following values:

RCC_APB1Periph_TIM2: TIM2 clock
RCC_APB1Periph_TIM3: TIM3 clock
RCC_APB1Periph_TIM4: TIM4 clock
RCC_APB1Periph_TIM5: TIM5 clock
RCC_APB1Periph_TIM6: TIM6 clock
RCC_APB1Periph_TIM7: TIM7 clock
RCC_APB1Periph_TIM12: TIM12 clock
RCC_APB1Periph_TIM13: TIM13 clock
RCC_APB1Periph_TIM14: TIM14 clock
RCC_APB1Periph_WWDG: WWDG clock
RCC_APB1Periph_SPI2: SPI2 clock
RCC_APB1Periph_SPI3: SPI3 clock
RCC_APB1Periph_USART2: USART2 clock
RCC_APB1Periph_USART3: USART3 clock
RCC_APB1Periph_UART4: UART4 clock
RCC_APB1Periph_UART5: UART5 clock
RCC_APB1Periph_I2C1: I2C1 clock
RCC_APB1Periph_I2C2: I2C2 clock
RCC_APB1Periph_I2C3: I2C3 clock
RCC_APB1Periph_CAN1: CAN1 clock
RCC_APB1Periph_CAN2: CAN2 clock
RCC_APB1Periph_PWR: PWR clock
RCC_APB1Periph_DAC: DAC clock
RCC_APB1Periph_UART7: UART7 clock
RCC_APB1Periph_UART8: UART8 clock

NewState new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.

Return values

None

Parameters

RCC_APB1Periph

specifies the APB1 peripheral to reset. This parameter can be any combination of the following values:

RCC_APB1Periph_TIM2
RCC_APB1Periph_TIM3
RCC_APB1Periph_TIM4
RCC_APB1Periph_TIM6
RCC_APB1Periph_TIM7
RCC_APB1Periph_WWDG
RCC_APB1Periph_SPI2
RCC_APB1Periph_SPI3
RCC_APB1Periph_USART2
RCC_APB1Periph_USART3
RCC_APB1Periph_UART4
RCC_APB1Periph_UART5
RCC_APB1Periph_I2C1
RCC_APB1Periph_I2C2
RCC_APB1Periph_I2C3
RCC_APB1Periph_USB
RCC_APB1Periph_CAN1
RCC_APB1Periph_PWR
RCC_APB1Periph_DAC

NewState new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values

None

Parameters

RCC_APB1Periph

specifies the APB1 peripheral to reset. This parameter can be any combination of the following values:

RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14

NewState new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values

None

Definition at line 2204 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_APB2PeriphClockCmd	(	uint32_t	RCC_APB2Periph,
		FunctionalState	NewState
	)

Enables or disables the High Speed APB (APB2) peripheral clock.

Note: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Parameters

RCC_APB2Periph

specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:

RCC_APB2Periph_TIM1: TIM1 clock
RCC_APB2Periph_TIM8: TIM8 clock
RCC_APB2Periph_USART1: USART1 clock
RCC_APB2Periph_USART6: USART6 clock
RCC_APB2Periph_ADC1: ADC1 clock
RCC_APB2Periph_ADC2: ADC2 clock
RCC_APB2Periph_ADC3: ADC3 clock
RCC_APB2Periph_SDIO: SDIO clock
RCC_APB2Periph_SPI1: SPI1 clock
RCC_APB2Periph_SPI4: SPI4 clock
RCC_APB2Periph_SYSCFG: SYSCFG clock
RCC_APB2Periph_TIM9: TIM9 clock
RCC_APB2Periph_TIM10: TIM10 clock
RCC_APB2Periph_TIM11: TIM11 clock
RCC_APB2Periph_SPI5: SPI5 clock
RCC_APB2Periph_SPI6: SPI6 clock
RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx devices)
RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices)
RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices)

NewState new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values

None

Note: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Parameters

RCC_APB2Periph

specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:

RCC_APB2Periph_TIM1: TIM1 clock
RCC_APB2Periph_TIM8: TIM8 clock
RCC_APB2Periph_USART1: USART1 clock
RCC_APB2Periph_USART6: USART6 clock
RCC_APB2Periph_ADC1: ADC1 clock
RCC_APB2Periph_ADC2: ADC2 clock
RCC_APB2Periph_ADC3: ADC3 clock
RCC_APB2Periph_SDIO: SDIO clock
RCC_APB2Periph_SPI1: SPI1 clock
RCC_APB2Periph_SPI4: SPI4 clock
RCC_APB2Periph_SYSCFG: SYSCFG clock
RCC_APB2Periph_TIM9: TIM9 clock
RCC_APB2Periph_TIM10: TIM10 clock
RCC_APB2Periph_TIM11: TIM11 clock
RCC_APB2Periph_SPI5: SPI5 clock
RCC_APB2Periph_SPI6: SPI6 clock

NewState new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values

None

Note: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Parameters

RCC_APB2Periph	specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values: RCC_APB2Periph_SYSCFG RCC_APB2Periph_SPI1 RCC_APB2Periph_USART1 RCC_APB2Periph_TIM15 RCC_APB2Periph_TIM16 RCC_APB2Periph_TIM17 RCC_APB2Periph_TIM1 RCC_APB2Periph_TIM8 RCC_APB2Periph_HRTIM1
NewState	new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values

None

Parameters

RCC_APB2Periph

specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:

RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11

NewState new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values

None

Definition at line 2051 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_APB2PeriphResetCmd	(	uint32_t	RCC_APB2Periph,
		FunctionalState	NewState
	)

Forces or releases High Speed APB (APB2) peripheral reset.

Parameters

RCC_APB2Periph

specifies the APB2 peripheral to reset. This parameter can be any combination of the following values:

RCC_APB2Periph_TIM1: TIM1 clock
RCC_APB2Periph_TIM8: TIM8 clock
RCC_APB2Periph_USART1: USART1 clock
RCC_APB2Periph_USART6: USART6 clock
RCC_APB2Periph_ADC1: ADC1 clock
RCC_APB2Periph_ADC2: ADC2 clock
RCC_APB2Periph_ADC3: ADC3 clock
RCC_APB2Periph_SDIO: SDIO clock
RCC_APB2Periph_SPI1: SPI1 clock
RCC_APB2Periph_SPI4: SPI4 clock
RCC_APB2Periph_SYSCFG: SYSCFG clock
RCC_APB2Periph_TIM9: TIM9 clock
RCC_APB2Periph_TIM10: TIM10 clock
RCC_APB2Periph_TIM11: TIM11 clock
RCC_APB2Periph_SPI5: SPI5 clock
RCC_APB2Periph_SPI6: SPI6 clock
RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx devices)
RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices)
RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices)

NewState new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.

Return values

None

Parameters

RCC_APB2Periph

specifies the APB2 peripheral to reset. This parameter can be any combination of the following values:

RCC_APB2Periph_TIM1: TIM1 clock
RCC_APB2Periph_TIM8: TIM8 clock
RCC_APB2Periph_USART1: USART1 clock
RCC_APB2Periph_USART6: USART6 clock
RCC_APB2Periph_ADC1: ADC1 clock
RCC_APB2Periph_ADC2: ADC2 clock
RCC_APB2Periph_ADC3: ADC3 clock
RCC_APB2Periph_SDIO: SDIO clock
RCC_APB2Periph_SPI1: SPI1 clock
RCC_APB2Periph_SPI4: SPI4 clock
RCC_APB2Periph_SYSCFG: SYSCFG clock
RCC_APB2Periph_TIM9: TIM9 clock
RCC_APB2Periph_TIM10: TIM10 clock
RCC_APB2Periph_TIM11: TIM11 clock
RCC_APB2Periph_SPI5: SPI5 clock
RCC_APB2Periph_SPI6: SPI6 clock

NewState new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.

Return values

None

Parameters

RCC_APB2Periph	specifies the APB2 peripheral to reset. This parameter can be any combination of the following values: RCC_APB2Periph_SYSCFG RCC_APB2Periph_SPI1 RCC_APB2Periph_USART1 RCC_APB2Periph_TIM15 RCC_APB2Periph_TIM16 RCC_APB2Periph_TIM17 RCC_APB2Periph_TIM1 RCC_APB2Periph_TIM8 RCC_APB2Periph_HRTIM1
NewState	new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.

Return values

None

Parameters

RCC_APB2Periph

specifies the APB2 peripheral to reset. This parameter can be any combination of the following values:

RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11

NewState new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.

Return values

None

Definition at line 2247 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_BackupResetCmd ( FunctionalState NewState )

Forces or releases the Backup domain reset.

Note: This function resets the RTC peripheral (including the backup registers) and the RTC clock source selection in RCC_CSR register.; The BKPSRAM is not affected by this reset.

Parameters

NewState new state of the Backup domain reset. This parameter can be: ENABLE or DISABLE.

Return values

None

Note: This function resets the RTC peripheral (including the backup registers) and the RTC clock source selection in RCC_BDCR register.

Parameters

NewState new state of the Backup domain reset. This parameter can be: ENABLE or DISABLE.

Return values

None

Parameters

NewState new state of the Backup domain reset. This parameter can be: ENABLE or DISABLE.

Return values

None

Definition at line 1519 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_ClearFlag ( void )

Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.

Clears the RCC reset flags. The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.

Parameters

None

Return values

None	Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.

Note: The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST

Parameters

None

Return values

None

Definition at line 2870 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_ClearITPendingBit ( uint8_t RCC_IT )

Clears the RCC's interrupt pending bits.

Parameters

RCC_IT

specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:

RCC_IT_LSIRDY: LSI ready interrupt
RCC_IT_LSERDY: LSE ready interrupt
RCC_IT_HSIRDY: HSI ready interrupt
RCC_IT_HSERDY: HSE ready interrupt
RCC_IT_PLLRDY: main PLL ready interrupt
RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices)
RCC_IT_CSS: Clock Security System interrupt

Return values

None

Parameters

RCC_IT

specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:

RCC_IT_LSIRDY: LSI ready interrupt
RCC_IT_LSERDY: LSE ready interrupt
RCC_IT_HSIRDY: HSI ready interrupt
RCC_IT_HSERDY: HSE ready interrupt
RCC_IT_PLLRDY: main PLL ready interrupt
RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
RCC_IT_CSS: Clock Security System interrupt

Return values

None

Parameters

RCC_IT

specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:

RCC_IT_LSIRDY: LSI ready interrupt
RCC_IT_LSERDY: LSE ready interrupt
RCC_IT_HSIRDY: HSI ready interrupt
RCC_IT_HSERDY: HSE ready interrupt
RCC_IT_PLLRDY: PLL ready interrupt
RCC_IT_CSS: Clock Security System interrupt

Return values

None

Parameters

RCC_IT specifies the interrupt pending bit to clear.

For STM32_Connectivity_line_devices, this parameter can be any combination of the following values:

RCC_IT_LSIRDY: LSI ready interrupt
RCC_IT_LSERDY: LSE ready interrupt
RCC_IT_HSIRDY: HSI ready interrupt
RCC_IT_HSERDY: HSE ready interrupt
RCC_IT_PLLRDY: PLL ready interrupt
RCC_IT_PLL2RDY: PLL2 ready interrupt
RCC_IT_PLL3RDY: PLL3 ready interrupt
RCC_IT_CSS: Clock Security System interrupt

For other_STM32_devices, this parameter can be any combination of the following values:

RCC_IT_LSIRDY: LSI ready interrupt
RCC_IT_LSERDY: LSE ready interrupt
RCC_IT_HSIRDY: HSI ready interrupt
RCC_IT_HSERDY: HSE ready interrupt
RCC_IT_PLLRDY: PLL ready interrupt

RCC_IT_CSS: Clock Security System interrupt
Return values

None

Definition at line 2924 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_ClockSecuritySystemCmd ( FunctionalState NewState )

Enables or disables the Clock Security System.

Note: If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt, CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.

Parameters

NewState new state of the Clock Security System. This parameter can be: ENABLE or DISABLE.

Return values

None

Parameters

NewState new state of the Clock Security System.. This parameter can be: ENABLE or DISABLE.

Return values

None

Definition at line 879 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_DeInit ( void )

Resets the RCC clock configuration to the default reset state.

Note

The default reset state of the clock configuration is given below:

HSI ON and used as system clock source
HSE, PLL and PLLI2S OFF
AHB, APB1 and APB2 prescaler set to 1.
CSS, MCO1 and MCO2 OFF
All interrupts disabled

This function doesn't modify the configuration of the

Peripheral clocks
LSI, LSE and RTC clocks

Parameters

None

Return values

None

Note: The default reset state of the clock configuration is given below:; HSI ON and used as system clock source; HSE and PLL OFF; AHB, APB1 and APB2 prescalers set to 1.; CSS and MCO OFF; All interrupts disabled; However, this function doesn't modify the configuration of the; Peripheral clocks; LSI, LSE and RTC clocks

Parameters

None

Return values

None

Parameters

None

Return values

None

Definition at line 225 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_GetClocksFreq ( RCC_ClocksTypeDef * RCC_Clocks )

Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2.

Returns the frequencies of the System, AHB, APB2 and APB1 busses clocks.

Note: The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:; If SYSCLK source is HSI, function returns values based on HSI_VALUE(*); If SYSCLK source is HSE, function returns values based on HSE_VALUE(**); If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) or HSI_VALUE(*) multiplied/divided by the PLL factors.; (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature.; (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value 25 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.; The result of this function could be not correct when using fractional value for HSE crystal.

Parameters

RCC_Clocks pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies.

Note: This function can be used by the user application to compute the baudrate for the communication peripherals or configure other parameters.; Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function must be called to update the structure's field. Otherwise, any configuration based on this function will be incorrect.

Return values

None

Note: This function returns the frequencies of : System, AHB, APB2 and APB1 busses clocks, ADC1/2/3/4 clocks, USART1/2/3/4/5 clocks, I2C1/2 clocks and TIM1/8 Clocks.; The frequency returned by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the source selected by RCC_SYSCLKConfig().; If SYSCLK source is HSI, function returns constant HSI_VALUE(*); If SYSCLK source is HSE, function returns constant HSE_VALUE(**); If SYSCLK source is PLL, function returns constant HSE_VALUE(**) or HSI_VALUE(*) multiplied by the PLL factors.; (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value 8 MHz) but the real value may vary depending on the variations in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().; (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value 8 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may return wrong result.; The result of this function could be not correct when using fractional value for HSE crystal.

Parameters

RCC_Clocks pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies.

Note: This function can be used by the user application to compute the baudrate for the communication peripherals or configure other parameters.; Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function must be called to update the structure's field. Otherwise, any configuration based on this function will be incorrect.

Return values

None	Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2.

Parameters

RCC_Clocks pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies.

Note: The result of this function could be not correct when using fractional value for HSE crystal.

Return values

None

Definition at line 1317 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

FlagStatus RCC_GetFlagStatus ( uint8_t RCC_FLAG )

Checks whether the specified RCC flag is set or not.

Parameters

RCC_FLAG

specifies the flag to check. This parameter can be one of the following values:

RCC_FLAG_HSIRDY: HSI oscillator clock ready
RCC_FLAG_HSERDY: HSE oscillator clock ready
RCC_FLAG_PLLRDY: main PLL clock ready
RCC_FLAG_PLLI2SRDY: PLLI2S clock ready
RCC_FLAG_PLLSAIRDY: PLLSAI clock ready (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices)
RCC_FLAG_LSERDY: LSE oscillator clock ready
RCC_FLAG_LSIRDY: LSI oscillator clock ready
RCC_FLAG_BORRST: POR/PDR or BOR reset
RCC_FLAG_PINRST: Pin reset
RCC_FLAG_PORRST: POR/PDR reset
RCC_FLAG_SFTRST: Software reset
RCC_FLAG_IWDGRST: Independent Watchdog reset
RCC_FLAG_WWDGRST: Window Watchdog reset
RCC_FLAG_LPWRRST: Low Power reset

Return values

The	new state of RCC_FLAG (SET or RESET).

Parameters

RCC_FLAG

specifies the flag to check. This parameter can be one of the following values:

RCC_FLAG_HSIRDY: HSI oscillator clock ready
RCC_FLAG_HSERDY: HSE oscillator clock ready
RCC_FLAG_PLLRDY: main PLL clock ready
RCC_FLAG_PLLI2SRDY: PLLI2S clock ready
RCC_FLAG_LSERDY: LSE oscillator clock ready
RCC_FLAG_LSIRDY: LSI oscillator clock ready
RCC_FLAG_BORRST: POR/PDR or BOR reset
RCC_FLAG_PINRST: Pin reset
RCC_FLAG_PORRST: POR/PDR reset
RCC_FLAG_SFTRST: Software reset
RCC_FLAG_IWDGRST: Independent Watchdog reset
RCC_FLAG_WWDGRST: Window Watchdog reset
RCC_FLAG_LPWRRST: Low Power reset

Return values

The	new state of RCC_FLAG (SET or RESET).

Parameters

RCC_FLAG

specifies the flag to check. This parameter can be one of the following values:

RCC_FLAG_HSIRDY: HSI oscillator clock ready
RCC_FLAG_HSERDY: HSE oscillator clock ready
RCC_FLAG_PLLRDY: PLL clock ready
RCC_FLAG_MCOF: MCO Flag
RCC_FLAG_LSERDY: LSE oscillator clock ready
RCC_FLAG_LSIRDY: LSI oscillator clock ready
RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
RCC_FLAG_PINRST: Pin reset
RCC_FLAG_PORRST: POR/PDR reset
RCC_FLAG_SFTRST: Software reset
RCC_FLAG_IWDGRST: Independent Watchdog reset
RCC_FLAG_WWDGRST: Window Watchdog reset
RCC_FLAG_LPWRRST: Low Power reset

Return values

The	new state of RCC_FLAG (SET or RESET).

Parameters

RCC_FLAG specifies the flag to check.

For STM32_Connectivity_line_devices, this parameter can be one of the following values:

RCC_FLAG_HSIRDY: HSI oscillator clock ready
RCC_FLAG_HSERDY: HSE oscillator clock ready
RCC_FLAG_PLLRDY: PLL clock ready
RCC_FLAG_PLL2RDY: PLL2 clock ready
RCC_FLAG_PLL3RDY: PLL3 clock ready
RCC_FLAG_LSERDY: LSE oscillator clock ready
RCC_FLAG_LSIRDY: LSI oscillator clock ready
RCC_FLAG_PINRST: Pin reset
RCC_FLAG_PORRST: POR/PDR reset
RCC_FLAG_SFTRST: Software reset
RCC_FLAG_IWDGRST: Independent Watchdog reset
RCC_FLAG_WWDGRST: Window Watchdog reset
RCC_FLAG_LPWRRST: Low Power reset

For other_STM32_devices, this parameter can be one of the following values:

RCC_FLAG_HSIRDY: HSI oscillator clock ready
RCC_FLAG_HSERDY: HSE oscillator clock ready
RCC_FLAG_PLLRDY: PLL clock ready
RCC_FLAG_LSERDY: LSE oscillator clock ready
RCC_FLAG_LSIRDY: LSI oscillator clock ready
RCC_FLAG_PINRST: Pin reset
RCC_FLAG_PORRST: POR/PDR reset
RCC_FLAG_SFTRST: Software reset
RCC_FLAG_IWDGRST: Independent Watchdog reset
RCC_FLAG_WWDGRST: Window Watchdog reset
RCC_FLAG_LPWRRST: Low Power reset

Return values

The	new state of RCC_FLAG (SET or RESET).

Definition at line 2825 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

ITStatus RCC_GetITStatus ( uint8_t RCC_IT )

Checks whether the specified RCC interrupt has occurred or not.

Parameters

RCC_IT

specifies the RCC interrupt source to check. This parameter can be one of the following values:

RCC_IT_LSIRDY: LSI ready interrupt
RCC_IT_LSERDY: LSE ready interrupt
RCC_IT_HSIRDY: HSI ready interrupt
RCC_IT_HSERDY: HSE ready interrupt
RCC_IT_PLLRDY: main PLL ready interrupt
RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
RCC_IT_PLLSAIRDY: PLLSAI clock ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices)
RCC_IT_CSS: Clock Security System interrupt

Return values

The	new state of RCC_IT (SET or RESET).

Parameters

RCC_IT

specifies the RCC interrupt source to check. This parameter can be one of the following values:

RCC_IT_LSIRDY: LSI ready interrupt
RCC_IT_LSERDY: LSE ready interrupt
RCC_IT_HSIRDY: HSI ready interrupt
RCC_IT_HSERDY: HSE ready interrupt
RCC_IT_PLLRDY: main PLL ready interrupt
RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
RCC_IT_CSS: Clock Security System interrupt

Return values

The	new state of RCC_IT (SET or RESET).

Parameters

RCC_IT

specifies the RCC interrupt source to check. This parameter can be one of the following values:

RCC_IT_LSIRDY: LSI ready interrupt
RCC_IT_LSERDY: LSE ready interrupt
RCC_IT_HSIRDY: HSI ready interrupt
RCC_IT_HSERDY: HSE ready interrupt
RCC_IT_PLLRDY: PLL ready interrupt
RCC_IT_CSS: Clock Security System interrupt

Return values

The	new state of RCC_IT (SET or RESET).

Parameters

RCC_IT specifies the RCC interrupt source to check.

For STM32_Connectivity_line_devices, this parameter can be one of the following values:

RCC_IT_LSIRDY: LSI ready interrupt
RCC_IT_LSERDY: LSE ready interrupt
RCC_IT_HSIRDY: HSI ready interrupt
RCC_IT_HSERDY: HSE ready interrupt
RCC_IT_PLLRDY: PLL ready interrupt
RCC_IT_PLL2RDY: PLL2 ready interrupt
RCC_IT_PLL3RDY: PLL3 ready interrupt
RCC_IT_CSS: Clock Security System interrupt

For other_STM32_devices, this parameter can be one of the following values:

RCC_IT_LSIRDY: LSI ready interrupt
RCC_IT_LSERDY: LSE ready interrupt
RCC_IT_HSIRDY: HSI ready interrupt
RCC_IT_HSERDY: HSE ready interrupt
RCC_IT_PLLRDY: PLL ready interrupt
RCC_IT_CSS: Clock Security System interrupt

Return values

The	new state of RCC_IT (SET or RESET).

Definition at line 2890 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

uint8_t RCC_GetSYSCLKSource ( void )

Returns the clock source used as system clock.

Parameters

None

Return values

The	clock source used as system clock. The returned value can be one of the following: 0x00: HSI used as system clock 0x04: HSE used as system clock 0x08: PLL used as system clock (PLL P for STM32F446xx devices) 0x0C: PLL R used as system clock (only for STM32F446xx devices)

Parameters

None

Return values

The	clock source used as system clock. The returned value can be one of the following: 0x00: HSI used as system clock 0x04: HSE used as system clock 0x08: PLL used as system clock

Parameters

None

Return values

The	clock source used as system clock. The returned value can be one of the following values: 0x00: HSI used as system clock 0x04: HSE used as system clock 0x08: PLL used as system clock

Parameters

None

Return values

The	clock source used as system clock. The returned value can be one of the following: 0x00: HSI used as system clock 0x04: HSE used as system clock 0x08: PLL used as system clock

Definition at line 1178 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_HCLKConfig ( uint32_t RCC_SYSCLK )

Configures the AHB clock (HCLK).

Note: Depending on the device voltage range, the software has to set correctly these bits to ensure that HCLK not exceed the maximum allowed frequency (for more details refer to section above "CPU, AHB and APB busses clocks configuration functions")

Parameters

RCC_SYSCLK

defines the AHB clock divider. This clock is derived from the system clock (SYSCLK). This parameter can be one of the following values:

RCC_SYSCLK_Div1: AHB clock = SYSCLK
RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
RCC_SYSCLK_Div512: AHB clock = SYSCLK/512

Return values

None

Note: Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details refer to section above "CPU, AHB and APB busses clocks configuration functions").

Parameters

RCC_SYSCLK

defines the AHB clock divider. This clock is derived from the system clock (SYSCLK). This parameter can be one of the following values:

RCC_SYSCLK_Div1: AHB clock = SYSCLK
RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
RCC_SYSCLK_Div512: AHB clock = SYSCLK/512

Return values

None

Parameters

RCC_SYSCLK

defines the AHB clock divider. This clock is derived from the system clock (SYSCLK). This parameter can be one of the following values:

RCC_SYSCLK_Div1: AHB clock = SYSCLK
RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
RCC_SYSCLK_Div512: AHB clock = SYSCLK/512

Return values

None

Definition at line 1203 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_HRTIM1CLKConfig ( uint32_t RCC_HRTIMCLK )

Configures the HRTIM1 clock sources(HRTIM1CLK).

Note: The configuration of the HRTIM1 clock source is only possible when the SYSCLK = PLL and HCLK and PCLK2 clocks are not divided in respect to SYSCLK; If one of the previous conditions is missed, the TIM clock source configuration is lost and calling again this function becomes mandatory.

Parameters

RCC_HRTIMCLK

defines the TIMx clock source. This parameter can be one of the following values:

RCC_HRTIM1CLK_HCLK: TIMx clock = APB high speed clock (doubled frequency when prescaled)
RCC_HRTIM1CLK_PLLCLK: TIMx clock = PLL output (running up to 144 MHz) (x can be 1 or 8).

Return values

None

Definition at line 1361 of file stm32f30x_rcc.c.

void RCC_HSEConfig ( uint8_t RCC_HSE )

Configures the External High Speed oscillator (HSE).

Note: After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application software should wait on HSERDY flag to be set indicating that HSE clock is stable and can be used to clock the PLL and/or system clock.; HSE state can not be changed if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then change the HSE state (ex. disable it).; The HSE is stopped by hardware when entering STOP and STANDBY modes.; This function reset the CSSON bit, so if the Clock security system(CSS) was previously enabled you have to enable it again after calling this function.

Parameters

RCC_HSE

specifies the new state of the HSE. This parameter can be one of the following values:

RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after 6 HSE oscillator clock cycles.
RCC_HSE_ON: turn ON the HSE oscillator
RCC_HSE_Bypass: HSE oscillator bypassed with external clock

Return values

None

Note: After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application software should wait on HSERDY flag to be set indicating that HSE clock is stable and can be used to clock the PLL and/or system clock.; HSE state can not be changed if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then change the HSE state (ex. disable it).; The HSE is stopped by hardware when entering STOP and STANDBY modes.; This function resets the CSSON bit, so if the Clock security system(CSS) was previously enabled you have to enable it again after calling this function.

Parameters

RCC_HSE

specifies the new state of the HSE. This parameter can be one of the following values:

RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after 6 HSE oscillator clock cycles.
RCC_HSE_ON: turn ON the HSE oscillator
RCC_HSE_Bypass: HSE oscillator bypassed with external clock

Return values

None

Definition at line 284 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_HSICmd ( FunctionalState NewState )

Enables or disables the Internal High Speed oscillator (HSI).

Note: The HSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after startup from Reset, wakeup from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).; HSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the HSI.; After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used as system clock source.

Parameters

NewState new state of the HSI. This parameter can be: ENABLE or DISABLE.

Note: When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.

Return values

None

Note: After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used to clock the PLL and/or system clock.; HSI can not be stopped if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then stop the HSI.; The HSI is stopped by hardware when entering STOP and STANDBY modes.; When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.

Parameters

NewState new state of the HSI. This parameter can be: ENABLE or DISABLE.

Return values

None

Note: HSI can not be stopped if it is used directly or through the PLL as system clock.

Parameters

NewState new state of the HSI. This parameter can be: ENABLE or DISABLE.

Return values

None

Definition at line 375 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_I2CCLKConfig ( uint32_t RCC_I2CCLK )

Configures the I2C clock (I2CCLK).

Parameters

RCC_I2CCLK

defines the I2C clock source. This clock is derived from the HSI or System clock. This parameter can be one of the following values:

RCC_I2CxCLK_HSI: I2Cx clock = HSI
RCC_I2CxCLK_SYSCLK: I2Cx clock = System Clock (x can be 1 or 2 or 3).

Return values

None

Definition at line 1268 of file stm32f30x_rcc.c.

void RCC_I2SCLKConfig ( uint32_t RCC_I2SCLKSource )

Configures the I2S clock source (I2SCLK).

Note: This function must be called before enabling the I2S APB clock.

Parameters

RCC_I2SCLKSource

specifies the I2S clock source. This parameter can be one of the following values:

RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source
RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin used as I2S clock source

Return values

None

Note: This function must be called before enabling the SPI2 and SPI3 clocks.

Parameters

RCC_I2SCLKSource

specifies the I2S clock source. This parameter can be one of the following values:

RCC_I2S2CLKSource_SYSCLK: SYSCLK clock used as I2S clock source
RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin used as I2S clock source

Return values

None

Definition at line 1065 of file STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c.

void RCC_ITConfig	(	uint8_t	RCC_IT,
		FunctionalState	NewState
	)

Enables or disables the specified RCC interrupts.

Parameters

RCC_IT

specifies the RCC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:

RCC_IT_LSIRDY: LSI ready interrupt
RCC_IT_LSERDY: LSE ready interrupt
RCC_IT_HSIRDY: HSI ready interrupt
RCC_IT_HSERDY: HSE ready interrupt
RCC_IT_PLLRDY: main PLL ready interrupt
RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices)

NewState new state of the specified RCC interrupts. This parameter can be: ENABLE or DISABLE.

Return values

None

Parameters

RCC_IT	specifies the RCC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values: RCC_IT_LSIRDY: LSI ready interrupt RCC_IT_LSERDY: LSE ready interrupt RCC_IT_HSIRDY: HSI ready interrupt RCC_IT_HSERDY: HSE ready interrupt RCC_IT_PLLRDY: main PLL ready interrupt RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
NewState	new state of the specified RCC interrupts. This parameter can be: ENABLE or DISABLE.

Return values

None

Note: The CSS interrupt doesn't have an enable bit; once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is automatically generated. The NMI will be executed indefinitely, and since NMI has higher priority than any other IRQ (and main program) the application will be stacked in the NMI ISR unless the CSS interrupt pending bit is cleared.

Parameters

RCC_IT	specifies the RCC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values: RCC_IT_LSIRDY: LSI ready interrupt RCC_IT_LSERDY: LSE ready interrupt RCC_IT_HSIRDY: HSI ready interrupt RCC_IT_HSERDY: HSE ready interrupt RCC_IT_PLLRDY: PLL ready interrupt
NewState	new state of the specified RCC interrupts. This parameter can be: ENABLE or DISABLE.

Return values

None

Parameters

RCC_IT specifies the RCC interrupt sources to be enabled or disabled.

For STM32_Connectivity_line_devices, this parameter can be any combination of the following values

RCC_IT_LSIRDY: LSI ready interrupt
RCC_IT_LSERDY: LSE ready interrupt
RCC_IT_HSIRDY: HSI ready interrupt
RCC_IT_HSERDY: HSE ready interrupt
RCC_IT_PLLRDY: PLL ready interrupt
RCC_IT_PLL2RDY: PLL2 ready interrupt
RCC_IT_PLL3RDY: PLL3 ready interrupt

For other_STM32_devices, this parameter can be any combination of the following values

RCC_IT_LSIRDY: LSI ready interrupt
RCC_IT_LSERDY: LSE ready interrupt
RCC_IT_HSIRDY: HSI ready interrupt
RCC_IT_HSERDY: HSE ready interrupt
RCC_IT_PLLRDY: PLL ready interrupt

Parameters

NewState new state of the specified RCC interrupts. This parameter can be: ENABLE or DISABLE.

Return values

None

Definition at line 2788 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_LSEConfig ( uint32_t RCC_LSE )

Configures the External Low Speed oscillator (LSE).

Note: As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using PWR_BackupAccessCmd(ENABLE) function before to configure the LSE (to be done once after reset).; After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.

Parameters

RCC_LSE

specifies the new state of the LSE. This parameter can be one of the following values:

RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles.
RCC_LSE_ON: turn ON the LSE oscillator
RCC_LSE_Bypass: LSE oscillator bypassed with external clock

Return values

None

Definition at line 354 of file stm32f30x_rcc.c.

void RCC_LSEDriveConfig ( uint32_t RCC_LSEDrive )

Configures the External Low Speed oscillator (LSE) drive capability.

Parameters

RCC_LSEDrive

specifies the new state of the LSE drive capability. This parameter can be one of the following values:

RCC_LSEDrive_Low: LSE oscillator low drive capability.
RCC_LSEDrive_MediumLow: LSE oscillator medium low drive capability.
RCC_LSEDrive_MediumHigh: LSE oscillator medium high drive capability.
RCC_LSEDrive_High: LSE oscillator high drive capability.

Return values

None

Definition at line 380 of file stm32f30x_rcc.c.

void RCC_LSICmd ( FunctionalState NewState )

Enables or disables the Internal Low Speed oscillator (LSI).

Note: After enabling the LSI, the application software should wait on LSIRDY flag to be set indicating that LSI clock is stable and can be used to clock the IWDG and/or the RTC.; LSI can not be disabled if the IWDG is running.

Parameters

NewState new state of the LSI. This parameter can be: ENABLE or DISABLE.

Note: When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator clock cycles.

Return values

None

Note: After enabling the LSI, the application software should wait on LSIRDY flag to be set indicating that LSI clock is stable and can be used to clock the IWDG and/or the RTC.; LSI can not be disabled if the IWDG is running.; When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator clock cycles.

Parameters

NewState new state of the LSI. This parameter can be: ENABLE or DISABLE.

Return values

None

Note: LSI can not be disabled if the IWDG is running.

Parameters

NewState new state of the LSI. This parameter can be: ENABLE or DISABLE.

Return values

None

Definition at line 440 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_MCOConfig	(	uint8_t	RCC_MCOSource,
		uint32_t	RCC_MCOPrescaler
	)

Selects the clock source to output on MCO pin (PA8) and the corresponding prescsaler.

Note: PA8 should be configured in alternate function mode.

Parameters

RCC_MCOSource

specifies the clock source to output. This parameter can be one of the following values:

RCC_MCOSource_NoClock: No clock selected.
RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
RCC_MCOSource_LSI: LSI oscillator clock selected.
RCC_MCOSource_LSE: LSE oscillator clock selected.
RCC_MCOSource_SYSCLK: System clock selected.
RCC_MCOSource_HSI: HSI oscillator clock selected.
RCC_MCOSource_HSE: HSE oscillator clock selected.
RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
RCC_MCOSource_PLLCLK: PLL clock selected.
RCC_MCOSource_HSI48: HSI48 clock selected.

RCC_MCOPrescaler

specifies the prescaler on MCO pin. This parameter can be one of the following values:

RCC_MCOPrescaler_1: MCO clock is divided by 1.
RCC_MCOPrescaler_2: MCO clock is divided by 2.
RCC_MCOPrescaler_4: MCO clock is divided by 4.
RCC_MCOPrescaler_8: MCO clock is divided by 8.
RCC_MCOPrescaler_16: MCO clock is divided by 16.
RCC_MCOPrescaler_32: MCO clock is divided by 32.
RCC_MCOPrescaler_64: MCO clock is divided by 64.
RCC_MCOPrescaler_128: MCO clock is divided by 128.

Return values

None

Definition at line 567 of file stm32f30x_rcc.c.

void RCC_PCLK1Config ( uint32_t RCC_HCLK )

Configures the Low Speed APB clock (PCLK1).

Parameters

RCC_HCLK

defines the APB1 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:

RCC_HCLK_Div1: APB1 clock = HCLK
RCC_HCLK_Div2: APB1 clock = HCLK/2
RCC_HCLK_Div4: APB1 clock = HCLK/4
RCC_HCLK_Div8: APB1 clock = HCLK/8
RCC_HCLK_Div16: APB1 clock = HCLK/16

Return values

None

Definition at line 1234 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_PCLK2Config ( uint32_t RCC_HCLK )

Configures the High Speed APB clock (PCLK2).

Parameters

RCC_HCLK

defines the APB2 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:

RCC_HCLK_Div1: APB2 clock = HCLK
RCC_HCLK_Div2: APB2 clock = HCLK/2
RCC_HCLK_Div4: APB2 clock = HCLK/4
RCC_HCLK_Div8: APB2 clock = HCLK/8
RCC_HCLK_Div16: APB2 clock = HCLK/16

Return values

None

Definition at line 1265 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_PLLCmd ( FunctionalState NewState )

Enables or disables the main PLL.

Enables or disables the PLL.

Note: After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.; The main PLL can not be disabled if it is used as system clock source; The main PLL is disabled by hardware when entering STOP and STANDBY modes.

Parameters

NewState new state of the main PLL. This parameter can be: ENABLE or DISABLE.

Return values

None

Note: After enabling the PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.; The PLL can not be disabled if it is used as system clock source; The PLL is disabled by hardware when entering STOP and STANDBY modes.

Parameters

NewState new state of the PLL. This parameter can be: ENABLE or DISABLE.

Return values

None	Enables or disables the main PLL.

Note: The PLL can not be disabled if it is used as system clock.

Parameters

NewState new state of the PLL. This parameter can be: ENABLE or DISABLE.

Return values

None

Definition at line 563 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_PLLConfig	(	uint32_t	RCC_PLLSource,
		uint32_t	RCC_PLLMul
	)

Configures the PLL clock source and multiplication factor.

Note: This function must be used only when the PLL is disabled.

Parameters

RCC_PLLSource

specifies the PLL entry clock source. For STM32_Connectivity_line_devices or STM32_Value_line_devices, this parameter can be one of the following values:

RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry For other_STM32_devices, this parameter can be one of the following values:
RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry
RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry

RCC_PLLMul specifies the PLL multiplication factor. For STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5} For other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16]

Return values

None

Note: This function must be used only when the PLL is disabled.; The minimum input clock frequency for PLL is 2 MHz (when using HSE as PLL source).

Parameters

RCC_PLLSource	specifies the PLL entry clock source. This parameter can be one of the following values: RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock source
RCC_PLLMul	specifies the PLL multiplication factor, which drive the PLLVCO clock This parameter can be RCC_PLLMul_x where x:[2,16]

Return values

None

Definition at line 379 of file stm32f10x_rcc.c.

void RCC_PREDIV1Config ( uint32_t RCC_PREDIV1_Div )

Configures the PREDIV1 division factor.

Note: This function must be used only when the PLL is disabled.

Parameters

RCC_PREDIV1_Div specifies the PREDIV1 clock division factor. This parameter can be RCC_PREDIV1_Divx where x:[1,16]

Return values

None

Definition at line 466 of file stm32f30x_rcc.c.

void RCC_RTCCLKCmd ( FunctionalState NewState )

Enables or disables the RTC clock.

Note: This function must be used only after the RTC clock source was selected using the RCC_RTCCLKConfig function.

Parameters

NewState new state of the RTC clock. This parameter can be: ENABLE or DISABLE.

Return values

None

Note: This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.

Parameters

NewState new state of the RTC clock. This parameter can be: ENABLE or DISABLE.

Return values

None

Definition at line 1502 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_RTCCLKConfig ( uint32_t RCC_RTCCLKSource )

Configures the RTC clock (RTCCLK).

Note: As the RTC clock configuration bits are in the Backup domain and write access is denied to this domain after reset, you have to enable write access using PWR_BackupAccessCmd(ENABLE) function before to configure the RTC clock source (to be done once after reset).; Once the RTC clock is configured it can't be changed unless the Backup domain is reset using RCC_BackupResetCmd() function, or by a Power On Reset (POR).

Parameters

RCC_RTCCLKSource

specifies the RTC clock source. This parameter can be one of the following values:

RCC_RTCCLKSource_LSE: LSE selected as RTC clock
RCC_RTCCLKSource_LSI: LSI selected as RTC clock
RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected as RTC clock, where x:[2,31]

Note: If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.; The maximum input clock frequency for RTC is 1MHz (when using HSE as RTC clock source).

Return values

None

Note: As the RTC clock configuration bits are in the Backup domain and write access is denied to this domain after reset, you have to enable write access using PWR_BackupAccessCmd(ENABLE) function before to configure the RTC clock source (to be done once after reset).; Once the RTC clock is configured it can't be changed unless the RTC is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR)

Parameters

RCC_RTCCLKSource

specifies the RTC clock source. This parameter can be one of the following values:

RCC_RTCCLKSource_LSE: LSE selected as RTC clock
RCC_RTCCLKSource_LSI: LSI selected as RTC clock
RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock

Note: If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.; The maximum input clock frequency for RTC is 2MHz (when using HSE as RTC clock source).

Return values

None

Note: Once the RTC clock is selected it can't be changed unless the Backup domain is reset.

Parameters

RCC_RTCCLKSource

specifies the RTC clock source. This parameter can be one of the following values:

RCC_RTCCLKSource_LSE: LSE selected as RTC clock
RCC_RTCCLKSource_LSI: LSI selected as RTC clock
RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock

Return values

None

Definition at line 1470 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_SYSCLKConfig ( uint32_t RCC_SYSCLKSource )

Configures the system clock (SYSCLK).

Note: The HSI is used (enabled by hardware) as system clock source after startup from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).; A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. You can use RCC_GetSYSCLKSource() function to know which clock is currently used as system clock source.

Parameters

RCC_SYSCLKSource

specifies the clock source used as system clock. This parameter can be one of the following values:

RCC_SYSCLKSource_HSI: HSI selected as system clock source
RCC_SYSCLKSource_HSE: HSE selected as system clock source
RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source (RCC_SYSCLKSource_PLLPCLK for STM32F446xx devices)
RCC_SYSCLKSource_PLLRCLK: PLL R selected as system clock source only for STM32F446xx devices

Return values

None

Note: The HSI is used (enabled by hardware) as system clock source after startup from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).; A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. You can use RCC_GetSYSCLKSource() function to know which clock is currently used as system clock source.

Parameters

RCC_SYSCLKSource

specifies the clock source used as system clock. This parameter can be one of the following values:

RCC_SYSCLKSource_HSI: HSI selected as system clock source
RCC_SYSCLKSource_HSE: HSE selected as system clock source
RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source

Return values

None

Note: The HSI is used (enabled by hardware) as system clock source after startup from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).; A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. You can use RCC_GetSYSCLKSource() function to know which clock is currently used as system clock source.

Parameters

RCC_SYSCLKSource

specifies the clock source used as system clock source This parameter can be one of the following values:

RCC_SYSCLKSource_HSI: HSI selected as system clock source
RCC_SYSCLKSource_HSE: HSE selected as system clock source
RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source

Return values

None

Parameters

RCC_SYSCLKSource

specifies the clock source used as system clock. This parameter can be one of the following values:

RCC_SYSCLKSource_HSI: HSI selected as system clock
RCC_SYSCLKSource_HSE: HSE selected as system clock
RCC_SYSCLKSource_PLLCLK: PLL selected as system clock

Return values

None

Definition at line 1149 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

void RCC_TIMCLKConfig ( uint32_t RCC_TIMCLK )

Configures the TIMx clock sources(TIMCLK).

Note: The configuration of the TIMx clock source is only possible when the SYSCLK = PLL and HCLK and PCLK2 clocks are not divided in respect to SYSCLK; If one of the previous conditions is missed, the TIM clock source configuration is lost and calling again this function becomes mandatory.

Parameters

RCC_TIMCLK

defines the TIMx clock source. This parameter can be one of the following values:

RCC_TIMxCLK_HCLK: TIMx clock = APB high speed clock (doubled frequency when prescaled)
RCC_TIMxCLK_PLLCLK: TIMx clock = PLL output (running up to 144 MHz) (x can be 1, 8, 15, 16, 17).

Return values

None

Definition at line 1311 of file stm32f30x_rcc.c.

void RCC_USARTCLKConfig ( uint32_t RCC_USARTCLK )

Configures the USART clock (USARTCLK).

Parameters

RCC_USARTCLK

defines the USART clock source. This clock is derived from the HSI or System clock. This parameter can be one of the following values:

RCC_USARTxCLK_PCLK: USART clock = APB Clock (PCLK)
RCC_USARTxCLK_SYSCLK: USART clock = System Clock
RCC_USARTxCLK_LSE: USART clock = LSE Clock
RCC_USARTxCLK_HSI: USART clock = HSI Clock (x can be 1, 2, 3, 4 or 5).

Return values

None

Definition at line 1385 of file stm32f30x_rcc.c.

void RCC_USBCLKConfig ( uint32_t RCC_USBCLKSource )

Configures the USB clock (USBCLK).

Parameters

RCC_USBCLKSource

specifies the USB clock source. This clock is derived from the PLL output. This parameter can be one of the following values:

RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB clock source
RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source

Return values

None

Definition at line 729 of file stm32f10x_rcc.c.

ErrorStatus RCC_WaitForHSEStartUp ( void )

Waits for HSE start-up.

Note: This functions waits on HSERDY flag to be set and return SUCCESS if this flag is set, otherwise returns ERROR if the timeout is reached and this flag is not set. The timeout value is defined by the constant HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending on the HSE crystal used in your application.

Parameters

None

Return values

An	ErrorStatus enumeration value: SUCCESS: HSE oscillator is stable and ready to use ERROR: HSE oscillator not yet ready

Note: This function waits on HSERDY flag to be set and return SUCCESS if this flag is set, otherwise returns ERROR if the timeout is reached and this flag is not set. The timeout value is defined by the constant HSE_STARTUP_TIMEOUT in stm32f30x.h file. You can tailor it depending on the HSE crystal used in your application.

Parameters

None

Return values

An	ErrorStatus enumeration value: SUCCESS: HSE oscillator is stable and ready to use ERROR: HSE oscillator not yet ready

Parameters

None

Return values

An	ErrorStatus enumuration value: SUCCESS: HSE oscillator is stable and ready to use ERROR: HSE oscillator not yet ready

Definition at line 308 of file CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c.

Modules

Functions

Detailed Description

Function Documentation