Go to the documentation of this file.
21 #ifndef STM32H7xx_HAL_TIM_EX_H
22 #define STM32H7xx_HAL_TIM_EX_H
53 uint32_t IC1Prescaler;
59 uint32_t Commutation_Delay;
62 #if defined(TIM_BREAK_INPUT_SUPPORT)
77 TIMEx_BreakInputConfigTypeDef;
93 #define TIM_TIM1_ETR_GPIO 0x00000000U
94 #define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0
95 #define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1
96 #define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
97 #define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_2)
98 #define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)
99 #define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)
100 #define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
101 #define TIM_TIM1_ETR_ADC3_AWD3 TIM1_AF1_ETRSEL_3
103 #define TIM_TIM8_ETR_GPIO 0x00000000U
104 #define TIM_TIM8_ETR_COMP1 TIM8_AF1_ETRSEL_0
105 #define TIM_TIM8_ETR_COMP2 TIM8_AF1_ETRSEL_1
106 #define TIM_TIM8_ETR_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)
107 #define TIM_TIM8_ETR_ADC2_AWD2 (TIM8_AF1_ETRSEL_2)
108 #define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)
109 #define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1)
110 #define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)
111 #define TIM_TIM8_ETR_ADC3_AWD3 TIM8_AF1_ETRSEL_3
113 #define TIM_TIM2_ETR_GPIO 0x00000000U
114 #define TIM_TIM2_ETR_COMP1 (TIM2_AF1_ETRSEL_0)
115 #define TIM_TIM2_ETR_COMP2 (TIM2_AF1_ETRSEL_1)
116 #define TIM_TIM2_ETR_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)
117 #define TIM_TIM2_ETR_SAI1_FSA TIM2_AF1_ETRSEL_2
118 #define TIM_TIM2_ETR_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)
120 #define TIM_TIM3_ETR_GPIO 0x00000000U
121 #define TIM_TIM3_ETR_COMP1 TIM3_AF1_ETRSEL_0
123 #define TIM_TIM5_ETR_GPIO 0x00000000U
124 #define TIM_TIM5_ETR_SAI2_FSA TIM5_AF1_ETRSEL_0
125 #define TIM_TIM5_ETR_SAI2_FSB TIM5_AF1_ETRSEL_1
126 #define TIM_TIM5_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0
127 #define TIM_TIM5_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1
129 #define TIM_TIM23_ETR_GPIO 0x00000000U
130 #define TIM_TIM23_ETR_COMP1 (TIM2_AF1_ETRSEL_0)
131 #define TIM_TIM23_ETR_COMP2 (TIM2_AF1_ETRSEL_1)
133 #define TIM_TIM24_ETR_GPIO 0x00000000U
134 #define TIM_TIM24_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0
135 #define TIM_TIM24_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1
136 #define TIM_TIM24_ETR_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)
137 #define TIM_TIM24_ETR_SAI1_FSB TIM2_AF1_ETRSEL_2
141 #if defined(TIM_BREAK_INPUT_SUPPORT)
146 #define TIM_BREAKINPUT_BRK 0x00000001U
147 #define TIM_BREAKINPUT_BRK2 0x00000002U
155 #define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U
156 #define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U
157 #define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U
158 #define TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U
166 #define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U
167 #define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U
175 #define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U
176 #define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U
185 #define TIM_TIM1_TI1_GPIO 0x00000000U
186 #define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0
188 #define TIM_TIM8_TI1_GPIO 0x00000000U
189 #define TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_0
191 #define TIM_TIM2_TI4_GPIO 0x00000000U
192 #define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0
193 #define TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1
194 #define TIM_TIM2_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1)
196 #define TIM_TIM3_TI1_GPIO 0x00000000U
197 #define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0
198 #define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1
199 #define TIM_TIM3_TI1_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1)
201 #define TIM_TIM5_TI1_GPIO 0x00000000U
202 #define TIM_TIM5_TI1_CAN_TMP TIM_TISEL_TI1SEL_0
203 #define TIM_TIM5_TI1_CAN_RTP TIM_TISEL_TI1SEL_1
205 #define TIM_TIM12_TI1_GPIO 0x00000000U
206 #define TIM_TIM12_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0
208 #define TIM_TIM15_TI1_GPIO 0x00000000U
209 #define TIM_TIM15_TI1_TIM2_CH1 TIM_TISEL_TI1SEL_0
210 #define TIM_TIM15_TI1_TIM3_CH1 TIM_TISEL_TI1SEL_1
211 #define TIM_TIM15_TI1_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1)
212 #define TIM_TIM15_TI1_RCC_LSE (TIM_TISEL_TI1SEL_2)
213 #define TIM_TIM15_TI1_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)
214 #define TIM_TIM15_TI1_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1)
216 #define TIM_TIM15_TI2_GPIO 0x00000000U
217 #define TIM_TIM15_TI2_TIM2_CH2 (TIM_TISEL_TI2SEL_0)
218 #define TIM_TIM15_TI2_TIM3_CH2 (TIM_TISEL_TI2SEL_1)
219 #define TIM_TIM15_TI2_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1)
221 #define TIM_TIM16_TI1_GPIO 0x00000000U
222 #define TIM_TIM16_TI1_RCC_LSI TIM_TISEL_TI1SEL_0
223 #define TIM_TIM16_TI1_RCC_LSE TIM_TISEL_TI1SEL_1
224 #define TIM_TIM16_TI1_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1)
226 #define TIM_TIM17_TI1_GPIO 0x00000000U
227 #define TIM_TIM17_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0
228 #define TIM_TIM17_TI1_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1
229 #define TIM_TIM17_TI1_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1)
231 #define TIM_TIM23_TI4_GPIO 0x00000000U
232 #define TIM_TIM23_TI4_COMP1 TIM_TISEL_TI4SEL_0
233 #define TIM_TIM23_TI4_COMP2 TIM_TISEL_TI4SEL_1
234 #define TIM_TIM23_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1)
236 #define TIM_TIM24_TI1_GPIO 0x00000000U
237 #define TIM_TIM24_TI1_CAN_TMP TIM_TISEL_TI1SEL_0
238 #define TIM_TIM24_TI1_CAN_RTP TIM_TISEL_TI1SEL_1
239 #define TIM_TIM24_TI1_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1)
263 #define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
264 ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
266 #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
267 ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
268 ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
269 ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))
271 #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
272 ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
274 #define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
275 ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
277 #define IS_TIM_TISEL(__TISEL__) (((__TISEL__) == TIM_TIM1_TI1_GPIO) ||\
278 ((__TISEL__) == TIM_TIM1_TI1_COMP1) ||\
279 ((__TISEL__) == TIM_TIM8_TI1_GPIO) ||\
280 ((__TISEL__) == TIM_TIM8_TI1_COMP2) ||\
281 ((__TISEL__) == TIM_TIM2_TI4_GPIO) ||\
282 ((__TISEL__) == TIM_TIM2_TI4_COMP1) ||\
283 ((__TISEL__) == TIM_TIM2_TI4_COMP2) ||\
284 ((__TISEL__) == TIM_TIM2_TI4_COMP1_COMP2) ||\
285 ((__TISEL__) == TIM_TIM3_TI1_GPIO) ||\
286 ((__TISEL__) == TIM_TIM3_TI1_COMP1) ||\
287 ((__TISEL__) == TIM_TIM3_TI1_COMP2) ||\
288 ((__TISEL__) == TIM_TIM3_TI1_COMP1_COMP2) ||\
289 ((__TISEL__) == TIM_TIM5_TI1_GPIO) ||\
290 ((__TISEL__) == TIM_TIM5_TI1_CAN_TMP) ||\
291 ((__TISEL__) == TIM_TIM5_TI1_CAN_RTP) ||\
292 ((__TISEL__) == TIM_TIM12_TI1_SPDIF_FS) ||\
293 ((__TISEL__) == TIM_TIM12_TI1_GPIO) ||\
294 ((__TISEL__) == TIM_TIM15_TI1_GPIO) ||\
295 ((__TISEL__) == TIM_TIM15_TI1_TIM2_CH1) ||\
296 ((__TISEL__) == TIM_TIM15_TI1_TIM3_CH1) ||\
297 ((__TISEL__) == TIM_TIM15_TI1_TIM4_CH1) ||\
298 ((__TISEL__) == TIM_TIM15_TI1_RCC_LSE) ||\
299 ((__TISEL__) == TIM_TIM15_TI1_RCC_CSI) ||\
300 ((__TISEL__) == TIM_TIM15_TI1_RCC_MCO2) ||\
301 ((__TISEL__) == TIM_TIM15_TI2_GPIO) ||\
302 ((__TISEL__) == TIM_TIM15_TI2_TIM2_CH2) ||\
303 ((__TISEL__) == TIM_TIM15_TI2_TIM3_CH2) ||\
304 ((__TISEL__) == TIM_TIM15_TI2_TIM4_CH2) ||\
305 ((__TISEL__) == TIM_TIM16_TI1_GPIO) ||\
306 ((__TISEL__) == TIM_TIM16_TI1_RCC_LSI) ||\
307 ((__TISEL__) == TIM_TIM16_TI1_RCC_LSE) ||\
308 ((__TISEL__) == TIM_TIM16_TI1_WKUP_IT) ||\
309 ((__TISEL__) == TIM_TIM17_TI1_GPIO) ||\
310 ((__TISEL__) == TIM_TIM17_TI1_SPDIF_FS) ||\
311 ((__TISEL__) == TIM_TIM17_TI1_RCC_HSE1MHZ) ||\
312 ((__TISEL__) == TIM_TIM17_TI1_RCC_MCO1) ||\
313 ((__TISEL__) == TIM_TIM23_TI4_GPIO) ||\
314 ((__TISEL__) == TIM_TIM23_TI4_COMP1) ||\
315 ((__TISEL__) == TIM_TIM23_TI4_COMP2) ||\
316 ((__TISEL__) == TIM_TIM23_TI4_COMP1_COMP2) ||\
317 ((__TISEL__) == TIM_TIM24_TI1_GPIO) ||\
318 ((__TISEL__) == TIM_TIM24_TI1_CAN_TMP) ||\
319 ((__TISEL__) == TIM_TIM24_TI1_CAN_RTP) ||\
320 ((__TISEL__) == TIM_TIM24_TI1_CAN_SOC))
322 #define IS_TIM_REMAP(__RREMAP__) (((__RREMAP__) == TIM_TIM1_ETR_GPIO) ||\
323 ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD1) ||\
324 ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD2) ||\
325 ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD3) ||\
326 ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD1) ||\
327 ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD2) ||\
328 ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD3) ||\
329 ((__RREMAP__) == TIM_TIM1_ETR_COMP1) ||\
330 ((__RREMAP__) == TIM_TIM1_ETR_COMP2) ||\
331 ((__RREMAP__) == TIM_TIM8_ETR_GPIO) ||\
332 ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD1) ||\
333 ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD2) ||\
334 ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD3) ||\
335 ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD1) ||\
336 ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD2) ||\
337 ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD3) ||\
338 ((__RREMAP__) == TIM_TIM8_ETR_COMP1) ||\
339 ((__RREMAP__) == TIM_TIM8_ETR_COMP2) ||\
340 ((__RREMAP__) == TIM_TIM2_ETR_GPIO) ||\
341 ((__RREMAP__) == TIM_TIM2_ETR_COMP1) ||\
342 ((__RREMAP__) == TIM_TIM2_ETR_COMP2) ||\
343 ((__RREMAP__) == TIM_TIM2_ETR_RCC_LSE) ||\
344 ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSA) ||\
345 ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSB) ||\
346 ((__RREMAP__) == TIM_TIM3_ETR_GPIO) ||\
347 ((__RREMAP__) == TIM_TIM3_ETR_COMP1) ||\
348 ((__RREMAP__) == TIM_TIM5_ETR_GPIO) ||\
349 ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSA) ||\
350 ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSB) ||\
351 ((__RREMAP__) == TIM_TIM23_ETR_GPIO) ||\
352 ((__RREMAP__) == TIM_TIM23_ETR_COMP1) ||\
353 ((__RREMAP__) == TIM_TIM23_ETR_COMP2) ||\
354 ((__RREMAP__) == TIM_TIM24_ETR_GPIO) ||\
355 ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSA) ||\
356 ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSB) ||\
357 ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSA) ||\
358 ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSB))
455 uint32_t CommutationSource);
457 uint32_t CommutationSource);
459 uint32_t CommutationSource);
464 #if defined(TIM_BREAK_INPUT_SUPPORT)
466 TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
HAL_StatusTypeDef
HAL Status structures definition
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
DMA handle Structure definition.
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
TIM Hall sensor Configuration Structure definition.
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
TIM Time Base Handle Structure definition.
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
HAL_TIM_StateTypeDef
HAL State structures definition.
HAL_TIM_ChannelStateTypeDef
TIM Channel States definition.
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
TIM Master configuration Structure definition.
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN)
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
TIM Break input(s) and Dead time configuration Structure definition.
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)