Macros
Collaboration diagram for TIM Extended Remapping:

Macros

#define TIM_TIM11_GPIO   0x00000000U
 
#define TIM_TIM11_GPIO   0x00000000U
 
#define TIM_TIM11_GPIO   (0x00000000U)
 
#define TIM_TIM11_HSE   TIM_OR_TI1_RMP_1
 
#define TIM_TIM11_HSE   TIM_OR_TI1_RMP_1
 
#define TIM_TIM11_HSE   (0x00000002U)
 
#define TIM_TIM11_MCO1   (0x00000003U)
 
#define TIM_TIM11_SPDIFRX   (0x00000001U)
 
#define TIM_TIM1_ETR_ADC1_AWD1   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */
 
#define TIM_TIM1_ETR_ADC1_AWD1   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */
 
#define TIM_TIM1_ETR_ADC1_AWD2   (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */
 
#define TIM_TIM1_ETR_ADC1_AWD2   (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */
 
#define TIM_TIM1_ETR_ADC1_AWD3   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
 
#define TIM_TIM1_ETR_ADC1_AWD3   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
 
#define TIM_TIM1_ETR_ADC3_AWD1   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */
 
#define TIM_TIM1_ETR_ADC3_AWD1   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */
 
#define TIM_TIM1_ETR_ADC3_AWD2   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */
 
#define TIM_TIM1_ETR_ADC3_AWD2   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */
 
#define TIM_TIM1_ETR_ADC3_AWD3   TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */
 
#define TIM_TIM1_ETR_ADC3_AWD3   TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */
 
#define TIM_TIM1_ETR_COMP1   TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 OUT */
 
#define TIM_TIM1_ETR_COMP1   TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 OUT */
 
#define TIM_TIM1_ETR_COMP2   TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 OUT */
 
#define TIM_TIM1_ETR_COMP2   TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 OUT */
 
#define TIM_TIM1_ETR_GPIO   0x00000000U /* !< TIM1_ETR is connected to GPIO */
 
#define TIM_TIM1_ETR_GPIO   0x00000000U /* !< TIM1_ETR is connected to GPIO */
 
#define TIM_TIM23_ETR_COMP1   (TIM2_AF1_ETRSEL_0) /* !< TIM23_ETR is connected to COMP1 OUT */
 
#define TIM_TIM23_ETR_COMP1   (TIM2_AF1_ETRSEL_0) /* !< TIM23_ETR is connected to COMP1 OUT */
 
#define TIM_TIM23_ETR_COMP2   (TIM2_AF1_ETRSEL_1) /* !< TIM23_ETR is connected to COMP2 OUT */
 
#define TIM_TIM23_ETR_COMP2   (TIM2_AF1_ETRSEL_1) /* !< TIM23_ETR is connected to COMP2 OUT */
 
#define TIM_TIM23_ETR_GPIO   0x00000000U /* !< TIM23_ETR is connected to GPIO */
 
#define TIM_TIM23_ETR_GPIO   0x00000000U /* !< TIM23_ETR is connected to GPIO */
 
#define TIM_TIM24_ETR_GPIO   0x00000000U /* !< TIM24_ETR is connected to GPIO */
 
#define TIM_TIM24_ETR_GPIO   0x00000000U /* !< TIM24_ETR is connected to GPIO */
 
#define TIM_TIM24_ETR_SAI1_FSA   (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM24_ETR is connected to SAI1 FS_A */
 
#define TIM_TIM24_ETR_SAI1_FSA   (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM24_ETR is connected to SAI1 FS_A */
 
#define TIM_TIM24_ETR_SAI1_FSB   TIM2_AF1_ETRSEL_2 /* !< TIM24_ETR is connected to SAI1 FS_B */
 
#define TIM_TIM24_ETR_SAI1_FSB   TIM2_AF1_ETRSEL_2 /* !< TIM24_ETR is connected to SAI1 FS_B */
 
#define TIM_TIM24_ETR_SAI4_FSA   TIM5_AF1_ETRSEL_0 /* !< TIM24_ETR is connected to SAI4 FS_A */
 
#define TIM_TIM24_ETR_SAI4_FSA   TIM5_AF1_ETRSEL_0 /* !< TIM24_ETR is connected to SAI4 FS_A */
 
#define TIM_TIM24_ETR_SAI4_FSB   TIM5_AF1_ETRSEL_1 /* !< TIM24_ETR is connected to SAI4 FS_B */
 
#define TIM_TIM24_ETR_SAI4_FSB   TIM5_AF1_ETRSEL_1 /* !< TIM24_ETR is connected to SAI4 FS_B */
 
#define TIM_TIM2_ETH_PTP   (0x00000400U)
 
#define TIM_TIM2_ETR_COMP1   (TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 OUT */
 
#define TIM_TIM2_ETR_COMP1   (TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 OUT */
 
#define TIM_TIM2_ETR_COMP2   (TIM2_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 OUT */
 
#define TIM_TIM2_ETR_COMP2   (TIM2_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 OUT */
 
#define TIM_TIM2_ETR_GPIO   0x00000000U /* !< TIM2_ETR is connected to GPIO */
 
#define TIM_TIM2_ETR_GPIO   0x00000000U /* !< TIM2_ETR is connected to GPIO */
 
#define TIM_TIM2_ETR_RCC_LSE   (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */
 
#define TIM_TIM2_ETR_RCC_LSE   (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */
 
#define TIM_TIM2_ETR_SAI1_FSA   TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to SAI1 FS_A */
 
#define TIM_TIM2_ETR_SAI1_FSA   TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to SAI1 FS_A */
 
#define TIM_TIM2_ETR_SAI1_FSB   (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */
 
#define TIM_TIM2_ETR_SAI1_FSB   (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */
 
#define TIM_TIM2_TIM8_TRGO   (0x00000000U)
 
#define TIM_TIM2_USBFS_SOF   (0x00000800U)
 
#define TIM_TIM2_USBHS_SOF   (0x00000C00U)
 
#define TIM_TIM3_ETR_COMP1   TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 OUT */
 
#define TIM_TIM3_ETR_COMP1   TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 OUT */
 
#define TIM_TIM3_ETR_GPIO   0x00000000U /* !< TIM3_ETR is connected to GPIO */
 
#define TIM_TIM3_ETR_GPIO   0x00000000U /* !< TIM3_ETR is connected to GPIO */
 
#define TIM_TIM5_ETR_GPIO   0x00000000U /* !< TIM5_ETR is connected to GPIO */
 
#define TIM_TIM5_ETR_GPIO   0x00000000U /* !< TIM5_ETR is connected to GPIO */
 
#define TIM_TIM5_ETR_SAI2_FSA   TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI2 FS_A */
 
#define TIM_TIM5_ETR_SAI2_FSA   TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI2 FS_A */
 
#define TIM_TIM5_ETR_SAI2_FSB   TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI2 FS_B */
 
#define TIM_TIM5_ETR_SAI2_FSB   TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI2 FS_B */
 
#define TIM_TIM5_ETR_SAI4_FSA   TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI4 FS_A */
 
#define TIM_TIM5_ETR_SAI4_FSA   TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI4 FS_A */
 
#define TIM_TIM5_ETR_SAI4_FSB   TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI4 FS_B */
 
#define TIM_TIM5_ETR_SAI4_FSB   TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI4 FS_B */
 
#define TIM_TIM5_GPIO   0x00000000U
 
#define TIM_TIM5_GPIO   0x00000000U
 
#define TIM_TIM5_GPIO   (0x00000000U)
 
#define TIM_TIM5_LSE   TIM_OR_TI4_RMP_1
 
#define TIM_TIM5_LSE   TIM_OR_TI4_RMP_1
 
#define TIM_TIM5_LSE   (0x00000080U)
 
#define TIM_TIM5_LSI   TIM_OR_TI4_RMP_0
 
#define TIM_TIM5_LSI   TIM_OR_TI4_RMP_0
 
#define TIM_TIM5_LSI   (0x00000040U)
 
#define TIM_TIM5_RTC   (TIM_OR_TI4_RMP_1 | TIM_OR_TI4_RMP_0)
 
#define TIM_TIM5_RTC   (TIM_OR_TI4_RMP_1 | TIM_OR_TI4_RMP_0)
 
#define TIM_TIM5_RTC   (0x000000C0U)
 
#define TIM_TIM8_ETR_ADC2_AWD1   (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */
 
#define TIM_TIM8_ETR_ADC2_AWD1   (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */
 
#define TIM_TIM8_ETR_ADC2_AWD2   (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC2 AWD2 */
 
#define TIM_TIM8_ETR_ADC2_AWD2   (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC2 AWD2 */
 
#define TIM_TIM8_ETR_ADC2_AWD3   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */
 
#define TIM_TIM8_ETR_ADC2_AWD3   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */
 
#define TIM_TIM8_ETR_ADC3_AWD1   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /* !< TIM8_ETR is connected to ADC3 AWD1 */
 
#define TIM_TIM8_ETR_ADC3_AWD1   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /* !< TIM8_ETR is connected to ADC3 AWD1 */
 
#define TIM_TIM8_ETR_ADC3_AWD2   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */
 
#define TIM_TIM8_ETR_ADC3_AWD2   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */
 
#define TIM_TIM8_ETR_ADC3_AWD3   TIM8_AF1_ETRSEL_3 /* !< TIM8_ETR is connected to ADC3 AWD3 */
 
#define TIM_TIM8_ETR_ADC3_AWD3   TIM8_AF1_ETRSEL_3 /* !< TIM8_ETR is connected to ADC3 AWD3 */
 
#define TIM_TIM8_ETR_COMP1   TIM8_AF1_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 OUT */
 
#define TIM_TIM8_ETR_COMP1   TIM8_AF1_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 OUT */
 
#define TIM_TIM8_ETR_COMP2   TIM8_AF1_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 OUT */
 
#define TIM_TIM8_ETR_COMP2   TIM8_AF1_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 OUT */
 
#define TIM_TIM8_ETR_GPIO   0x00000000U /* !< TIM8_ETR is connected to GPIO */
 
#define TIM_TIM8_ETR_GPIO   0x00000000U /* !< TIM8_ETR is connected to GPIO */
 

Detailed Description

Macro Definition Documentation

◆ TIM_TIM11_GPIO [1/3]

#define TIM_TIM11_GPIO   0x00000000U

TIM11 TI1 is connected to GPIO

Definition at line 90 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h.

◆ TIM_TIM11_GPIO [2/3]

#define TIM_TIM11_GPIO   0x00000000U

TIM11 TI1 is connected to GPIO

Definition at line 90 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h.

◆ TIM_TIM11_GPIO [3/3]

#define TIM_TIM11_GPIO   (0x00000000U)

Definition at line 101 of file stm32f7xx_hal_tim_ex.h.

◆ TIM_TIM11_HSE [1/3]

#define TIM_TIM11_HSE   TIM_OR_TI1_RMP_1

TIM11 TI1 is connected to HSE_RTC clock

Definition at line 91 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h.

◆ TIM_TIM11_HSE [2/3]

#define TIM_TIM11_HSE   TIM_OR_TI1_RMP_1

TIM11 TI1 is connected to HSE_RTC clock

Definition at line 91 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h.

◆ TIM_TIM11_HSE [3/3]

#define TIM_TIM11_HSE   (0x00000002U)

Definition at line 103 of file stm32f7xx_hal_tim_ex.h.

◆ TIM_TIM11_MCO1

#define TIM_TIM11_MCO1   (0x00000003U)

Definition at line 104 of file stm32f7xx_hal_tim_ex.h.

◆ TIM_TIM11_SPDIFRX

#define TIM_TIM11_SPDIFRX   (0x00000001U)

Definition at line 102 of file stm32f7xx_hal_tim_ex.h.

◆ TIM_TIM1_ETR_ADC1_AWD1 [1/2]

#define TIM_TIM1_ETR_ADC1_AWD1   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */

◆ TIM_TIM1_ETR_ADC1_AWD1 [2/2]

#define TIM_TIM1_ETR_ADC1_AWD1   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */

◆ TIM_TIM1_ETR_ADC1_AWD2 [1/2]

#define TIM_TIM1_ETR_ADC1_AWD2   (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */

◆ TIM_TIM1_ETR_ADC1_AWD2 [2/2]

#define TIM_TIM1_ETR_ADC1_AWD2   (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */

◆ TIM_TIM1_ETR_ADC1_AWD3 [1/2]

#define TIM_TIM1_ETR_ADC1_AWD3   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */

◆ TIM_TIM1_ETR_ADC1_AWD3 [2/2]

#define TIM_TIM1_ETR_ADC1_AWD3   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */

◆ TIM_TIM1_ETR_ADC3_AWD1 [1/2]

#define TIM_TIM1_ETR_ADC3_AWD1   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */

◆ TIM_TIM1_ETR_ADC3_AWD1 [2/2]

#define TIM_TIM1_ETR_ADC3_AWD1   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */

◆ TIM_TIM1_ETR_ADC3_AWD2 [1/2]

#define TIM_TIM1_ETR_ADC3_AWD2   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */

◆ TIM_TIM1_ETR_ADC3_AWD2 [2/2]

#define TIM_TIM1_ETR_ADC3_AWD2   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */

◆ TIM_TIM1_ETR_ADC3_AWD3 [1/2]

#define TIM_TIM1_ETR_ADC3_AWD3   TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */

◆ TIM_TIM1_ETR_ADC3_AWD3 [2/2]

#define TIM_TIM1_ETR_ADC3_AWD3   TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */

◆ TIM_TIM1_ETR_COMP1 [1/2]

#define TIM_TIM1_ETR_COMP1   TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 OUT */

◆ TIM_TIM1_ETR_COMP1 [2/2]

#define TIM_TIM1_ETR_COMP1   TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 OUT */

◆ TIM_TIM1_ETR_COMP2 [1/2]

#define TIM_TIM1_ETR_COMP2   TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 OUT */

◆ TIM_TIM1_ETR_COMP2 [2/2]

#define TIM_TIM1_ETR_COMP2   TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 OUT */

◆ TIM_TIM1_ETR_GPIO [1/2]

#define TIM_TIM1_ETR_GPIO   0x00000000U /* !< TIM1_ETR is connected to GPIO */

◆ TIM_TIM1_ETR_GPIO [2/2]

#define TIM_TIM1_ETR_GPIO   0x00000000U /* !< TIM1_ETR is connected to GPIO */

◆ TIM_TIM23_ETR_COMP1 [1/2]

#define TIM_TIM23_ETR_COMP1   (TIM2_AF1_ETRSEL_0) /* !< TIM23_ETR is connected to COMP1 OUT */

◆ TIM_TIM23_ETR_COMP1 [2/2]

#define TIM_TIM23_ETR_COMP1   (TIM2_AF1_ETRSEL_0) /* !< TIM23_ETR is connected to COMP1 OUT */

◆ TIM_TIM23_ETR_COMP2 [1/2]

#define TIM_TIM23_ETR_COMP2   (TIM2_AF1_ETRSEL_1) /* !< TIM23_ETR is connected to COMP2 OUT */

◆ TIM_TIM23_ETR_COMP2 [2/2]

#define TIM_TIM23_ETR_COMP2   (TIM2_AF1_ETRSEL_1) /* !< TIM23_ETR is connected to COMP2 OUT */

◆ TIM_TIM23_ETR_GPIO [1/2]

#define TIM_TIM23_ETR_GPIO   0x00000000U /* !< TIM23_ETR is connected to GPIO */

◆ TIM_TIM23_ETR_GPIO [2/2]

#define TIM_TIM23_ETR_GPIO   0x00000000U /* !< TIM23_ETR is connected to GPIO */

◆ TIM_TIM24_ETR_GPIO [1/2]

#define TIM_TIM24_ETR_GPIO   0x00000000U /* !< TIM24_ETR is connected to GPIO */

◆ TIM_TIM24_ETR_GPIO [2/2]

#define TIM_TIM24_ETR_GPIO   0x00000000U /* !< TIM24_ETR is connected to GPIO */

◆ TIM_TIM24_ETR_SAI1_FSA [1/2]

#define TIM_TIM24_ETR_SAI1_FSA   (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM24_ETR is connected to SAI1 FS_A */

◆ TIM_TIM24_ETR_SAI1_FSA [2/2]

#define TIM_TIM24_ETR_SAI1_FSA   (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM24_ETR is connected to SAI1 FS_A */

◆ TIM_TIM24_ETR_SAI1_FSB [1/2]

#define TIM_TIM24_ETR_SAI1_FSB   TIM2_AF1_ETRSEL_2 /* !< TIM24_ETR is connected to SAI1 FS_B */

◆ TIM_TIM24_ETR_SAI1_FSB [2/2]

#define TIM_TIM24_ETR_SAI1_FSB   TIM2_AF1_ETRSEL_2 /* !< TIM24_ETR is connected to SAI1 FS_B */

◆ TIM_TIM24_ETR_SAI4_FSA [1/2]

#define TIM_TIM24_ETR_SAI4_FSA   TIM5_AF1_ETRSEL_0 /* !< TIM24_ETR is connected to SAI4 FS_A */

◆ TIM_TIM24_ETR_SAI4_FSA [2/2]

#define TIM_TIM24_ETR_SAI4_FSA   TIM5_AF1_ETRSEL_0 /* !< TIM24_ETR is connected to SAI4 FS_A */

◆ TIM_TIM24_ETR_SAI4_FSB [1/2]

#define TIM_TIM24_ETR_SAI4_FSB   TIM5_AF1_ETRSEL_1 /* !< TIM24_ETR is connected to SAI4 FS_B */

◆ TIM_TIM24_ETR_SAI4_FSB [2/2]

#define TIM_TIM24_ETR_SAI4_FSB   TIM5_AF1_ETRSEL_1 /* !< TIM24_ETR is connected to SAI4 FS_B */

◆ TIM_TIM2_ETH_PTP

#define TIM_TIM2_ETH_PTP   (0x00000400U)

Definition at line 94 of file stm32f7xx_hal_tim_ex.h.

◆ TIM_TIM2_ETR_COMP1 [1/2]

#define TIM_TIM2_ETR_COMP1   (TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 OUT */

◆ TIM_TIM2_ETR_COMP1 [2/2]

#define TIM_TIM2_ETR_COMP1   (TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 OUT */

◆ TIM_TIM2_ETR_COMP2 [1/2]

#define TIM_TIM2_ETR_COMP2   (TIM2_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 OUT */

◆ TIM_TIM2_ETR_COMP2 [2/2]

#define TIM_TIM2_ETR_COMP2   (TIM2_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 OUT */

◆ TIM_TIM2_ETR_GPIO [1/2]

#define TIM_TIM2_ETR_GPIO   0x00000000U /* !< TIM2_ETR is connected to GPIO */

◆ TIM_TIM2_ETR_GPIO [2/2]

#define TIM_TIM2_ETR_GPIO   0x00000000U /* !< TIM2_ETR is connected to GPIO */

◆ TIM_TIM2_ETR_RCC_LSE [1/2]

#define TIM_TIM2_ETR_RCC_LSE   (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */

◆ TIM_TIM2_ETR_RCC_LSE [2/2]

#define TIM_TIM2_ETR_RCC_LSE   (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */

◆ TIM_TIM2_ETR_SAI1_FSA [1/2]

#define TIM_TIM2_ETR_SAI1_FSA   TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to SAI1 FS_A */

◆ TIM_TIM2_ETR_SAI1_FSA [2/2]

#define TIM_TIM2_ETR_SAI1_FSA   TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to SAI1 FS_A */

◆ TIM_TIM2_ETR_SAI1_FSB [1/2]

#define TIM_TIM2_ETR_SAI1_FSB   (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */

◆ TIM_TIM2_ETR_SAI1_FSB [2/2]

#define TIM_TIM2_ETR_SAI1_FSB   (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */

◆ TIM_TIM2_TIM8_TRGO

#define TIM_TIM2_TIM8_TRGO   (0x00000000U)

Definition at line 93 of file stm32f7xx_hal_tim_ex.h.

◆ TIM_TIM2_USBFS_SOF

#define TIM_TIM2_USBFS_SOF   (0x00000800U)

Definition at line 95 of file stm32f7xx_hal_tim_ex.h.

◆ TIM_TIM2_USBHS_SOF

#define TIM_TIM2_USBHS_SOF   (0x00000C00U)

Definition at line 96 of file stm32f7xx_hal_tim_ex.h.

◆ TIM_TIM3_ETR_COMP1 [1/2]

#define TIM_TIM3_ETR_COMP1   TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 OUT */

◆ TIM_TIM3_ETR_COMP1 [2/2]

#define TIM_TIM3_ETR_COMP1   TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 OUT */

◆ TIM_TIM3_ETR_GPIO [1/2]

#define TIM_TIM3_ETR_GPIO   0x00000000U /* !< TIM3_ETR is connected to GPIO */

◆ TIM_TIM3_ETR_GPIO [2/2]

#define TIM_TIM3_ETR_GPIO   0x00000000U /* !< TIM3_ETR is connected to GPIO */

◆ TIM_TIM5_ETR_GPIO [1/2]

#define TIM_TIM5_ETR_GPIO   0x00000000U /* !< TIM5_ETR is connected to GPIO */

◆ TIM_TIM5_ETR_GPIO [2/2]

#define TIM_TIM5_ETR_GPIO   0x00000000U /* !< TIM5_ETR is connected to GPIO */

◆ TIM_TIM5_ETR_SAI2_FSA [1/2]

#define TIM_TIM5_ETR_SAI2_FSA   TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI2 FS_A */

◆ TIM_TIM5_ETR_SAI2_FSA [2/2]

#define TIM_TIM5_ETR_SAI2_FSA   TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI2 FS_A */

◆ TIM_TIM5_ETR_SAI2_FSB [1/2]

#define TIM_TIM5_ETR_SAI2_FSB   TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI2 FS_B */

◆ TIM_TIM5_ETR_SAI2_FSB [2/2]

#define TIM_TIM5_ETR_SAI2_FSB   TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI2 FS_B */

◆ TIM_TIM5_ETR_SAI4_FSA [1/2]

#define TIM_TIM5_ETR_SAI4_FSA   TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI4 FS_A */

◆ TIM_TIM5_ETR_SAI4_FSA [2/2]

#define TIM_TIM5_ETR_SAI4_FSA   TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI4 FS_A */

◆ TIM_TIM5_ETR_SAI4_FSB [1/2]

#define TIM_TIM5_ETR_SAI4_FSB   TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI4 FS_B */

◆ TIM_TIM5_ETR_SAI4_FSB [2/2]

#define TIM_TIM5_ETR_SAI4_FSB   TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI4 FS_B */

◆ TIM_TIM5_GPIO [1/3]

#define TIM_TIM5_GPIO   0x00000000U

TIM5 TI4 is connected to GPIO

Definition at line 85 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h.

◆ TIM_TIM5_GPIO [2/3]

#define TIM_TIM5_GPIO   0x00000000U

TIM5 TI4 is connected to GPIO

Definition at line 85 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h.

◆ TIM_TIM5_GPIO [3/3]

#define TIM_TIM5_GPIO   (0x00000000U)

Definition at line 97 of file stm32f7xx_hal_tim_ex.h.

◆ TIM_TIM5_LSE [1/3]

#define TIM_TIM5_LSE   TIM_OR_TI4_RMP_1

TIM5 TI4 is connected to LSE

Definition at line 87 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h.

◆ TIM_TIM5_LSE [2/3]

#define TIM_TIM5_LSE   TIM_OR_TI4_RMP_1

TIM5 TI4 is connected to LSE

Definition at line 87 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h.

◆ TIM_TIM5_LSE [3/3]

#define TIM_TIM5_LSE   (0x00000080U)

Definition at line 99 of file stm32f7xx_hal_tim_ex.h.

◆ TIM_TIM5_LSI [1/3]

#define TIM_TIM5_LSI   TIM_OR_TI4_RMP_0

TIM5 TI4 is connected to LSI

Definition at line 86 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h.

◆ TIM_TIM5_LSI [2/3]

#define TIM_TIM5_LSI   TIM_OR_TI4_RMP_0

TIM5 TI4 is connected to LSI

Definition at line 86 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h.

◆ TIM_TIM5_LSI [3/3]

#define TIM_TIM5_LSI   (0x00000040U)

Definition at line 98 of file stm32f7xx_hal_tim_ex.h.

◆ TIM_TIM5_RTC [1/3]

#define TIM_TIM5_RTC   (TIM_OR_TI4_RMP_1 | TIM_OR_TI4_RMP_0)

TIM5 TI4 is connected to the RTC wakeup interrupt

Definition at line 88 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h.

◆ TIM_TIM5_RTC [2/3]

#define TIM_TIM5_RTC   (TIM_OR_TI4_RMP_1 | TIM_OR_TI4_RMP_0)

TIM5 TI4 is connected to the RTC wakeup interrupt

Definition at line 88 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h.

◆ TIM_TIM5_RTC [3/3]

#define TIM_TIM5_RTC   (0x000000C0U)

Definition at line 100 of file stm32f7xx_hal_tim_ex.h.

◆ TIM_TIM8_ETR_ADC2_AWD1 [1/2]

#define TIM_TIM8_ETR_ADC2_AWD1   (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */

◆ TIM_TIM8_ETR_ADC2_AWD1 [2/2]

#define TIM_TIM8_ETR_ADC2_AWD1   (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */

◆ TIM_TIM8_ETR_ADC2_AWD2 [1/2]

#define TIM_TIM8_ETR_ADC2_AWD2   (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC2 AWD2 */

◆ TIM_TIM8_ETR_ADC2_AWD2 [2/2]

#define TIM_TIM8_ETR_ADC2_AWD2   (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC2 AWD2 */

◆ TIM_TIM8_ETR_ADC2_AWD3 [1/2]

#define TIM_TIM8_ETR_ADC2_AWD3   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */

◆ TIM_TIM8_ETR_ADC2_AWD3 [2/2]

#define TIM_TIM8_ETR_ADC2_AWD3   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */

◆ TIM_TIM8_ETR_ADC3_AWD1 [1/2]

#define TIM_TIM8_ETR_ADC3_AWD1   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /* !< TIM8_ETR is connected to ADC3 AWD1 */

◆ TIM_TIM8_ETR_ADC3_AWD1 [2/2]

#define TIM_TIM8_ETR_ADC3_AWD1   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /* !< TIM8_ETR is connected to ADC3 AWD1 */

◆ TIM_TIM8_ETR_ADC3_AWD2 [1/2]

#define TIM_TIM8_ETR_ADC3_AWD2   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */

◆ TIM_TIM8_ETR_ADC3_AWD2 [2/2]

#define TIM_TIM8_ETR_ADC3_AWD2   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */

◆ TIM_TIM8_ETR_ADC3_AWD3 [1/2]

#define TIM_TIM8_ETR_ADC3_AWD3   TIM8_AF1_ETRSEL_3 /* !< TIM8_ETR is connected to ADC3 AWD3 */

◆ TIM_TIM8_ETR_ADC3_AWD3 [2/2]

#define TIM_TIM8_ETR_ADC3_AWD3   TIM8_AF1_ETRSEL_3 /* !< TIM8_ETR is connected to ADC3 AWD3 */

◆ TIM_TIM8_ETR_COMP1 [1/2]

#define TIM_TIM8_ETR_COMP1   TIM8_AF1_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 OUT */

◆ TIM_TIM8_ETR_COMP1 [2/2]

#define TIM_TIM8_ETR_COMP1   TIM8_AF1_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 OUT */

◆ TIM_TIM8_ETR_COMP2 [1/2]

#define TIM_TIM8_ETR_COMP2   TIM8_AF1_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 OUT */

◆ TIM_TIM8_ETR_COMP2 [2/2]

#define TIM_TIM8_ETR_COMP2   TIM8_AF1_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 OUT */

◆ TIM_TIM8_ETR_GPIO [1/2]

#define TIM_TIM8_ETR_GPIO   0x00000000U /* !< TIM8_ETR is connected to GPIO */

◆ TIM_TIM8_ETR_GPIO [2/2]

#define TIM_TIM8_ETR_GPIO   0x00000000U /* !< TIM8_ETR is connected to GPIO */


picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:15:07