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enum | HAL_TIM_ActiveChannel {
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U,
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U,
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U,
HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U,
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U,
HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U,
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U,
HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U
} |
| HAL Active channel structures definition. More...
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enum | HAL_TIM_ActiveChannel {
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U,
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U,
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U,
HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U,
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U,
HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U,
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U,
HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U
} |
| HAL Active channel structures definition. More...
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enum | HAL_TIM_ActiveChannel {
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U,
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U,
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U,
HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U,
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U,
HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U,
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U,
HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U
} |
| HAL Active channel structures definition. More...
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enum | HAL_TIM_ActiveChannel {
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U,
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U,
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U,
HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U,
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U,
HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U,
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U,
HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U
} |
| HAL Active channel structures definition. More...
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enum | HAL_TIM_ActiveChannel {
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U,
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U,
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U,
HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U,
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U,
HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U,
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U,
HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U
} |
| HAL Active channel structures definition. More...
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enum | HAL_TIM_ChannelStateTypeDef {
HAL_TIM_CHANNEL_STATE_RESET = 0x00U,
HAL_TIM_CHANNEL_STATE_READY = 0x01U,
HAL_TIM_CHANNEL_STATE_BUSY = 0x02U,
HAL_TIM_CHANNEL_STATE_RESET = 0x00U,
HAL_TIM_CHANNEL_STATE_READY = 0x01U,
HAL_TIM_CHANNEL_STATE_BUSY = 0x02U
} |
| TIM Channel States definition. More...
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enum | HAL_TIM_ChannelStateTypeDef {
HAL_TIM_CHANNEL_STATE_RESET = 0x00U,
HAL_TIM_CHANNEL_STATE_READY = 0x01U,
HAL_TIM_CHANNEL_STATE_BUSY = 0x02U,
HAL_TIM_CHANNEL_STATE_RESET = 0x00U,
HAL_TIM_CHANNEL_STATE_READY = 0x01U,
HAL_TIM_CHANNEL_STATE_BUSY = 0x02U
} |
| TIM Channel States definition. More...
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enum | HAL_TIM_DMABurstStateTypeDef {
HAL_DMA_BURST_STATE_RESET = 0x00U,
HAL_DMA_BURST_STATE_READY = 0x01U,
HAL_DMA_BURST_STATE_BUSY = 0x02U,
HAL_DMA_BURST_STATE_RESET = 0x00U,
HAL_DMA_BURST_STATE_READY = 0x01U,
HAL_DMA_BURST_STATE_BUSY = 0x02U
} |
| DMA Burst States definition. More...
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enum | HAL_TIM_DMABurstStateTypeDef {
HAL_DMA_BURST_STATE_RESET = 0x00U,
HAL_DMA_BURST_STATE_READY = 0x01U,
HAL_DMA_BURST_STATE_BUSY = 0x02U,
HAL_DMA_BURST_STATE_RESET = 0x00U,
HAL_DMA_BURST_STATE_READY = 0x01U,
HAL_DMA_BURST_STATE_BUSY = 0x02U
} |
| DMA Burst States definition. More...
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enum | HAL_TIM_StateTypeDef {
HAL_TIM_STATE_RESET = 0x00U,
HAL_TIM_STATE_READY = 0x01U,
HAL_TIM_STATE_BUSY = 0x02U,
HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U,
HAL_TIM_STATE_RESET = 0x00U,
HAL_TIM_STATE_READY = 0x01U,
HAL_TIM_STATE_BUSY = 0x02U,
HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U,
HAL_TIM_STATE_RESET = 0x00U,
HAL_TIM_STATE_READY = 0x01U,
HAL_TIM_STATE_BUSY = 0x02U,
HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U,
HAL_TIM_STATE_RESET = 0x00U,
HAL_TIM_STATE_READY = 0x01U,
HAL_TIM_STATE_BUSY = 0x02U,
HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U,
HAL_TIM_STATE_RESET = 0x00U,
HAL_TIM_STATE_READY = 0x01U,
HAL_TIM_STATE_BUSY = 0x02U,
HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U
} |
| HAL State structures definition. More...
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enum | HAL_TIM_StateTypeDef {
HAL_TIM_STATE_RESET = 0x00U,
HAL_TIM_STATE_READY = 0x01U,
HAL_TIM_STATE_BUSY = 0x02U,
HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U,
HAL_TIM_STATE_RESET = 0x00U,
HAL_TIM_STATE_READY = 0x01U,
HAL_TIM_STATE_BUSY = 0x02U,
HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U,
HAL_TIM_STATE_RESET = 0x00U,
HAL_TIM_STATE_READY = 0x01U,
HAL_TIM_STATE_BUSY = 0x02U,
HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U,
HAL_TIM_STATE_RESET = 0x00U,
HAL_TIM_STATE_READY = 0x01U,
HAL_TIM_STATE_BUSY = 0x02U,
HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U,
HAL_TIM_STATE_RESET = 0x00U,
HAL_TIM_STATE_READY = 0x01U,
HAL_TIM_STATE_BUSY = 0x02U,
HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U
} |
| HAL State structures definition. More...
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enum | HAL_TIM_StateTypeDef {
HAL_TIM_STATE_RESET = 0x00U,
HAL_TIM_STATE_READY = 0x01U,
HAL_TIM_STATE_BUSY = 0x02U,
HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U,
HAL_TIM_STATE_RESET = 0x00U,
HAL_TIM_STATE_READY = 0x01U,
HAL_TIM_STATE_BUSY = 0x02U,
HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U,
HAL_TIM_STATE_RESET = 0x00U,
HAL_TIM_STATE_READY = 0x01U,
HAL_TIM_STATE_BUSY = 0x02U,
HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U,
HAL_TIM_STATE_RESET = 0x00U,
HAL_TIM_STATE_READY = 0x01U,
HAL_TIM_STATE_BUSY = 0x02U,
HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U,
HAL_TIM_STATE_RESET = 0x00U,
HAL_TIM_STATE_READY = 0x01U,
HAL_TIM_STATE_BUSY = 0x02U,
HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U
} |
| HAL State structures definition. More...
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enum | HAL_TIM_StateTypeDef {
HAL_TIM_STATE_RESET = 0x00U,
HAL_TIM_STATE_READY = 0x01U,
HAL_TIM_STATE_BUSY = 0x02U,
HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U,
HAL_TIM_STATE_RESET = 0x00U,
HAL_TIM_STATE_READY = 0x01U,
HAL_TIM_STATE_BUSY = 0x02U,
HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U,
HAL_TIM_STATE_RESET = 0x00U,
HAL_TIM_STATE_READY = 0x01U,
HAL_TIM_STATE_BUSY = 0x02U,
HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U,
HAL_TIM_STATE_RESET = 0x00U,
HAL_TIM_STATE_READY = 0x01U,
HAL_TIM_STATE_BUSY = 0x02U,
HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U,
HAL_TIM_STATE_RESET = 0x00U,
HAL_TIM_STATE_READY = 0x01U,
HAL_TIM_STATE_BUSY = 0x02U,
HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U
} |
| HAL State structures definition. More...
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enum | HAL_TIM_StateTypeDef {
HAL_TIM_STATE_RESET = 0x00U,
HAL_TIM_STATE_READY = 0x01U,
HAL_TIM_STATE_BUSY = 0x02U,
HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U,
HAL_TIM_STATE_RESET = 0x00U,
HAL_TIM_STATE_READY = 0x01U,
HAL_TIM_STATE_BUSY = 0x02U,
HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U,
HAL_TIM_STATE_RESET = 0x00U,
HAL_TIM_STATE_READY = 0x01U,
HAL_TIM_STATE_BUSY = 0x02U,
HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U,
HAL_TIM_STATE_RESET = 0x00U,
HAL_TIM_STATE_READY = 0x01U,
HAL_TIM_STATE_BUSY = 0x02U,
HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U,
HAL_TIM_STATE_RESET = 0x00U,
HAL_TIM_STATE_READY = 0x01U,
HAL_TIM_STATE_BUSY = 0x02U,
HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U
} |
| HAL State structures definition. More...
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