utils/cmsis/same70/include/component/rtc.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_RTC_COMPONENT_
36 #define _SAME70_RTC_COMPONENT_
37 
38 /* ============================================================================= */
40 /* ============================================================================= */
43 
44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
45 
46 typedef struct {
47  __IO uint32_t RTC_CR;
48  __IO uint32_t RTC_MR;
49  __IO uint32_t RTC_TIMR;
50  __IO uint32_t RTC_CALR;
51  __IO uint32_t RTC_TIMALR;
52  __IO uint32_t RTC_CALALR;
53  __I uint32_t RTC_SR;
54  __O uint32_t RTC_SCCR;
55  __O uint32_t RTC_IER;
56  __O uint32_t RTC_IDR;
57  __I uint32_t RTC_IMR;
58  __I uint32_t RTC_VER;
59  __I uint32_t Reserved1[45];
60  __IO uint32_t RTC_WPMR;
61  __I uint32_t Reserved2[5];
62  __I uint32_t RTC_VERSION;
63 } Rtc;
64 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
65 /* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
66 #define RTC_CR_UPDTIM (0x1u << 0)
67 #define RTC_CR_UPDCAL (0x1u << 1)
68 #define RTC_CR_TIMEVSEL_Pos 8
69 #define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos)
70 #define RTC_CR_TIMEVSEL(value) ((RTC_CR_TIMEVSEL_Msk & ((value) << RTC_CR_TIMEVSEL_Pos)))
71 #define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8)
72 #define RTC_CR_TIMEVSEL_HOUR (0x1u << 8)
73 #define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8)
74 #define RTC_CR_TIMEVSEL_NOON (0x3u << 8)
75 #define RTC_CR_CALEVSEL_Pos 16
76 #define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos)
77 #define RTC_CR_CALEVSEL(value) ((RTC_CR_CALEVSEL_Msk & ((value) << RTC_CR_CALEVSEL_Pos)))
78 #define RTC_CR_CALEVSEL_WEEK (0x0u << 16)
79 #define RTC_CR_CALEVSEL_MONTH (0x1u << 16)
80 #define RTC_CR_CALEVSEL_YEAR (0x2u << 16)
81 /* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
82 #define RTC_MR_HRMOD (0x1u << 0)
83 #define RTC_MR_PERSIAN (0x1u << 1)
84 #define RTC_MR_NEGPPM (0x1u << 4)
85 #define RTC_MR_CORRECTION_Pos 8
86 #define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos)
87 #define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos)))
88 #define RTC_MR_HIGHPPM (0x1u << 15)
89 #define RTC_MR_OUT0_Pos 16
90 #define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos)
91 #define RTC_MR_OUT0(value) ((RTC_MR_OUT0_Msk & ((value) << RTC_MR_OUT0_Pos)))
92 #define RTC_MR_OUT0_NO_WAVE (0x0u << 16)
93 #define RTC_MR_OUT0_FREQ1HZ (0x1u << 16)
94 #define RTC_MR_OUT0_FREQ32HZ (0x2u << 16)
95 #define RTC_MR_OUT0_FREQ64HZ (0x3u << 16)
96 #define RTC_MR_OUT0_FREQ512HZ (0x4u << 16)
97 #define RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16)
98 #define RTC_MR_OUT0_ALARM_FLAG (0x6u << 16)
99 #define RTC_MR_OUT0_PROG_PULSE (0x7u << 16)
100 #define RTC_MR_OUT1_Pos 20
101 #define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos)
102 #define RTC_MR_OUT1(value) ((RTC_MR_OUT1_Msk & ((value) << RTC_MR_OUT1_Pos)))
103 #define RTC_MR_OUT1_NO_WAVE (0x0u << 20)
104 #define RTC_MR_OUT1_FREQ1HZ (0x1u << 20)
105 #define RTC_MR_OUT1_FREQ32HZ (0x2u << 20)
106 #define RTC_MR_OUT1_FREQ64HZ (0x3u << 20)
107 #define RTC_MR_OUT1_FREQ512HZ (0x4u << 20)
108 #define RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20)
109 #define RTC_MR_OUT1_ALARM_FLAG (0x6u << 20)
110 #define RTC_MR_OUT1_PROG_PULSE (0x7u << 20)
111 #define RTC_MR_THIGH_Pos 24
112 #define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos)
113 #define RTC_MR_THIGH(value) ((RTC_MR_THIGH_Msk & ((value) << RTC_MR_THIGH_Pos)))
114 #define RTC_MR_THIGH_H_31MS (0x0u << 24)
115 #define RTC_MR_THIGH_H_16MS (0x1u << 24)
116 #define RTC_MR_THIGH_H_4MS (0x2u << 24)
117 #define RTC_MR_THIGH_H_976US (0x3u << 24)
118 #define RTC_MR_THIGH_H_488US (0x4u << 24)
119 #define RTC_MR_THIGH_H_122US (0x5u << 24)
120 #define RTC_MR_THIGH_H_30US (0x6u << 24)
121 #define RTC_MR_THIGH_H_15US (0x7u << 24)
122 #define RTC_MR_TPERIOD_Pos 28
123 #define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos)
124 #define RTC_MR_TPERIOD(value) ((RTC_MR_TPERIOD_Msk & ((value) << RTC_MR_TPERIOD_Pos)))
125 #define RTC_MR_TPERIOD_P_1S (0x0u << 28)
126 #define RTC_MR_TPERIOD_P_500MS (0x1u << 28)
127 #define RTC_MR_TPERIOD_P_250MS (0x2u << 28)
128 #define RTC_MR_TPERIOD_P_125MS (0x3u << 28)
129 /* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
130 #define RTC_TIMR_SEC_Pos 0
131 #define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos)
132 #define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
133 #define RTC_TIMR_MIN_Pos 8
134 #define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos)
135 #define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
136 #define RTC_TIMR_HOUR_Pos 16
137 #define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos)
138 #define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
139 #define RTC_TIMR_AMPM (0x1u << 22)
140 /* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
141 #define RTC_CALR_CENT_Pos 0
142 #define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos)
143 #define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
144 #define RTC_CALR_YEAR_Pos 8
145 #define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos)
146 #define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
147 #define RTC_CALR_MONTH_Pos 16
148 #define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos)
149 #define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
150 #define RTC_CALR_DAY_Pos 21
151 #define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos)
152 #define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
153 #define RTC_CALR_DATE_Pos 24
154 #define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos)
155 #define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
156 /* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
157 #define RTC_TIMALR_SEC_Pos 0
158 #define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos)
159 #define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
160 #define RTC_TIMALR_SECEN (0x1u << 7)
161 #define RTC_TIMALR_MIN_Pos 8
162 #define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos)
163 #define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
164 #define RTC_TIMALR_MINEN (0x1u << 15)
165 #define RTC_TIMALR_HOUR_Pos 16
166 #define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos)
167 #define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
168 #define RTC_TIMALR_AMPM (0x1u << 22)
169 #define RTC_TIMALR_HOUREN (0x1u << 23)
170 /* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
171 #define RTC_CALALR_MONTH_Pos 16
172 #define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos)
173 #define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
174 #define RTC_CALALR_MTHEN (0x1u << 23)
175 #define RTC_CALALR_DATE_Pos 24
176 #define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos)
177 #define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
178 #define RTC_CALALR_DATEEN (0x1u << 31)
179 /* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
180 #define RTC_SR_ACKUPD (0x1u << 0)
181 #define RTC_SR_ACKUPD_FREERUN (0x0u << 0)
182 #define RTC_SR_ACKUPD_UPDATE (0x1u << 0)
183 #define RTC_SR_ALARM (0x1u << 1)
184 #define RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1)
185 #define RTC_SR_ALARM_ALARMEVENT (0x1u << 1)
186 #define RTC_SR_SEC (0x1u << 2)
187 #define RTC_SR_SEC_NO_SECEVENT (0x0u << 2)
188 #define RTC_SR_SEC_SECEVENT (0x1u << 2)
189 #define RTC_SR_TIMEV (0x1u << 3)
190 #define RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3)
191 #define RTC_SR_TIMEV_TIMEVENT (0x1u << 3)
192 #define RTC_SR_CALEV (0x1u << 4)
193 #define RTC_SR_CALEV_NO_CALEVENT (0x0u << 4)
194 #define RTC_SR_CALEV_CALEVENT (0x1u << 4)
195 #define RTC_SR_TDERR (0x1u << 5)
196 #define RTC_SR_TDERR_CORRECT (0x0u << 5)
197 #define RTC_SR_TDERR_ERR_TIMEDATE (0x1u << 5)
198 /* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
199 #define RTC_SCCR_ACKCLR (0x1u << 0)
200 #define RTC_SCCR_ALRCLR (0x1u << 1)
201 #define RTC_SCCR_SECCLR (0x1u << 2)
202 #define RTC_SCCR_TIMCLR (0x1u << 3)
203 #define RTC_SCCR_CALCLR (0x1u << 4)
204 #define RTC_SCCR_TDERRCLR (0x1u << 5)
205 /* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
206 #define RTC_IER_ACKEN (0x1u << 0)
207 #define RTC_IER_ALREN (0x1u << 1)
208 #define RTC_IER_SECEN (0x1u << 2)
209 #define RTC_IER_TIMEN (0x1u << 3)
210 #define RTC_IER_CALEN (0x1u << 4)
211 #define RTC_IER_TDERREN (0x1u << 5)
212 /* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
213 #define RTC_IDR_ACKDIS (0x1u << 0)
214 #define RTC_IDR_ALRDIS (0x1u << 1)
215 #define RTC_IDR_SECDIS (0x1u << 2)
216 #define RTC_IDR_TIMDIS (0x1u << 3)
217 #define RTC_IDR_CALDIS (0x1u << 4)
218 #define RTC_IDR_TDERRDIS (0x1u << 5)
219 /* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
220 #define RTC_IMR_ACK (0x1u << 0)
221 #define RTC_IMR_ALR (0x1u << 1)
222 #define RTC_IMR_SEC (0x1u << 2)
223 #define RTC_IMR_TIM (0x1u << 3)
224 #define RTC_IMR_CAL (0x1u << 4)
225 #define RTC_IMR_TDERR (0x1u << 5)
226 /* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
227 #define RTC_VER_NVTIM (0x1u << 0)
228 #define RTC_VER_NVCAL (0x1u << 1)
229 #define RTC_VER_NVTIMALR (0x1u << 2)
230 #define RTC_VER_NVCALALR (0x1u << 3)
231 /* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protection Mode Register -------- */
232 #define RTC_WPMR_WPEN (0x1u << 0)
233 #define RTC_WPMR_WPKEY_Pos 8
234 #define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos)
235 #define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos)))
236 #define RTC_WPMR_WPKEY_PASSWD (0x525443u << 8)
237 /* -------- RTC_VERSION : (RTC Offset: 0xFC) Version Register -------- */
238 #define RTC_VERSION_VERSION_Pos 0
239 #define RTC_VERSION_VERSION_Msk (0xfffu << RTC_VERSION_VERSION_Pos)
240 #define RTC_VERSION_MFN_Pos 16
241 #define RTC_VERSION_MFN_Msk (0x7u << RTC_VERSION_MFN_Pos)
244 
245 
246 #endif /* _SAME70_RTC_COMPONENT_ */
__O uint32_t RTC_IDR
(Rtc Offset: 0x24) Interrupt Disable Register
__IO uint32_t RTC_CALALR
(Rtc Offset: 0x14) Calendar Alarm Register
__I uint32_t RTC_VER
(Rtc Offset: 0x2C) Valid Entry Register
#define __IO
Definition: core_cm7.h:266
#define __O
Definition: core_cm7.h:265
__IO uint32_t RTC_CR
(Rtc Offset: 0x00) Control Register
__I uint32_t RTC_VERSION
(Rtc Offset: 0xFC) Version Register
__IO uint32_t RTC_WPMR
(Rtc Offset: 0xE4) Write Protection Mode Register
__IO uint32_t RTC_CALR
(Rtc Offset: 0x0C) Calendar Register
__O uint32_t RTC_IER
(Rtc Offset: 0x20) Interrupt Enable Register
__I uint32_t RTC_SR
(Rtc Offset: 0x18) Status Register
__IO uint32_t RTC_TIMR
(Rtc Offset: 0x08) Time Register
__IO uint32_t RTC_MR
(Rtc Offset: 0x04) Mode Register
__IO uint32_t RTC_TIMALR
(Rtc Offset: 0x10) Time Alarm Register
__O uint32_t RTC_SCCR
(Rtc Offset: 0x1C) Status Clear Command Register
#define __I
Definition: core_cm7.h:263
__I uint32_t RTC_IMR
(Rtc Offset: 0x28) Interrupt Mask Register
Rtc hardware registers.


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autogenerated on Sat Sep 19 2020 03:19:04