Structure type to access the Trace Port Interface Register (TPI). More...

#include <core_cm7.h>

Public Attributes
__IO uint32_t	ACPR

__IO uint32_t	CLAIMCLR

__IO uint32_t	CLAIMSET

__IO uint32_t	CSPSR

__I uint32_t	DEVID

__I uint32_t	DEVTYPE

__IO uint32_t	FFCR

__I uint32_t	FFSR

__I uint32_t	FIFO0

__I uint32_t	FIFO1

__I uint32_t	FSCR

__I uint32_t	ITATBCTR0

__I uint32_t	ITATBCTR2

__IO uint32_t	ITCTRL

uint32_t	RESERVED0 [2]

uint32_t	RESERVED1 [55]

uint32_t	RESERVED2 [131]

uint32_t	RESERVED3 [759]

uint32_t	RESERVED4 [1]

uint32_t	RESERVED5 [39]

uint32_t	RESERVED7 [8]

__IO uint32_t	SPPR

__IO uint32_t	SSPSR

__I uint32_t	TRIGGER

Detailed Description

Structure type to access the Trace Port Interface Register (TPI).

Definition at line 1132 of file core_cm7.h.

Member Data Documentation

◆ ACPR

__IO uint32_t TPI_Type::ACPR

Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register

Definition at line 1137 of file core_cm7.h.

◆ CLAIMCLR

__IO uint32_t TPI_Type::CLAIMCLR

Offset: 0xFA4 (R/W) Claim tag clear

Definition at line 1154 of file core_cm7.h.

◆ CLAIMSET

__IO uint32_t TPI_Type::CLAIMSET

Offset: 0xFA0 (R/W) Claim tag set

Definition at line 1153 of file core_cm7.h.

◆ CSPSR

__IO uint32_t TPI_Type::CSPSR

Offset: 0x004 (R/W) Current Parallel Port Size Register

Definition at line 1135 of file core_cm7.h.

◆ DEVID

__I uint32_t TPI_Type::DEVID

Offset: 0xFC8 (R/ ) TPIU_DEVID

Definition at line 1156 of file core_cm7.h.

◆ DEVTYPE

__I uint32_t TPI_Type::DEVTYPE

Offset: 0xFCC (R/ ) TPIU_DEVTYPE

Definition at line 1157 of file core_cm7.h.

◆ FFCR

__IO uint32_t TPI_Type::FFCR

Offset: 0x304 (R/W) Formatter and Flush Control Register

Definition at line 1142 of file core_cm7.h.

◆ FFSR

__I uint32_t TPI_Type::FFSR

Offset: 0x300 (R/ ) Formatter and Flush Status Register

Definition at line 1141 of file core_cm7.h.

◆ FIFO0

__I uint32_t TPI_Type::FIFO0

Offset: 0xEEC (R/ ) Integration ETM Data

Definition at line 1146 of file core_cm7.h.

◆ FIFO1

__I uint32_t TPI_Type::FIFO1

Offset: 0xEFC (R/ ) Integration ITM Data

Definition at line 1150 of file core_cm7.h.

◆ FSCR

__I uint32_t TPI_Type::FSCR

Offset: 0x308 (R/ ) Formatter Synchronization Counter Register

Definition at line 1143 of file core_cm7.h.

◆ ITATBCTR0

__I uint32_t TPI_Type::ITATBCTR0

Offset: 0xEF8 (R/ ) ITATBCTR0

Definition at line 1149 of file core_cm7.h.

◆ ITATBCTR2

__I uint32_t TPI_Type::ITATBCTR2

Offset: 0xEF0 (R/ ) ITATBCTR2

Definition at line 1147 of file core_cm7.h.

◆ ITCTRL

__IO uint32_t TPI_Type::ITCTRL

Offset: 0xF00 (R/W) Integration Mode Control

Definition at line 1151 of file core_cm7.h.

◆ RESERVED0

uint32_t TPI_Type::RESERVED0[2]

Definition at line 1136 of file core_cm7.h.

◆ RESERVED1

uint32_t TPI_Type::RESERVED1[55]

Definition at line 1138 of file core_cm7.h.

◆ RESERVED2

uint32_t TPI_Type::RESERVED2[131]

Definition at line 1140 of file core_cm7.h.

◆ RESERVED3

uint32_t TPI_Type::RESERVED3[759]

Definition at line 1144 of file core_cm7.h.

◆ RESERVED4

uint32_t TPI_Type::RESERVED4[1]

Definition at line 1148 of file core_cm7.h.

◆ RESERVED5

uint32_t TPI_Type::RESERVED5[39]

Definition at line 1152 of file core_cm7.h.

◆ RESERVED7

uint32_t TPI_Type::RESERVED7[8]

Definition at line 1155 of file core_cm7.h.

◆ SPPR

__IO uint32_t TPI_Type::SPPR

Offset: 0x0F0 (R/W) Selected Pin Protocol Register

Definition at line 1139 of file core_cm7.h.

◆ SSPSR

__IO uint32_t TPI_Type::SSPSR

Offset: 0x000 (R/ ) Supported Parallel Port Size Register

Definition at line 1134 of file core_cm7.h.

◆ TRIGGER

__I uint32_t TPI_Type::TRIGGER

Offset: 0xEE8 (R/ ) TRIGGER

Definition at line 1145 of file core_cm7.h.

The documentation for this struct was generated from the following file:

core_cm7.h

Public Attributes