hsmci.c
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1 
33 /*
34  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
35  */
36 
37 #include <asf.h>
38 #include "conf_board.h"
39 #include "sd_mmc_protocol.h"
40 #include "sysclk.h"
41 #include "pmc.h"
42 #include "hsmci.h"
43 
52 // Check configurations
53 #if (!defined SD_MMC_HSMCI_MEM_CNT) || (SD_MMC_HSMCI_MEM_CNT == 0)
54 # warning SD_MMC_HSMCI_MEM_CNT must be defined in board.h file.
55 # define SD_MMC_HSMCI_MEM_CNT 1
56 #endif
57 #ifndef CONF_BOARD_SD_MMC_HSMCI
58 # warning CONF_BOARD_SD_MMC_HSMCI must be defined in conf_board.h file.
59 #endif
60 #if (SAM3XA)
61 # if (SD_MMC_HSMCI_MEM_CNT > 2)
62 # warning Wrong define SD_MMC_HSMCI_MEM_CNT in board.h,\
63  this part have 2 slots maximum on HSMCI.
64 # endif
65 #else
66 # if (SD_MMC_HSMCI_MEM_CNT > 1)
67 # warning Wrong define SD_MMC_HSMCI_MEM_CNT in board.h,\
68  this part have 1 slots maximum on HSMCI.
69 # endif
70 #endif
71 #ifndef SD_MMC_HSMCI_SLOT_0_SIZE
72 # warning SD_MMC_HSMCI_SLOT_0_SIZE must be defined in board.h.
73 # define SD_MMC_HSMCI_SLOT_0_SIZE 1
74 #endif
75 #if (SD_MMC_HSMCI_MEM_CNT > 2)
76 # ifndef SD_MMC_HSMCI_SLOT_1_SIZE
77 # warning SD_MMC_HSMCI_SLOT_1_SIZE must be defined in board.h.
78 # define SD_MMC_HSMCI_SLOT_1_SIZE 1
79 # endif
80 #endif
81 
82 // Enable debug information for SD/MMC SPI module
83 #ifdef HSMCI_DEBUG
84 # include <stdio.h>
85 # define hsmci_debug(...) printf(__VA_ARGS__)
86 #else
87 # define hsmci_debug(...)
88 #endif
89 
90 #if (SAM3S || SAM4S || SAM4E)
91  // PDC is used for transfer
92 #elif (SAM3U || SAM3XA)
93  // DMA is used for transfer
94 # include "dmac.h"
95 # define DMA_HW_ID_HSMCI 0
96 # ifndef CONF_HSMCI_DMA_CHANNEL
97 # define CONF_HSMCI_DMA_CHANNEL 0
98 # endif
99 #elif (SAMV70 || SAMV71 || SAME70 || SAMS70)
100  // XDMAC is used for transfer
101 # include "xdmac.h"
102 # define XDMAC_HW_ID_HSMCI 0
103 # ifndef CONF_HSMCI_XDMAC_CHANNEL
104 # define CONF_HSMCI_XDMAC_CHANNEL DMA_CH_SD_CARD
105 # endif
106 #else
107 # error Not supported device
108 #endif
109 
111 static uint32_t hsmci_transfert_pos;
113 static uint16_t hsmci_block_size;
115 static uint16_t hsmci_nb_block;
116 
117 static void hsmci_reset(void);
118 static void hsmci_set_speed(uint32_t speed, uint32_t mck);
119 static bool hsmci_wait_busy(void);
120 static bool hsmci_send_cmd_execute(uint32_t cmdr, sdmmc_cmd_def_t cmd,
121  uint32_t arg);
122 
126 static void hsmci_reset(void)
127 {
128  uint32_t mr = HSMCI->HSMCI_MR;
129  uint32_t dtor = HSMCI->HSMCI_DTOR;
130  uint32_t sdcr = HSMCI->HSMCI_SDCR;
131  uint32_t cstor = HSMCI->HSMCI_CSTOR;
132  uint32_t cfg = HSMCI->HSMCI_CFG;
133  HSMCI->HSMCI_CR = HSMCI_CR_SWRST;
134  HSMCI->HSMCI_MR = mr;
135  HSMCI->HSMCI_DTOR = dtor;
136  HSMCI->HSMCI_SDCR = sdcr;
137  HSMCI->HSMCI_CSTOR = cstor;
138  HSMCI->HSMCI_CFG = cfg;
139 #ifdef HSMCI_SR_DMADONE
140  HSMCI->HSMCI_DMA = 0;
141 #endif
142 #if (SAMV70 || SAMV71 || SAME70 || SAMS70)
143 #ifdef HSMCI_DMA_DMAEN
144  HSMCI->HSMCI_DMA = 0;
145 #endif
146 #endif
147  // Enable the HSMCI
148  HSMCI->HSMCI_CR = HSMCI_CR_PWSEN | HSMCI_CR_MCIEN;
149 }
150 
157 static void hsmci_set_speed(uint32_t speed, uint32_t mck)
158 {
159 #if (SAM4E || SAMV70 || SAMV71 || SAME70 || SAMS70)
160  uint32_t clkdiv = 0;
161  uint32_t clkodd = 0;
162  // clock divider, represent (((clkdiv << 1) + clkodd) + 2)
163  uint32_t div = 0;
164 
165  // Speed = MCK clock / (((clkdiv << 1) + clkodd) + 2)
166  if ((speed * 2) < mck) {
167  div = (mck / speed) - 2;
168  if (mck % speed) {
169  // Ensure that the card speed not be higher than expected.
170  div++;
171  }
172  clkdiv = div >> 1;
173  // clkodd is the last significant bit of the clock divider (div).
174  clkodd = div % 2;
175  } else {
176  clkdiv = 0;
177  clkodd = 0;
178  }
179 
180  HSMCI->HSMCI_MR &= ~HSMCI_MR_CLKDIV_Msk;
181  HSMCI->HSMCI_MR |= HSMCI_MR_CLKDIV(clkdiv);
182  if (clkodd) {
183  HSMCI->HSMCI_MR |= HSMCI_MR_CLKODD;
184  }
185  else {
186  HSMCI->HSMCI_MR &= ~HSMCI_MR_CLKODD;
187  }
188 #else
189  uint32_t clkdiv = 0;
190  uint32_t rest = 0;
191 
192  // Speed = MCK clock / (2 * (CLKDIV + 1))
193  if ((speed * 2) < mck) {
194  clkdiv = mck / (2 * speed);
195  rest = mck % (2 * speed);
196  if (rest > 0) {
197  // Ensure that the card speed not be higher than expected.
198  clkdiv++;
199  }
200  if (clkdiv > 0) {
201  clkdiv -= 1;
202  }
203  } else {
204  clkdiv = 0;
205  }
206  HSMCI->HSMCI_MR &= ~HSMCI_MR_CLKDIV_Msk;
207  HSMCI->HSMCI_MR |= HSMCI_MR_CLKDIV(clkdiv);
208 #endif
209 
210 }
211 
216 static bool hsmci_wait_busy(void)
217 {
218  uint32_t busy_wait = 0xFFFFFFFF;
219  uint32_t sr;
220 
221  do {
222  sr = HSMCI->HSMCI_SR;
223  if (busy_wait-- == 0) {
224  hsmci_debug("%s: timeout\n\r", __func__);
225  hsmci_reset();
226  return false;
227  }
228  } while (!((sr & HSMCI_SR_NOTBUSY) && ((sr & HSMCI_SR_DTIP) == 0)));
229  return true;
230 }
231 
232 
241 static bool hsmci_send_cmd_execute(uint32_t cmdr, sdmmc_cmd_def_t cmd,
242  uint32_t arg)
243 {
244  uint32_t sr;
245 
246  cmdr |= HSMCI_CMDR_CMDNB(cmd) | HSMCI_CMDR_SPCMD_STD;
247  if (cmd & SDMMC_RESP_PRESENT) {
248  cmdr |= HSMCI_CMDR_MAXLAT;
249  if (cmd & SDMMC_RESP_136) {
251  } else if (cmd & SDMMC_RESP_BUSY) {
252  cmdr |= HSMCI_CMDR_RSPTYP_R1B;
253  } else {
254  cmdr |= HSMCI_CMDR_RSPTYP_48_BIT;
255  }
256  }
257  if (cmd & SDMMC_CMD_OPENDRAIN) {
259  }
260 
261  // Write argument
262  HSMCI->HSMCI_ARGR = arg;
263  // Write and start command
264  HSMCI->HSMCI_CMDR = cmdr;
265 
266  // Wait end of command
267  do {
268  sr = HSMCI->HSMCI_SR;
269  if (cmd & SDMMC_RESP_CRC) {
270  if (sr & (HSMCI_SR_CSTOE | HSMCI_SR_RTOE
273  hsmci_debug("%s: CMD 0x%08x sr 0x%08x error\n\r",
274  __func__, cmd, sr);
275  hsmci_reset();
276  return false;
277  }
278  } else {
279  if (sr & (HSMCI_SR_CSTOE | HSMCI_SR_RTOE
282  hsmci_debug("%s: CMD 0x%08x sr 0x%08x error\n\r",
283  __func__, cmd, sr);
284  hsmci_reset();
285  return false;
286  }
287  }
288  } while (!(sr & HSMCI_SR_CMDRDY));
289 
290  if (cmd & SDMMC_RESP_BUSY) {
291  if (!hsmci_wait_busy()) {
292  return false;
293  }
294  }
295  return true;
296 }
297 
298 
299 //-------------------------------------------------------------------
300 //--------------------- PUBLIC FUNCTIONS ----------------------------
301 
302 void hsmci_init(void)
303 {
305 #ifdef HSMCI_SR_DMADONE
306  // Enable clock for DMA controller
307  pmc_enable_periph_clk(ID_DMAC);
308 #endif
309 
310 #if (SAMV70 || SAMV71 || SAME70 || SAMS70)
311 #ifdef HSMCI_DMA_DMAEN
312  // Enable clock for DMA controller
314 #endif
315 #endif
316 
317  // Set the Data Timeout Register to 2 Mega Cycles
319  // Set Completion Signal Timeout to 2 Mega Cycles
321  // Set Configuration Register
323  // Set power saving to maximum value
324  HSMCI->HSMCI_MR = HSMCI_MR_PWSDIV_Msk;
325 
326  // Enable the HSMCI and the Power Saving
327  HSMCI->HSMCI_CR = HSMCI_CR_MCIEN | HSMCI_CR_PWSEN;
328 }
329 
330 uint8_t hsmci_get_bus_width(uint8_t slot)
331 {
332  switch (slot) {
333  case 0:
335 #if (SD_MMC_HSMCI_MEM_CNT == 2)
336  case 1:
337  return SD_MMC_HSMCI_SLOT_1_SIZE;
338 #endif
339  default:
340  return 0; // Slot number wrong
341  }
342 }
343 
345 {
346  return true;
347 }
348 
349 void hsmci_select_device(uint8_t slot, uint32_t clock, uint8_t bus_width, bool high_speed)
350 {
351  uint32_t hsmci_slot = HSMCI_SDCR_SDCSEL_SLOTA;
352  uint32_t hsmci_bus_width = HSMCI_SDCR_SDCBUS_1;
353 
354  if (high_speed) {
355  HSMCI->HSMCI_CFG |= HSMCI_CFG_HSMODE;
356  } else {
357  HSMCI->HSMCI_CFG &= ~HSMCI_CFG_HSMODE;
358  }
359 
361 
362  switch (slot) {
363  case 0:
364  hsmci_slot = HSMCI_SDCR_SDCSEL_SLOTA;
365  break;
366 #if (SD_MMC_HSMCI_MEM_CNT == 2)
367  case 1:
368  hsmci_slot = HSMCI_SDCR_SDCSEL_SLOTB;
369  break;
370 #endif
371  default:
372  Assert(false); // Slot number wrong
373  }
374 
375  switch (bus_width) {
376  case 1:
377  hsmci_bus_width = HSMCI_SDCR_SDCBUS_1;
378  break;
379 
380  case 4:
381  hsmci_bus_width = HSMCI_SDCR_SDCBUS_4;
382  break;
383 
384  case 8:
385  hsmci_bus_width = HSMCI_SDCR_SDCBUS_8;
386  break;
387 
388  default:
389  Assert(false); // Bus width wrong
390  }
391  HSMCI->HSMCI_SDCR = hsmci_slot | hsmci_bus_width;
392 }
393 
394 void hsmci_deselect_device(uint8_t slot)
395 {
396  UNUSED(slot);
397  // Nothing to do
398 }
399 
401 {
402  // Configure command
404  // Write argument
405  HSMCI->HSMCI_ARGR = 0;
406  // Write and start initialization command
407  HSMCI->HSMCI_CMDR = HSMCI_CMDR_RSPTYP_NORESP
410  // Wait end of initialization command
411  while (!(HSMCI->HSMCI_SR & HSMCI_SR_CMDRDY));
412 }
413 
414 bool hsmci_send_cmd(sdmmc_cmd_def_t cmd, uint32_t arg)
415 {
416  // Configure command
418 #ifdef HSMCI_SR_DMADONE
419  // Disable DMA for HSMCI
420  HSMCI->HSMCI_DMA = 0;
421 #endif
422 #ifdef HSMCI_MR_PDCMODE
423  // Disable PDC for HSMCI
424  HSMCI->HSMCI_MR &= ~HSMCI_MR_PDCMODE;
425 #endif
426 #if (SAMV70 || SAMV71 || SAME70 || SAMS70)
427 #ifdef HSMCI_DMA_DMAEN
428  // Disable DMA for HSMCI
429  HSMCI->HSMCI_DMA = 0;
430 #endif
431 #endif
432  HSMCI->HSMCI_BLKR = 0;
433  return hsmci_send_cmd_execute(0, cmd, arg);
434 }
435 
436 uint32_t hsmci_get_response(void)
437 {
438  return HSMCI->HSMCI_RSPR[0];
439 }
440 
441 void hsmci_get_response_128(uint8_t* response)
442 {
443  uint32_t response_32;
444 
445  for (uint8_t i = 0; i < 4; i++) {
446  response_32 = HSMCI->HSMCI_RSPR[0];
447  *response = (response_32 >> 24) & 0xFF;
448  response++;
449  *response = (response_32 >> 16) & 0xFF;
450  response++;
451  *response = (response_32 >> 8) & 0xFF;
452  response++;
453  *response = (response_32 >> 0) & 0xFF;
454  response++;
455  }
456 }
457 
458 bool hsmci_adtc_start(sdmmc_cmd_def_t cmd, uint32_t arg, uint16_t block_size, uint16_t nb_block, bool access_block)
459 {
460  uint32_t cmdr;
461 
462 #ifdef HSMCI_SR_DMADONE
463  if (access_block) {
464  // Enable DMA for HSMCI
465  HSMCI->HSMCI_DMA = HSMCI_DMA_DMAEN;
466  } else {
467  // Disable DMA for HSMCI
468  HSMCI->HSMCI_DMA = 0;
469  }
470 #endif
471 
472 #ifdef HSMCI_MR_PDCMODE
473  if (access_block) {
474  // Enable PDC for HSMCI
475  HSMCI->HSMCI_MR |= HSMCI_MR_PDCMODE;
476  } else {
477  // Disable PDC for HSMCI
478  HSMCI->HSMCI_MR &= ~HSMCI_MR_PDCMODE;
479  }
480 #endif
481 
482 #if (SAMV70 || SAMV71 || SAME70 || SAMS70)
483 #ifdef HSMCI_DMA_DMAEN
484  if (access_block) {
485  // Enable DMA for HSMCI
486  HSMCI->HSMCI_DMA = HSMCI_DMA_DMAEN;
487  } else {
488  // Disable DMA for HSMCI
489  HSMCI->HSMCI_DMA = 0;
490  }
491 #endif
492 #endif
493  // Enabling Read/Write Proof allows to stop the HSMCI Clock during
494  // read/write access if the internal FIFO is full.
495  // This will guarantee data integrity, not bandwidth.
496  HSMCI->HSMCI_MR |= HSMCI_MR_WRPROOF | HSMCI_MR_RDPROOF;
497  // Force byte transfer if needed
498  if (block_size & 0x3) {
499  HSMCI->HSMCI_MR |= HSMCI_MR_FBYTE;
500  } else {
501  HSMCI->HSMCI_MR &= ~HSMCI_MR_FBYTE;
502  }
503 
504  if (cmd & SDMMC_CMD_WRITE) {
506  } else {
508  }
509 
510  if (cmd & SDMMC_CMD_SDIO_BYTE) {
511  cmdr |= HSMCI_CMDR_TRTYP_BYTE;
512  // Value 0 corresponds to a 512-byte transfer
513  HSMCI->HSMCI_BLKR = ((block_size % 512) << HSMCI_BLKR_BCNT_Pos);
514  } else {
515  HSMCI->HSMCI_BLKR = (block_size << HSMCI_BLKR_BLKLEN_Pos) |
516  (nb_block << HSMCI_BLKR_BCNT_Pos);
517  if (cmd & SDMMC_CMD_SDIO_BLOCK) {
518  cmdr |= HSMCI_CMDR_TRTYP_BLOCK;
519  } else if (cmd & SDMMC_CMD_STREAM) {
520  cmdr |= HSMCI_CMDR_TRTYP_STREAM;
521  } else if (cmd & SDMMC_CMD_SINGLE_BLOCK) {
522  cmdr |= HSMCI_CMDR_TRTYP_SINGLE;
523  } else if (cmd & SDMMC_CMD_MULTI_BLOCK) {
525  } else {
526  Assert(false); // Incorrect flags
527  }
528  }
530  hsmci_block_size = block_size;
531  hsmci_nb_block = nb_block;
532 
533  return hsmci_send_cmd_execute(cmdr, cmd, arg);
534 }
535 
536 bool hsmci_adtc_stop(sdmmc_cmd_def_t cmd, uint32_t arg)
537 {
539 }
540 
541 bool hsmci_read_word(uint32_t* value)
542 {
543  uint32_t sr;
544 
546 
547  // Wait data available
548  do {
549  sr = HSMCI->HSMCI_SR;
550  if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | \
552  hsmci_debug("%s: DMA sr 0x%08x error\n\r",
553  __func__, sr);
554  hsmci_reset();
555  return false;
556  }
557  } while (!(sr & HSMCI_SR_RXRDY));
558 
559  // Read data
560  *value = HSMCI->HSMCI_RDR;
561  hsmci_transfert_pos += 4;
562  if (((uint32_t)hsmci_block_size * hsmci_nb_block) > hsmci_transfert_pos) {
563  return true;
564  }
565 
566  // Wait end of transfer
567  // Note: no need of timeout, because it is include in HSMCI
568  do {
569  sr = HSMCI->HSMCI_SR;
570  if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | \
572  hsmci_debug("%s: DMA sr 0x%08x error\n\r",
573  __func__, sr);
574  hsmci_reset();
575  return false;
576  }
577  } while (!(sr & HSMCI_SR_XFRDONE));
578  return true;
579 }
580 
581 bool hsmci_write_word(uint32_t value)
582 {
583  uint32_t sr;
584 
586 
587  // Wait data available
588  do {
589  sr = HSMCI->HSMCI_SR;
590  if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | \
592  hsmci_debug("%s: DMA sr 0x%08x error\n\r",
593  __func__, sr);
594  hsmci_reset();
595  return false;
596  }
597  } while (!(sr & HSMCI_SR_TXRDY));
598 
599  // Write data
600  HSMCI->HSMCI_TDR = value;
601  hsmci_transfert_pos += 4;
602  if (((uint32_t)hsmci_block_size * hsmci_nb_block) > hsmci_transfert_pos) {
603  return true;
604  }
605 
606  // Wait end of transfer
607  // Note: no need of timeout, because it is include in HSMCI, see DTOE bit.
608  do {
609  sr = HSMCI->HSMCI_SR;
610  if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | \
612  hsmci_debug("%s: DMA sr 0x%08x error\n\r",
613  __func__, sr);
614  hsmci_reset();
615  return false;
616  }
617  } while (!(sr & HSMCI_SR_NOTBUSY));
618  Assert(HSMCI->HSMCI_SR & HSMCI_SR_FIFOEMPTY);
619  return true;
620 }
621 
622 #ifdef HSMCI_SR_DMADONE
623 bool hsmci_start_read_blocks(void *dest, uint16_t nb_block)
624 {
625  uint32_t cfg, nb_data;
626  dma_transfer_descriptor_t desc;
627  bool transfert_byte;
628 
629  nb_data = nb_block * hsmci_block_size;
630  transfert_byte = ((HSMCI->HSMCI_MR & HSMCI_MR_FBYTE) || (((uint32_t)dest & 0x3) > 0)) ? 1 : 0;
631 
632  Assert(nb_data <= (((uint32_t)hsmci_block_size * hsmci_nb_block) - hsmci_transfert_pos));
633  Assert(nb_data <= (transfert_byte ?
634  DMAC_CTRLA_BTSIZE_Msk >> DMAC_CTRLA_BTSIZE_Pos :
635  ((DMAC_CTRLA_BTSIZE_Msk >> DMAC_CTRLA_BTSIZE_Pos) * 4)));
636 
637  /* Set channel configuration register
638  * - Enable stop on done
639  * - Hardware Selection for the Source
640  * - Source with Peripheral identifier
641  * - Set AHB Protection
642  * - FIFO Configuration
643  */
644  dmac_enable(DMAC);
645  dmac_channel_disable(DMAC, CONF_HSMCI_DMA_CHANNEL);
646  cfg = DMAC_CFG_SOD_ENABLE | DMAC_CFG_SRC_H2SEL |
647  DMAC_CFG_SRC_PER(DMA_HW_ID_HSMCI) |
648  DMAC_CFG_AHB_PROT(1) | DMAC_CFG_FIFOCFG_ALAP_CFG;
649  dmac_channel_set_configuration(DMAC, CONF_HSMCI_DMA_CHANNEL, cfg);
650 
651  // Prepare DMA transfer
652  desc.ul_source_addr = (uint32_t)&(HSMCI->HSMCI_RDR);
653  desc.ul_destination_addr = (uint32_t)dest;
654  if (transfert_byte) {
655  desc.ul_ctrlA = DMAC_CTRLA_BTSIZE(nb_data)
656  | DMAC_CTRLA_SRC_WIDTH_BYTE
657  | DMAC_CTRLA_DST_WIDTH_BYTE;
658  } else {
659  desc.ul_ctrlA = DMAC_CTRLA_BTSIZE(nb_data / 4)
660  | DMAC_CTRLA_SRC_WIDTH_WORD
661  | DMAC_CTRLA_DST_WIDTH_WORD;
662  }
663  desc.ul_ctrlB = DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE
664  | DMAC_CTRLB_DST_DSCR_FETCH_DISABLE
665  | DMAC_CTRLB_FC_PER2MEM_DMA_FC
666  | DMAC_CTRLB_SRC_INCR_FIXED
667  | DMAC_CTRLB_DST_INCR_INCREMENTING
668  | DMAC_CTRLB_IEN;
669  desc.ul_descriptor_addr = (uint32_t)NULL;
670  dmac_channel_single_buf_transfer_init(DMAC, CONF_HSMCI_DMA_CHANNEL,
671  &desc);
672 
673  // Start DMA transfer
674  dmac_channel_enable(DMAC, CONF_HSMCI_DMA_CHANNEL);
675  hsmci_transfert_pos += nb_data;
676  return true;
677 }
678 
680 {
681  uint32_t sr;
682  // Wait end of transfer
683  // Note: no need of timeout, because it is include in HSMCI
684  do {
685  sr = HSMCI->HSMCI_SR;
686  if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | \
688  hsmci_debug("%s: DMA sr 0x%08x error\n\r",
689  __func__, sr);
690  hsmci_reset();
691  // Disable DMA
692  dmac_channel_disable(DMAC, CONF_HSMCI_DMA_CHANNEL);
693  return false;
694  }
696  // It is not the end of all transfers
697  // then just wait end of DMA
698  if (sr & HSMCI_SR_DMADONE) {
699  return true;
700  }
701  }
702  } while (!(sr & HSMCI_SR_XFRDONE));
703  return true;
704 }
705 
706 bool hsmci_start_write_blocks(const void *src, uint16_t nb_block)
707 {
708  bool transfert_byte;
709  uint32_t cfg, nb_data;
710  dma_transfer_descriptor_t desc;
711 
712  nb_data = nb_block * hsmci_block_size;
713  transfert_byte = ((HSMCI->HSMCI_MR & HSMCI_MR_FBYTE) || (((uint32_t)src & 0x3) > 0)) ? 1 : 0;
714 
715  Assert(nb_data <= (((uint32_t)hsmci_block_size * hsmci_nb_block) - hsmci_transfert_pos));
716  Assert(nb_data <= (transfert_byte ?
717  DMAC_CTRLA_BTSIZE_Msk >> DMAC_CTRLA_BTSIZE_Pos :
718  ((DMAC_CTRLA_BTSIZE_Msk >> DMAC_CTRLA_BTSIZE_Pos) * 4)));
719 
720  /* Set channel configuration register:
721  * - Enable stop on done
722  * - Hardware Selection for the Destination
723  * - Destination with Peripheral identifier
724  * - Set AHB Protection
725  * - FIFO Configuration
726  */
727  dmac_enable(DMAC);
728  Assert(!dmac_channel_is_enable(DMAC, CONF_HSMCI_DMA_CHANNEL));
729  cfg = DMAC_CFG_SOD_ENABLE | DMAC_CFG_DST_H2SEL |
730  DMAC_CFG_DST_PER(DMA_HW_ID_HSMCI) |
731  DMAC_CFG_AHB_PROT(1) | DMAC_CFG_FIFOCFG_ALAP_CFG;
732  dmac_channel_set_configuration(DMAC, CONF_HSMCI_DMA_CHANNEL, cfg);
733 
734  // Prepare DMA transfer
735  desc.ul_source_addr = (uint32_t)src;
736  desc.ul_destination_addr = (uint32_t)&(HSMCI->HSMCI_TDR);
737  if (transfert_byte) {
738  desc.ul_ctrlA = DMAC_CTRLA_BTSIZE(nb_data)
739  | DMAC_CTRLA_SRC_WIDTH_BYTE
740  | DMAC_CTRLA_DST_WIDTH_BYTE;
741  } else {
742  desc.ul_ctrlA = DMAC_CTRLA_BTSIZE(nb_data / 4)
743  | DMAC_CTRLA_SRC_WIDTH_WORD
744  | DMAC_CTRLA_DST_WIDTH_WORD;
745  }
746  desc.ul_ctrlB = DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE
747  | DMAC_CTRLB_DST_DSCR_FETCH_DISABLE
748  | DMAC_CTRLB_FC_MEM2PER_DMA_FC
749  | DMAC_CTRLB_SRC_INCR_INCREMENTING
750  | DMAC_CTRLB_DST_INCR_FIXED
751  | DMAC_CTRLB_IEN;
752  desc.ul_descriptor_addr = (uint32_t)NULL;
753  dmac_channel_single_buf_transfer_init(DMAC, CONF_HSMCI_DMA_CHANNEL,
754  &desc);
755 
756  // Start DMA transfer
757  dmac_channel_enable(DMAC, CONF_HSMCI_DMA_CHANNEL);
758  hsmci_transfert_pos += nb_data;
759  return true;
760 }
761 
763 {
764  uint32_t sr;
765  // Wait end of transfer
766  // Note: no need of timeout, because it is include in HSMCI, see DTOE bit.
767  do {
768  sr = HSMCI->HSMCI_SR;
769  if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | \
771  hsmci_debug("%s: DMA sr 0x%08x error\n\r",
772  __func__, sr);
773  hsmci_reset();
774  // Disable DMA
775  dmac_channel_disable(DMAC, CONF_HSMCI_DMA_CHANNEL);
776  return false;
777  }
779  // It is not the end of all transfers
780  // then just wait end of DMA
781  if (sr & HSMCI_SR_DMADONE) {
782  return true;
783  }
784  }
785  } while (!(sr & HSMCI_SR_NOTBUSY));
786  Assert(HSMCI->HSMCI_SR & HSMCI_SR_FIFOEMPTY);
787  Assert(!dmac_channel_is_enable(DMAC, CONF_HSMCI_DMA_CHANNEL));
788  return true;
789 
790 }
791 #endif // HSMCI_SR_DMADONE
792 
793 #ifdef HSMCI_MR_PDCMODE
794 bool hsmci_start_read_blocks(void *dest, uint16_t nb_block)
795 {
796  uint32_t nb_data;
797 
798  nb_data = nb_block * hsmci_block_size;
799  Assert(nb_data <= (((uint32_t)hsmci_block_size * hsmci_nb_block) - hsmci_transfert_pos));
800  Assert(nb_data <= (PERIPH_RCR_RXCTR_Msk >> PERIPH_RCR_RXCTR_Pos));
801 
802  // Handle unaligned memory address
803  if (((uint32_t)dest & 0x3) || (hsmci_block_size & 0x3)) {
804  HSMCI->HSMCI_MR |= HSMCI_MR_FBYTE;
805  } else {
806  HSMCI->HSMCI_MR &= ~HSMCI_MR_FBYTE;
807  }
808 
809  // Configure PDC transfer
810  HSMCI->HSMCI_RPR = (uint32_t)dest;
811  HSMCI->HSMCI_RCR = (HSMCI->HSMCI_MR & HSMCI_MR_FBYTE) ?
812  nb_data : nb_data / 4;
813  HSMCI->HSMCI_RNCR = 0;
814  // Start transfer
815  HSMCI->HSMCI_PTCR = HSMCI_PTCR_RXTEN;
816  hsmci_transfert_pos += nb_data;
817  return true;
818 }
819 
821 {
822  uint32_t sr;
823  // Wait end of transfer
824  // Note: no need of timeout, because it is include in HSMCI, see DTOE bit.
825  do {
826  sr = HSMCI->HSMCI_SR;
827  if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | \
829  hsmci_debug("%s: PDC sr 0x%08x error\n\r",
830  __func__, sr);
831  HSMCI->HSMCI_PTCR = HSMCI_PTCR_RXTDIS | HSMCI_PTCR_TXTDIS;
832  hsmci_reset();
833  return false;
834  }
835 
836  } while (!(sr & HSMCI_SR_RXBUFF));
837 
839  return true;
840  }
841  // It is the last transfer, then wait command completed
842  // Note: no need of timeout, because it is include in HSMCI, see DTOE bit.
843  do {
844  sr = HSMCI->HSMCI_SR;
845  if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | \
847  hsmci_debug("%s: PDC sr 0x%08x last transfer error\n\r",
848  __func__, sr);
849  hsmci_reset();
850  return false;
851  }
852  } while (!(sr & HSMCI_SR_XFRDONE));
853  return true;
854 }
855 
856 bool hsmci_start_write_blocks(const void *src, uint16_t nb_block)
857 {
858  uint32_t nb_data;
859 
860  nb_data = nb_block * hsmci_block_size;
861  Assert(nb_data <= (((uint32_t)hsmci_block_size * hsmci_nb_block) - hsmci_transfert_pos));
862  Assert(nb_data <= (PERIPH_TCR_TXCTR_Msk >> PERIPH_TCR_TXCTR_Pos));
863 
864  // Handle unaligned memory address
865  if (((uint32_t)src & 0x3) || (hsmci_block_size & 0x3)) {
866  HSMCI->HSMCI_MR |= HSMCI_MR_FBYTE;
867  } else {
868  HSMCI->HSMCI_MR &= ~HSMCI_MR_FBYTE;
869  }
870 
871  // Configure PDC transfer
872  HSMCI->HSMCI_TPR = (uint32_t)src;
873  HSMCI->HSMCI_TCR = (HSMCI->HSMCI_MR & HSMCI_MR_FBYTE) ?
874  nb_data : nb_data / 4;
875  HSMCI->HSMCI_TNCR = 0;
876  // Start transfer
877  HSMCI->HSMCI_PTCR = HSMCI_PTCR_TXTEN;
878  hsmci_transfert_pos += nb_data;
879  return true;
880 }
881 
883 {
884  uint32_t sr;
885 
886  // Wait end of transfer
887  // Note: no need of timeout, because it is include in HSMCI, see DTOE bit.
888  do {
889  sr = HSMCI->HSMCI_SR;
890  if (sr &
893  hsmci_debug("%s: PDC sr 0x%08x error\n\r",
894  __func__, sr);
895  hsmci_reset();
896  HSMCI->HSMCI_PTCR = HSMCI_PTCR_RXTDIS | HSMCI_PTCR_TXTDIS;
897  return false;
898  }
899  } while (!(sr & HSMCI_SR_TXBUFE));
900 
901 
903  return true;
904  }
905  // It is the last transfer, then wait command completed
906  // Note: no need of timeout, because it is include in HSMCI, see DTOE bit.
907  do {
908  sr = HSMCI->HSMCI_SR;
909  if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | \
911  hsmci_debug("%s: PDC sr 0x%08x last transfer error\n\r",
912  __func__, sr);
913  hsmci_reset();
914  return false;
915  }
916  } while (!(sr & HSMCI_SR_NOTBUSY));
917  Assert(HSMCI->HSMCI_SR & HSMCI_SR_FIFOEMPTY);
918  return true;
919 }
920 #endif // HSMCI_MR_PDCMODE
921 
922 #if (SAMV70 || SAMV71 || SAME70 || SAMS70)
923 #ifdef HSMCI_DMA_DMAEN
924 bool hsmci_start_read_blocks(void *dest, uint16_t nb_block)
925 {
926  xdmac_channel_config_t p_cfg = {0, 0, 0, 0, 0, 0, 0, 0};
927  uint32_t nb_data;
928 
929  Assert(nb_block);
930  Assert(dest);
931 
933 
934  nb_data = nb_block * hsmci_block_size;
935 
936  if((uint32_t)dest & 3) {
947  p_cfg.mbr_ubc = nb_data;
948  HSMCI->HSMCI_MR |= HSMCI_MR_FBYTE;
949  } else {
960  p_cfg.mbr_ubc = nb_data / 4;
961  HSMCI->HSMCI_MR &= ~HSMCI_MR_FBYTE;
962  }
963  p_cfg.mbr_sa = (uint32_t)&(HSMCI->HSMCI_FIFO[0]);
964  p_cfg.mbr_da = (uint32_t)dest;
967  hsmci_transfert_pos += nb_data;
968  return true;
969 }
970 
972 {
973  uint32_t sr;
974  uint32_t dma_sr;
975  // Wait end of transfer
976  // Note: no need of timeout, because it is include in HSMCI
977  do {
978  sr = HSMCI->HSMCI_SR;
979  if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | \
981  hsmci_debug("%s: DMA sr 0x%08x error\n\r",
982  __func__, sr);
983  hsmci_reset();
984  // Disable XDMAC
986  return false;
987  }
989  // It is not the end of all transfers
990  // then just wait end of DMA
992  if (dma_sr & XDMAC_CIS_BIS) {
993  return true;
994  }
995  }
996  } while (!(sr & HSMCI_SR_XFRDONE));
997  return true;
998 }
999 
1000 bool hsmci_start_write_blocks(const void *src, uint16_t nb_block)
1001 {
1002  xdmac_channel_config_t p_cfg = {0, 0, 0, 0, 0, 0, 0, 0};
1003  uint32_t nb_data;
1004 
1005  Assert(nb_block);
1006  Assert(dest);
1007 
1009 
1010  nb_data = nb_block * hsmci_block_size;
1011 
1012  if((uint32_t)src & 3) {
1023  p_cfg.mbr_ubc = nb_data;
1024  HSMCI->HSMCI_MR |= HSMCI_MR_FBYTE;
1025  } else {
1036  p_cfg.mbr_ubc = nb_data / 4;
1037  HSMCI->HSMCI_MR &= ~HSMCI_MR_FBYTE;
1038  }
1039  p_cfg.mbr_sa = (uint32_t)src;
1040  p_cfg.mbr_da = (uint32_t)&(HSMCI->HSMCI_FIFO[0]);
1043  hsmci_transfert_pos += nb_data;
1044  return true;
1045 }
1046 
1048 {
1049  uint32_t sr;
1050  uint32_t dma_sr;
1051  // Wait end of transfer
1052  // Note: no need of timeout, because it is include in HSMCI
1053  do {
1054  sr = HSMCI->HSMCI_SR;
1055  if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | \
1057  hsmci_debug("%s: DMA sr 0x%08x error\n\r",
1058  __func__, sr);
1059  hsmci_reset();
1060  // Disable XDMAC
1062  return false;
1063  }
1064  if (((uint32_t)hsmci_block_size * hsmci_nb_block) > hsmci_transfert_pos) {
1065  // It is not the end of all transfers
1066  // then just wait end of DMA
1068  if (dma_sr & XDMAC_CIS_BIS) {
1069  return true;
1070  }
1071  }
1072  } while (!(sr & HSMCI_SR_XFRDONE));
1073 
1074  return true;
1075 }
1076 #endif // HSMCI_DMA_DMAEN
1077 #endif
#define HSMCI_MR_WRPROOF
(HSMCI_MR) Write Proof Enable
#define HSMCI_MR_CLKDIV(value)
#define XDMAC_CC_DSYNC_MEM2PER
(XDMAC_CC) Memory to Peripheral transfer
#define HSMCI_MR_CLKODD
(HSMCI_MR) Clock divider is odd
static void hsmci_set_speed(uint32_t speed, uint32_t mck)
Set speed of the HSMCI clock.
Definition: hsmci.c:157
#define HSMCI_CMDR_RSPTYP_NORESP
(HSMCI_CMDR) No response
#define UNUSED(v)
Marking v as a unused parameter or value.
Definition: compiler.h:86
bool hsmci_adtc_start(sdmmc_cmd_def_t cmd, uint32_t arg, uint16_t block_size, uint16_t nb_block, bool access_block)
Send an ADTC command on the selected slot An ADTC (Addressed Data Transfer Commands) command is used ...
Definition: hsmci.c:458
#define XDMAC_CC_DWIDTH_WORD
(XDMAC_CC) The data size is set to 32 bits
void hsmci_select_device(uint8_t slot, uint32_t clock, uint8_t bus_width, bool high_speed)
Select a slot and initialize it.
Definition: hsmci.c:349
#define HSMCI_CMDR_RSPTYP_136_BIT
(HSMCI_CMDR) 136-bit response
#define ID_XDMAC
DMA (XDMAC)
Definition: same70j19.h:443
SD/MMC protocol definitions.
#define HSMCI_SDCR_SDCBUS_8
(HSMCI_SDCR) 8 bits
#define XDMAC_CC_TYPE_PER_TRAN
(XDMAC_CC) Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).
bool hsmci_read_word(uint32_t *value)
Read a word on the line.
Definition: hsmci.c:541
static uint32_t hsmci_transfert_pos
Current position (byte) of the transfer started by hsmci_adtc_start()
Definition: hsmci.c:111
#define HSMCI_CMDR_TRTYP_BYTE
(HSMCI_CMDR) SDIO Byte
#define HSMCI_SR_FIFOEMPTY
(HSMCI_SR) FIFO empty flag
#define XDMAC_CC_SAM_FIXED_AM
(XDMAC_CC) The address remains unchanged.
uint32_t hsmci_get_response(void)
Return the 32 bits response of the last command.
Definition: hsmci.c:436
bool hsmci_wait_end_of_read_blocks(void)
Wait the end of transfer initiated by mci_start_read_blocks()
static void hsmci_reset(void)
Reset the HSMCI interface.
Definition: hsmci.c:126
#define HSMCI_CMDR_TRTYP_STREAM
(HSMCI_CMDR) MMC Stream
#define HSMCI_SR_NOTBUSY
(HSMCI_SR) HSMCI Not Busy
#define HSMCI_CFG_HSMODE
(HSMCI_CFG) High Speed Mode
#define HSMCI_SR_RCRCE
(HSMCI_SR) Response CRC Error (cleared by writing in HSMCI_CMDR)
GeneratorWrapper< T > value(T &&value)
Definition: catch.hpp:3589
#define XDMAC
(XDMAC ) Base Address
Definition: same70j19.h:520
#define CONF_HSMCI_XDMAC_CHANNEL
Definition: conf_board.h:59
#define HSMCI_SR_DTOE
(HSMCI_SR) Data Time-out Error (cleared on read)
#define SDMMC_CMD_SINGLE_BLOCK
To signal a data transfer in single block mode.
#define HSMCI_CMDR_TRTYP_MULTIPLE
(HSMCI_CMDR) MMC/SD Card Multiple Block
#define HSMCI_CMDR_TRCMD_START_DATA
(HSMCI_CMDR) Start data transfer
#define HSMCI_CMDR_OPDCMD_OPENDRAIN
(HSMCI_CMDR) Open drain command.
#define SDMMC_CMD_OPENDRAIN
#define HSMCI_SR_UNRE
(HSMCI_SR) Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL...
#define HSMCI_CSTOR_CSTOCYC(value)
uint32_t pmc_enable_periph_clk(uint32_t ul_id)
Enable the specified peripheral clock.
Definition: pmc.c:682
#define HSMCI_SDCR_SDCBUS_4
(HSMCI_SDCR) 4 bits
#define HSMCI_SR_CMDRDY
(HSMCI_SR) Command Ready (cleared by writing in HSMCI_CMDR)
#define NULL
Definition: nm_bsp.h:52
#define HSMCI_SR_CSTOE
(HSMCI_SR) Completion Signal Time-out Error (cleared on read)
void hsmci_init(void)
Initializes the low level driver.
Definition: hsmci.c:302
void hsmci_get_response_128(uint8_t *response)
Return the 128 bits response of the last command.
Definition: hsmci.c:441
#define HSMCI_SDCR_SDCBUS_1
(HSMCI_SDCR) 1 bit
#define SDMMC_RESP_BUSY
Card may send busy.
static uint32_t xdmac_channel_get_interrupt_status(Xdmac *xdmac, uint32_t channel_num)
Get interrupt status for the relevant channel of given XDMA.
#define XDMAC_CC_DAM_FIXED_AM
(XDMAC_CC) The address remains unchanged.
#define HSMCI_CMDR_SPCMD_INIT
(HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence.
#define HSMCI_CMDR_TRTYP_BLOCK
(HSMCI_CMDR) SDIO Block
#define HSMCI_DTOR_DTOMUL_1048576
(HSMCI_DTOR) DTOCYC x 1048576
#define HSMCI_CMDR_TRDIR_READ
(HSMCI_CMDR) Read.
#define HSMCI_CMDR_CMDNB(value)
#define HSMCI_MR_RDPROOF
(HSMCI_MR) Read Proof Enable
#define XDMAC_CC_DAM_INCREMENTED_AM
(XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size)...
bool hsmci_start_write_blocks(const void *src, uint16_t nb_block)
Start a write blocks transfer on the line Note: The driver will use the DMA available to speed up the...
#define XDMAC_CC_SIF_AHB_IF1
(XDMAC_CC) The data is read through the system bus interface 1
#define SDMMC_RESP_CRC
Expect valid crc (MCI only)
bool hsmci_wait_end_of_write_blocks(void)
Wait the end of transfer initiated by mci_start_write_blocks()
#define XDMAC_CC_SIF_AHB_IF0
(XDMAC_CC) The data is read through the system bus interface 0
static uint32_t sysclk_get_peripheral_hz(void)
Retrieves the current rate in Hz of the peripheral clocks.
#define HSMCI_SR_RXRDY
(HSMCI_SR) Receiver Ready (cleared by reading HSMCI_RDR)
static void xdmac_channel_enable(Xdmac *xdmac, uint32_t channel_num)
enables the relevant channel of given XDMAC.
#define XDMAC_CC_DIF_AHB_IF0
(XDMAC_CC) The data is written through the system bus interface 0
static void xdmac_channel_disable(Xdmac *xdmac, uint32_t channel_num)
Disables the relevant channel of given XDMAC.
#define SDMMC_CMD_STREAM
To signal a data transfer in stream mode.
static uint16_t hsmci_nb_block
Total number of block requested by last hsmci_adtc_start()
Definition: hsmci.c:115
Board configuration.
bool hsmci_start_read_blocks(void *dest, uint16_t nb_block)
Start a read blocks transfer on the line Note: The driver will use the DMA available to speed up the ...
#define XDMAC_CC_DIF_AHB_IF1
(XDMAC_CC) The data is written though the system bus interface 1
void xdmac_configure_transfer(Xdmac *xdmac, uint32_t channel_num, xdmac_channel_config_t *cfg)
Configure DMA for a transfer.
Definition: xdmac.c:46
#define HSMCI_SR_RTOE
(HSMCI_SR) Response Time-out Error (cleared by writing in HSMCI_CMDR)
#define HSMCI_SR_DCRCE
(HSMCI_SR) Data CRC Error (cleared on read)
#define HSMCI_CMDR_TRTYP_SINGLE
(HSMCI_CMDR) MMC/SD Card Single Block
void hsmci_deselect_device(uint8_t slot)
Deselect a slot.
Definition: hsmci.c:394
#define HSMCI_CSTOR_CSTOMUL_1048576
(HSMCI_CSTOR) CSTOCYC x 1048576
#define HSMCI_DMA_DMAEN
(HSMCI_DMA) DMA Hardware Handshaking Enable
#define HSMCI
(HSMCI ) Base Address
Definition: same70n19.h:539
#define XDMAC_CC_CSIZE_CHK_1
(XDMAC_CC) 1 data transferred
bool hsmci_is_high_speed_capable(void)
Return the high speed capability of the driver.
Definition: hsmci.c:344
#define ID_HSMCI
Multimedia Card Interface (HSMCI)
Definition: same70n19.h:447
#define HSMCI_CMDR_SPCMD_STD
(HSMCI_CMDR) Not a special CMD.
#define HSMCI_SR_RDIRE
(HSMCI_SR) Response Direction Error (cleared by writing in HSMCI_CMDR)
uint8_t hsmci_get_bus_width(uint8_t slot)
Return the maximum bus width of a slot.
Definition: hsmci.c:330
#define HSMCI_CR_SWRST
(HSMCI_CR) Software Reset
#define HSMCI_MR_CLKDIV_Msk
(HSMCI_MR) Clock Divider
#define HSMCI_SR_RENDE
(HSMCI_SR) Response End Bit Error (cleared by writing in HSMCI_CMDR)
#define SDMMC_CMD_WRITE
To signal a data write operation.
#define XDMAC_CC_DSYNC_PER2MEM
(XDMAC_CC) Peripheral to Memory transfer
#define HSMCI_CFG_FIFOMODE
(HSMCI_CFG) HSMCI Internal FIFO control mode
#define HSMCI_CMDR_MAXLAT
(HSMCI_CMDR) Max Latency for Command to Response
uint32_t sdmmc_cmd_def_t
Value to define a SD/MMC/SDIO command.
#define HSMCI_CFG_FERRCTRL
(HSMCI_CFG) Flow Error flag reset control mode
#define SDMMC_RESP_PRESENT
Have response (MCI only)
SAM HSMCI driver.
static bool hsmci_send_cmd_execute(uint32_t cmdr, sdmmc_cmd_def_t cmd, uint32_t arg)
Send a command.
Definition: hsmci.c:241
#define SDMMC_CMD_SDIO_BLOCK
To signal a SDIO tranfer in block mode.
#define HSMCI_CR_PWSEN
(HSMCI_CR) Power Save Mode Enable
bool hsmci_adtc_stop(sdmmc_cmd_def_t cmd, uint32_t arg)
Send a command to stop an ADTC command on the selected slot.
Definition: hsmci.c:536
#define XDMAC_CIS_BIS
(XDMAC_CIS) End of Block Interrupt Status Bit
#define hsmci_debug(...)
Definition: hsmci.c:87
#define HSMCI_SR_RINDE
(HSMCI_SR) Response Index Error (cleared by writing in HSMCI_CMDR)
#define HSMCI_MR_PWSDIV_Msk
(HSMCI_MR) Power Saving Divider
static uint16_t hsmci_block_size
Size block requested by last hsmci_adtc_start()
Definition: hsmci.c:113
bool hsmci_write_word(uint32_t value)
Write a word on the line.
Definition: hsmci.c:581
#define SDMMC_CMD_SDIO_BYTE
To signal a SDIO tranfer in multi byte mode.
#define SDMMC_RESP_136
136 bit response (MCI only)
#define XDMAC_CC_SAM_INCREMENTED_AM
(XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size)...
#define SD_MMC_HSMCI_SLOT_0_SIZE
Definition: hsmci.c:73
#define HSMCI_CMDR_TRDIR_WRITE
(HSMCI_CMDR) Write.
#define HSMCI_SR_TXRDY
(HSMCI_SR) Transmit Ready (cleared by writing in HSMCI_TDR)
#define HSMCI_CMDR_RSPTYP_48_BIT
(HSMCI_CMDR) 48-bit response
Autogenerated API include file for the Atmel Software Framework (ASF)
#define HSMCI_CMDR_RSPTYP_R1B
(HSMCI_CMDR) R1b response type
#define HSMCI_SR_OVRE
(HSMCI_SR) Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL ...
#define HSMCI_SR_DTIP
(HSMCI_SR) Data Transfer in Progress (cleared at the end of CRC16 calculation)
void hsmci_send_clock(void)
Send 74 clock cycles on the line of selected slot Note: It is required after card plug and before car...
Definition: hsmci.c:400
#define HSMCI_CMDR_TRCMD_STOP_DATA
(HSMCI_CMDR) Stop data transfer
static bool hsmci_wait_busy(void)
Wait the end of busy signal on data line.
Definition: hsmci.c:216
#define HSMCI_MR_FBYTE
(HSMCI_MR) Force Byte Transfer
#define HSMCI_SDCR_SDCSEL_SLOTA
(HSMCI_SDCR) Slot A is selected.
#define XDMAC_CC_MBSIZE_SINGLE
(XDMAC_CC) The memory burst size is set to one.
#define HSMCI_SR_XFRDONE
(HSMCI_SR) Transfer Done flag
#define Assert(expr)
This macro is used to test fatal errors.
Definition: compiler.h:196
bool hsmci_send_cmd(sdmmc_cmd_def_t cmd, uint32_t arg)
Send a command on the selected slot.
Definition: hsmci.c:414
#define XDMAC_CC_DWIDTH_BYTE
(XDMAC_CC) The data size is set to 8 bits
#define SDMMC_CMD_MULTI_BLOCK
To signal a data transfer in multi block mode.
#define HSMCI_CR_MCIEN
(HSMCI_CR) Multi-Media Interface Enable
#define HSMCI_DTOR_DTOCYC(value)


inertial_sense_ros
Author(s):
autogenerated on Sat Sep 19 2020 03:19:04