Classes | |
| struct | Xdmac |
| struct | XdmacChid |
| XdmacChid hardware registers. More... | |
Macros | |
| #define | XDMAC_CBC_BLEN(value) ((XDMAC_CBC_BLEN_Msk & ((value) << XDMAC_CBC_BLEN_Pos))) |
| #define | XDMAC_CBC_BLEN_Msk (0xfffu << XDMAC_CBC_BLEN_Pos) |
| (XDMAC_CBC) Channel x Block Length More... | |
| #define | XDMAC_CBC_BLEN_Pos 0 |
| #define | XDMAC_CC_CSIZE(value) ((XDMAC_CC_CSIZE_Msk & ((value) << XDMAC_CC_CSIZE_Pos))) |
| #define | XDMAC_CC_CSIZE_CHK_1 (0x0u << 8) |
| (XDMAC_CC) 1 data transferred More... | |
| #define | XDMAC_CC_CSIZE_CHK_16 (0x4u << 8) |
| (XDMAC_CC) 16 data transferred More... | |
| #define | XDMAC_CC_CSIZE_CHK_2 (0x1u << 8) |
| (XDMAC_CC) 2 data transferred More... | |
| #define | XDMAC_CC_CSIZE_CHK_4 (0x2u << 8) |
| (XDMAC_CC) 4 data transferred More... | |
| #define | XDMAC_CC_CSIZE_CHK_8 (0x3u << 8) |
| (XDMAC_CC) 8 data transferred More... | |
| #define | XDMAC_CC_CSIZE_Msk (0x7u << XDMAC_CC_CSIZE_Pos) |
| (XDMAC_CC) Channel x Chunk Size More... | |
| #define | XDMAC_CC_CSIZE_Pos 8 |
| #define | XDMAC_CC_DAM(value) ((XDMAC_CC_DAM_Msk & ((value) << XDMAC_CC_DAM_Pos))) |
| #define | XDMAC_CC_DAM_FIXED_AM (0x0u << 18) |
| (XDMAC_CC) The address remains unchanged. More... | |
| #define | XDMAC_CC_DAM_INCREMENTED_AM (0x1u << 18) |
| (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). More... | |
| #define | XDMAC_CC_DAM_Msk (0x3u << XDMAC_CC_DAM_Pos) |
| (XDMAC_CC) Channel x Destination Addressing Mode More... | |
| #define | XDMAC_CC_DAM_Pos 18 |
| #define | XDMAC_CC_DAM_UBS_AM (0x2u << 18) |
| (XDMAC_CC) The microblock stride is added at the microblock boundary. More... | |
| #define | XDMAC_CC_DAM_UBS_DS_AM (0x3u << 18) |
| (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. More... | |
| #define | XDMAC_CC_DIF (0x1u << 14) |
| (XDMAC_CC) Channel x Destination Interface Identifier More... | |
| #define | XDMAC_CC_DIF_AHB_IF0 (0x0u << 14) |
| (XDMAC_CC) The data is written through the system bus interface 0 More... | |
| #define | XDMAC_CC_DIF_AHB_IF1 (0x1u << 14) |
| (XDMAC_CC) The data is written though the system bus interface 1 More... | |
| #define | XDMAC_CC_DSYNC (0x1u << 4) |
| (XDMAC_CC) Channel x Synchronization More... | |
| #define | XDMAC_CC_DSYNC_MEM2PER (0x1u << 4) |
| (XDMAC_CC) Memory to Peripheral transfer More... | |
| #define | XDMAC_CC_DSYNC_PER2MEM (0x0u << 4) |
| (XDMAC_CC) Peripheral to Memory transfer More... | |
| #define | XDMAC_CC_DWIDTH(value) ((XDMAC_CC_DWIDTH_Msk & ((value) << XDMAC_CC_DWIDTH_Pos))) |
| #define | XDMAC_CC_DWIDTH_BYTE (0x0u << 11) |
| (XDMAC_CC) The data size is set to 8 bits More... | |
| #define | XDMAC_CC_DWIDTH_HALFWORD (0x1u << 11) |
| (XDMAC_CC) The data size is set to 16 bits More... | |
| #define | XDMAC_CC_DWIDTH_Msk (0x3u << XDMAC_CC_DWIDTH_Pos) |
| (XDMAC_CC) Channel x Data Width More... | |
| #define | XDMAC_CC_DWIDTH_Pos 11 |
| #define | XDMAC_CC_DWIDTH_WORD (0x2u << 11) |
| (XDMAC_CC) The data size is set to 32 bits More... | |
| #define | XDMAC_CC_INITD (0x1u << 21) |
| (XDMAC_CC) Channel Initialization Terminated (this bit is read-only) More... | |
| #define | XDMAC_CC_INITD_IN_PROGRESS (0x0u << 21) |
| (XDMAC_CC) Channel initialization is in progress. More... | |
| #define | XDMAC_CC_INITD_TERMINATED (0x1u << 21) |
| (XDMAC_CC) Channel initialization is completed. More... | |
| #define | XDMAC_CC_MBSIZE(value) ((XDMAC_CC_MBSIZE_Msk & ((value) << XDMAC_CC_MBSIZE_Pos))) |
| #define | XDMAC_CC_MBSIZE_EIGHT (0x2u << 1) |
| (XDMAC_CC) The memory burst size is set to eight. More... | |
| #define | XDMAC_CC_MBSIZE_FOUR (0x1u << 1) |
| (XDMAC_CC) The memory burst size is set to four. More... | |
| #define | XDMAC_CC_MBSIZE_Msk (0x3u << XDMAC_CC_MBSIZE_Pos) |
| (XDMAC_CC) Channel x Memory Burst Size More... | |
| #define | XDMAC_CC_MBSIZE_Pos 1 |
| #define | XDMAC_CC_MBSIZE_SINGLE (0x0u << 1) |
| (XDMAC_CC) The memory burst size is set to one. More... | |
| #define | XDMAC_CC_MBSIZE_SIXTEEN (0x3u << 1) |
| (XDMAC_CC) The memory burst size is set to sixteen. More... | |
| #define | XDMAC_CC_MEMSET (0x1u << 7) |
| (XDMAC_CC) Channel x Fill Block of memory More... | |
| #define | XDMAC_CC_MEMSET_HW_MODE (0x1u << 7) |
| (XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. More... | |
| #define | XDMAC_CC_MEMSET_NORMAL_MODE (0x0u << 7) |
| (XDMAC_CC) Memset is not activated More... | |
| #define | XDMAC_CC_PERID(value) ((XDMAC_CC_PERID_Msk & ((value) << XDMAC_CC_PERID_Pos))) |
| #define | XDMAC_CC_PERID_Msk (0x7fu << XDMAC_CC_PERID_Pos) |
| (XDMAC_CC) Channel x Peripheral Identifier More... | |
| #define | XDMAC_CC_PERID_Pos 24 |
| #define | XDMAC_CC_PROT (0x1u << 5) |
| (XDMAC_CC) Channel x Protection More... | |
| #define | XDMAC_CC_PROT_SEC (0x0u << 5) |
| (XDMAC_CC) Channel is secured More... | |
| #define | XDMAC_CC_PROT_UNSEC (0x1u << 5) |
| (XDMAC_CC) Channel is unsecured More... | |
| #define | XDMAC_CC_RDIP (0x1u << 22) |
| (XDMAC_CC) Read in Progress (this bit is read-only) More... | |
| #define | XDMAC_CC_RDIP_DONE (0x0u << 22) |
| (XDMAC_CC) No Active read transaction on the bus. More... | |
| #define | XDMAC_CC_RDIP_IN_PROGRESS (0x1u << 22) |
| (XDMAC_CC) A read transaction is in progress. More... | |
| #define | XDMAC_CC_SAM(value) ((XDMAC_CC_SAM_Msk & ((value) << XDMAC_CC_SAM_Pos))) |
| #define | XDMAC_CC_SAM_FIXED_AM (0x0u << 16) |
| (XDMAC_CC) The address remains unchanged. More... | |
| #define | XDMAC_CC_SAM_INCREMENTED_AM (0x1u << 16) |
| (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). More... | |
| #define | XDMAC_CC_SAM_Msk (0x3u << XDMAC_CC_SAM_Pos) |
| (XDMAC_CC) Channel x Source Addressing Mode More... | |
| #define | XDMAC_CC_SAM_Pos 16 |
| #define | XDMAC_CC_SAM_UBS_AM (0x2u << 16) |
| (XDMAC_CC) The microblock stride is added at the microblock boundary. More... | |
| #define | XDMAC_CC_SAM_UBS_DS_AM (0x3u << 16) |
| (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. More... | |
| #define | XDMAC_CC_SIF (0x1u << 13) |
| (XDMAC_CC) Channel x Source Interface Identifier More... | |
| #define | XDMAC_CC_SIF_AHB_IF0 (0x0u << 13) |
| (XDMAC_CC) The data is read through the system bus interface 0 More... | |
| #define | XDMAC_CC_SIF_AHB_IF1 (0x1u << 13) |
| (XDMAC_CC) The data is read through the system bus interface 1 More... | |
| #define | XDMAC_CC_SWREQ (0x1u << 6) |
| (XDMAC_CC) Channel x Software Request Trigger More... | |
| #define | XDMAC_CC_SWREQ_HWR_CONNECTED (0x0u << 6) |
| (XDMAC_CC) Hardware request line is connected to the peripheral request line. More... | |
| #define | XDMAC_CC_SWREQ_SWR_CONNECTED (0x1u << 6) |
| (XDMAC_CC) Software request is connected to the peripheral request line. More... | |
| #define | XDMAC_CC_TYPE (0x1u << 0) |
| (XDMAC_CC) Channel x Transfer Type More... | |
| #define | XDMAC_CC_TYPE_MEM_TRAN (0x0u << 0) |
| (XDMAC_CC) Self triggered mode (Memory to Memory Transfer). More... | |
| #define | XDMAC_CC_TYPE_PER_TRAN (0x1u << 0) |
| (XDMAC_CC) Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). More... | |
| #define | XDMAC_CC_WRIP (0x1u << 23) |
| (XDMAC_CC) Write in Progress (this bit is read-only) More... | |
| #define | XDMAC_CC_WRIP_DONE (0x0u << 23) |
| (XDMAC_CC) No Active write transaction on the bus. More... | |
| #define | XDMAC_CC_WRIP_IN_PROGRESS (0x1u << 23) |
| (XDMAC_CC) A Write transaction is in progress. More... | |
| #define | XDMAC_CDA_DA(value) ((XDMAC_CDA_DA_Msk & ((value) << XDMAC_CDA_DA_Pos))) |
| #define | XDMAC_CDA_DA_Msk (0xffffffffu << XDMAC_CDA_DA_Pos) |
| (XDMAC_CDA) Channel x Destination Address More... | |
| #define | XDMAC_CDA_DA_Pos 0 |
| #define | XDMAC_CDS_MSP_DDS_MSP(value) ((XDMAC_CDS_MSP_DDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_DDS_MSP_Pos))) |
| #define | XDMAC_CDS_MSP_DDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_DDS_MSP_Pos) |
| (XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern More... | |
| #define | XDMAC_CDS_MSP_DDS_MSP_Pos 16 |
| #define | XDMAC_CDS_MSP_SDS_MSP(value) ((XDMAC_CDS_MSP_SDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_SDS_MSP_Pos))) |
| #define | XDMAC_CDS_MSP_SDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_SDS_MSP_Pos) |
| (XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern More... | |
| #define | XDMAC_CDS_MSP_SDS_MSP_Pos 0 |
| #define | XDMAC_CDUS_DUBS(value) ((XDMAC_CDUS_DUBS_Msk & ((value) << XDMAC_CDUS_DUBS_Pos))) |
| #define | XDMAC_CDUS_DUBS_Msk (0xffffffu << XDMAC_CDUS_DUBS_Pos) |
| (XDMAC_CDUS) Channel x Destination Microblock Stride More... | |
| #define | XDMAC_CDUS_DUBS_Pos 0 |
| #define | XDMAC_CID_BID (0x1u << 0) |
| (XDMAC_CID) End of Block Interrupt Disable Bit More... | |
| #define | XDMAC_CID_DID (0x1u << 2) |
| (XDMAC_CID) End of Disable Interrupt Disable Bit More... | |
| #define | XDMAC_CID_FID (0x1u << 3) |
| (XDMAC_CID) End of Flush Interrupt Disable Bit More... | |
| #define | XDMAC_CID_LID (0x1u << 1) |
| (XDMAC_CID) End of Linked List Interrupt Disable Bit More... | |
| #define | XDMAC_CID_RBEID (0x1u << 4) |
| (XDMAC_CID) Read Bus Error Interrupt Disable Bit More... | |
| #define | XDMAC_CID_ROID (0x1u << 6) |
| (XDMAC_CID) Request Overflow Error Interrupt Disable Bit More... | |
| #define | XDMAC_CID_WBEID (0x1u << 5) |
| (XDMAC_CID) Write Bus Error Interrupt Disable Bit More... | |
| #define | XDMAC_CIE_BIE (0x1u << 0) |
| (XDMAC_CIE) End of Block Interrupt Enable Bit More... | |
| #define | XDMAC_CIE_DIE (0x1u << 2) |
| (XDMAC_CIE) End of Disable Interrupt Enable Bit More... | |
| #define | XDMAC_CIE_FIE (0x1u << 3) |
| (XDMAC_CIE) End of Flush Interrupt Enable Bit More... | |
| #define | XDMAC_CIE_LIE (0x1u << 1) |
| (XDMAC_CIE) End of Linked List Interrupt Enable Bit More... | |
| #define | XDMAC_CIE_RBIE (0x1u << 4) |
| (XDMAC_CIE) Read Bus Error Interrupt Enable Bit More... | |
| #define | XDMAC_CIE_ROIE (0x1u << 6) |
| (XDMAC_CIE) Request Overflow Error Interrupt Enable Bit More... | |
| #define | XDMAC_CIE_WBIE (0x1u << 5) |
| (XDMAC_CIE) Write Bus Error Interrupt Enable Bit More... | |
| #define | XDMAC_CIM_BIM (0x1u << 0) |
| (XDMAC_CIM) End of Block Interrupt Mask Bit More... | |
| #define | XDMAC_CIM_DIM (0x1u << 2) |
| (XDMAC_CIM) End of Disable Interrupt Mask Bit More... | |
| #define | XDMAC_CIM_FIM (0x1u << 3) |
| (XDMAC_CIM) End of Flush Interrupt Mask Bit More... | |
| #define | XDMAC_CIM_LIM (0x1u << 1) |
| (XDMAC_CIM) End of Linked List Interrupt Mask Bit More... | |
| #define | XDMAC_CIM_RBEIM (0x1u << 4) |
| (XDMAC_CIM) Read Bus Error Interrupt Mask Bit More... | |
| #define | XDMAC_CIM_ROIM (0x1u << 6) |
| (XDMAC_CIM) Request Overflow Error Interrupt Mask Bit More... | |
| #define | XDMAC_CIM_WBEIM (0x1u << 5) |
| (XDMAC_CIM) Write Bus Error Interrupt Mask Bit More... | |
| #define | XDMAC_CIS_BIS (0x1u << 0) |
| (XDMAC_CIS) End of Block Interrupt Status Bit More... | |
| #define | XDMAC_CIS_DIS (0x1u << 2) |
| (XDMAC_CIS) End of Disable Interrupt Status Bit More... | |
| #define | XDMAC_CIS_FIS (0x1u << 3) |
| (XDMAC_CIS) End of Flush Interrupt Status Bit More... | |
| #define | XDMAC_CIS_LIS (0x1u << 1) |
| (XDMAC_CIS) End of Linked List Interrupt Status Bit More... | |
| #define | XDMAC_CIS_RBEIS (0x1u << 4) |
| (XDMAC_CIS) Read Bus Error Interrupt Status Bit More... | |
| #define | XDMAC_CIS_ROIS (0x1u << 6) |
| (XDMAC_CIS) Request Overflow Error Interrupt Status Bit More... | |
| #define | XDMAC_CIS_WBEIS (0x1u << 5) |
| (XDMAC_CIS) Write Bus Error Interrupt Status Bit More... | |
| #define | XDMAC_CNDA_NDA(value) (XDMAC_CNDA_NDA_Msk & (value)) |
| #define | XDMAC_CNDA_NDA_Msk (0x3fffffffu << XDMAC_CNDA_NDA_Pos) |
| (XDMAC_CNDA) Channel x Next Descriptor Address More... | |
| #define | XDMAC_CNDA_NDA_Pos 2 |
| #define | XDMAC_CNDA_NDAIF (0x1u << 0) |
| (XDMAC_CNDA) Channel x Next Descriptor Interface More... | |
| #define | XDMAC_CNDC_NDDUP (0x1u << 2) |
| (XDMAC_CNDC) Channel x Next Descriptor Destination Update More... | |
| #define | XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED (0x0u << 2) |
| (XDMAC_CNDC) Destination parameters remain unchanged. More... | |
| #define | XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED (0x1u << 2) |
| (XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved. More... | |
| #define | XDMAC_CNDC_NDE (0x1u << 0) |
| (XDMAC_CNDC) Channel x Next Descriptor Enable More... | |
| #define | XDMAC_CNDC_NDE_DSCR_FETCH_DIS (0x0u << 0) |
| (XDMAC_CNDC) Descriptor fetch is disabled More... | |
| #define | XDMAC_CNDC_NDE_DSCR_FETCH_EN (0x1u << 0) |
| (XDMAC_CNDC) Descriptor fetch is enabled More... | |
| #define | XDMAC_CNDC_NDSUP (0x1u << 1) |
| (XDMAC_CNDC) Channel x Next Descriptor Source Update More... | |
| #define | XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED (0x0u << 1) |
| (XDMAC_CNDC) Source parameters remain unchanged. More... | |
| #define | XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED (0x1u << 1) |
| (XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved. More... | |
| #define | XDMAC_CNDC_NDVIEW(value) ((XDMAC_CNDC_NDVIEW_Msk & ((value) << XDMAC_CNDC_NDVIEW_Pos))) |
| #define | XDMAC_CNDC_NDVIEW_Msk (0x3u << XDMAC_CNDC_NDVIEW_Pos) |
| (XDMAC_CNDC) Channel x Next Descriptor View More... | |
| #define | XDMAC_CNDC_NDVIEW_NDV0 (0x0u << 3) |
| (XDMAC_CNDC) Next Descriptor View 0 More... | |
| #define | XDMAC_CNDC_NDVIEW_NDV1 (0x1u << 3) |
| (XDMAC_CNDC) Next Descriptor View 1 More... | |
| #define | XDMAC_CNDC_NDVIEW_NDV2 (0x2u << 3) |
| (XDMAC_CNDC) Next Descriptor View 2 More... | |
| #define | XDMAC_CNDC_NDVIEW_NDV3 (0x3u << 3) |
| (XDMAC_CNDC) Next Descriptor View 3 More... | |
| #define | XDMAC_CNDC_NDVIEW_Pos 3 |
| #define | XDMAC_CSA_SA(value) ((XDMAC_CSA_SA_Msk & ((value) << XDMAC_CSA_SA_Pos))) |
| #define | XDMAC_CSA_SA_Msk (0xffffffffu << XDMAC_CSA_SA_Pos) |
| (XDMAC_CSA) Channel x Source Address More... | |
| #define | XDMAC_CSA_SA_Pos 0 |
| #define | XDMAC_CSUS_SUBS(value) ((XDMAC_CSUS_SUBS_Msk & ((value) << XDMAC_CSUS_SUBS_Pos))) |
| #define | XDMAC_CSUS_SUBS_Msk (0xffffffu << XDMAC_CSUS_SUBS_Pos) |
| (XDMAC_CSUS) Channel x Source Microblock Stride More... | |
| #define | XDMAC_CSUS_SUBS_Pos 0 |
| #define | XDMAC_CUBC_UBLEN(value) ((XDMAC_CUBC_UBLEN_Msk & ((value) << XDMAC_CUBC_UBLEN_Pos))) |
| #define | XDMAC_CUBC_UBLEN_Msk (0xffffffu << XDMAC_CUBC_UBLEN_Pos) |
| (XDMAC_CUBC) Channel x Microblock Length More... | |
| #define | XDMAC_CUBC_UBLEN_Pos 0 |
| #define | XDMAC_GCFG_BXKBEN (0x1u << 8) |
| (XDMAC_GCFG) Boundary X Kilo byte Enable More... | |
| #define | XDMAC_GCFG_CGDISFIFO (0x1u << 2) |
| (XDMAC_GCFG) FIFO Clock Gating Disable More... | |
| #define | XDMAC_GCFG_CGDISIF (0x1u << 3) |
| (XDMAC_GCFG) Bus Interface Clock Gating Disable More... | |
| #define | XDMAC_GCFG_CGDISPIPE (0x1u << 1) |
| (XDMAC_GCFG) Pipeline Clock Gating Disable More... | |
| #define | XDMAC_GCFG_CGDISREG (0x1u << 0) |
| (XDMAC_GCFG) Configuration Registers Clock Gating Disable More... | |
| #define | XDMAC_GD_DI0 (0x1u << 0) |
| (XDMAC_GD) XDMAC Channel 0 Disable Bit More... | |
| #define | XDMAC_GD_DI1 (0x1u << 1) |
| (XDMAC_GD) XDMAC Channel 1 Disable Bit More... | |
| #define | XDMAC_GD_DI10 (0x1u << 10) |
| (XDMAC_GD) XDMAC Channel 10 Disable Bit More... | |
| #define | XDMAC_GD_DI11 (0x1u << 11) |
| (XDMAC_GD) XDMAC Channel 11 Disable Bit More... | |
| #define | XDMAC_GD_DI12 (0x1u << 12) |
| (XDMAC_GD) XDMAC Channel 12 Disable Bit More... | |
| #define | XDMAC_GD_DI13 (0x1u << 13) |
| (XDMAC_GD) XDMAC Channel 13 Disable Bit More... | |
| #define | XDMAC_GD_DI14 (0x1u << 14) |
| (XDMAC_GD) XDMAC Channel 14 Disable Bit More... | |
| #define | XDMAC_GD_DI15 (0x1u << 15) |
| (XDMAC_GD) XDMAC Channel 15 Disable Bit More... | |
| #define | XDMAC_GD_DI16 (0x1u << 16) |
| (XDMAC_GD) XDMAC Channel 16 Disable Bit More... | |
| #define | XDMAC_GD_DI17 (0x1u << 17) |
| (XDMAC_GD) XDMAC Channel 17 Disable Bit More... | |
| #define | XDMAC_GD_DI18 (0x1u << 18) |
| (XDMAC_GD) XDMAC Channel 18 Disable Bit More... | |
| #define | XDMAC_GD_DI19 (0x1u << 19) |
| (XDMAC_GD) XDMAC Channel 19 Disable Bit More... | |
| #define | XDMAC_GD_DI2 (0x1u << 2) |
| (XDMAC_GD) XDMAC Channel 2 Disable Bit More... | |
| #define | XDMAC_GD_DI20 (0x1u << 20) |
| (XDMAC_GD) XDMAC Channel 20 Disable Bit More... | |
| #define | XDMAC_GD_DI21 (0x1u << 21) |
| (XDMAC_GD) XDMAC Channel 21 Disable Bit More... | |
| #define | XDMAC_GD_DI22 (0x1u << 22) |
| (XDMAC_GD) XDMAC Channel 22 Disable Bit More... | |
| #define | XDMAC_GD_DI23 (0x1u << 23) |
| (XDMAC_GD) XDMAC Channel 23 Disable Bit More... | |
| #define | XDMAC_GD_DI3 (0x1u << 3) |
| (XDMAC_GD) XDMAC Channel 3 Disable Bit More... | |
| #define | XDMAC_GD_DI4 (0x1u << 4) |
| (XDMAC_GD) XDMAC Channel 4 Disable Bit More... | |
| #define | XDMAC_GD_DI5 (0x1u << 5) |
| (XDMAC_GD) XDMAC Channel 5 Disable Bit More... | |
| #define | XDMAC_GD_DI6 (0x1u << 6) |
| (XDMAC_GD) XDMAC Channel 6 Disable Bit More... | |
| #define | XDMAC_GD_DI7 (0x1u << 7) |
| (XDMAC_GD) XDMAC Channel 7 Disable Bit More... | |
| #define | XDMAC_GD_DI8 (0x1u << 8) |
| (XDMAC_GD) XDMAC Channel 8 Disable Bit More... | |
| #define | XDMAC_GD_DI9 (0x1u << 9) |
| (XDMAC_GD) XDMAC Channel 9 Disable Bit More... | |
| #define | XDMAC_GE_EN0 (0x1u << 0) |
| (XDMAC_GE) XDMAC Channel 0 Enable Bit More... | |
| #define | XDMAC_GE_EN1 (0x1u << 1) |
| (XDMAC_GE) XDMAC Channel 1 Enable Bit More... | |
| #define | XDMAC_GE_EN10 (0x1u << 10) |
| (XDMAC_GE) XDMAC Channel 10 Enable Bit More... | |
| #define | XDMAC_GE_EN11 (0x1u << 11) |
| (XDMAC_GE) XDMAC Channel 11 Enable Bit More... | |
| #define | XDMAC_GE_EN12 (0x1u << 12) |
| (XDMAC_GE) XDMAC Channel 12 Enable Bit More... | |
| #define | XDMAC_GE_EN13 (0x1u << 13) |
| (XDMAC_GE) XDMAC Channel 13 Enable Bit More... | |
| #define | XDMAC_GE_EN14 (0x1u << 14) |
| (XDMAC_GE) XDMAC Channel 14 Enable Bit More... | |
| #define | XDMAC_GE_EN15 (0x1u << 15) |
| (XDMAC_GE) XDMAC Channel 15 Enable Bit More... | |
| #define | XDMAC_GE_EN16 (0x1u << 16) |
| (XDMAC_GE) XDMAC Channel 16 Enable Bit More... | |
| #define | XDMAC_GE_EN17 (0x1u << 17) |
| (XDMAC_GE) XDMAC Channel 17 Enable Bit More... | |
| #define | XDMAC_GE_EN18 (0x1u << 18) |
| (XDMAC_GE) XDMAC Channel 18 Enable Bit More... | |
| #define | XDMAC_GE_EN19 (0x1u << 19) |
| (XDMAC_GE) XDMAC Channel 19 Enable Bit More... | |
| #define | XDMAC_GE_EN2 (0x1u << 2) |
| (XDMAC_GE) XDMAC Channel 2 Enable Bit More... | |
| #define | XDMAC_GE_EN20 (0x1u << 20) |
| (XDMAC_GE) XDMAC Channel 20 Enable Bit More... | |
| #define | XDMAC_GE_EN21 (0x1u << 21) |
| (XDMAC_GE) XDMAC Channel 21 Enable Bit More... | |
| #define | XDMAC_GE_EN22 (0x1u << 22) |
| (XDMAC_GE) XDMAC Channel 22 Enable Bit More... | |
| #define | XDMAC_GE_EN23 (0x1u << 23) |
| (XDMAC_GE) XDMAC Channel 23 Enable Bit More... | |
| #define | XDMAC_GE_EN3 (0x1u << 3) |
| (XDMAC_GE) XDMAC Channel 3 Enable Bit More... | |
| #define | XDMAC_GE_EN4 (0x1u << 4) |
| (XDMAC_GE) XDMAC Channel 4 Enable Bit More... | |
| #define | XDMAC_GE_EN5 (0x1u << 5) |
| (XDMAC_GE) XDMAC Channel 5 Enable Bit More... | |
| #define | XDMAC_GE_EN6 (0x1u << 6) |
| (XDMAC_GE) XDMAC Channel 6 Enable Bit More... | |
| #define | XDMAC_GE_EN7 (0x1u << 7) |
| (XDMAC_GE) XDMAC Channel 7 Enable Bit More... | |
| #define | XDMAC_GE_EN8 (0x1u << 8) |
| (XDMAC_GE) XDMAC Channel 8 Enable Bit More... | |
| #define | XDMAC_GE_EN9 (0x1u << 9) |
| (XDMAC_GE) XDMAC Channel 9 Enable Bit More... | |
| #define | XDMAC_GID_ID0 (0x1u << 0) |
| (XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit More... | |
| #define | XDMAC_GID_ID1 (0x1u << 1) |
| (XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit More... | |
| #define | XDMAC_GID_ID10 (0x1u << 10) |
| (XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit More... | |
| #define | XDMAC_GID_ID11 (0x1u << 11) |
| (XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit More... | |
| #define | XDMAC_GID_ID12 (0x1u << 12) |
| (XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit More... | |
| #define | XDMAC_GID_ID13 (0x1u << 13) |
| (XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit More... | |
| #define | XDMAC_GID_ID14 (0x1u << 14) |
| (XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit More... | |
| #define | XDMAC_GID_ID15 (0x1u << 15) |
| (XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit More... | |
| #define | XDMAC_GID_ID16 (0x1u << 16) |
| (XDMAC_GID) XDMAC Channel 16 Interrupt Disable Bit More... | |
| #define | XDMAC_GID_ID17 (0x1u << 17) |
| (XDMAC_GID) XDMAC Channel 17 Interrupt Disable Bit More... | |
| #define | XDMAC_GID_ID18 (0x1u << 18) |
| (XDMAC_GID) XDMAC Channel 18 Interrupt Disable Bit More... | |
| #define | XDMAC_GID_ID19 (0x1u << 19) |
| (XDMAC_GID) XDMAC Channel 19 Interrupt Disable Bit More... | |
| #define | XDMAC_GID_ID2 (0x1u << 2) |
| (XDMAC_GID) XDMAC Channel 2 Interrupt Disable Bit More... | |
| #define | XDMAC_GID_ID20 (0x1u << 20) |
| (XDMAC_GID) XDMAC Channel 20 Interrupt Disable Bit More... | |
| #define | XDMAC_GID_ID21 (0x1u << 21) |
| (XDMAC_GID) XDMAC Channel 21 Interrupt Disable Bit More... | |
| #define | XDMAC_GID_ID22 (0x1u << 22) |
| (XDMAC_GID) XDMAC Channel 22 Interrupt Disable Bit More... | |
| #define | XDMAC_GID_ID23 (0x1u << 23) |
| (XDMAC_GID) XDMAC Channel 23 Interrupt Disable Bit More... | |
| #define | XDMAC_GID_ID3 (0x1u << 3) |
| (XDMAC_GID) XDMAC Channel 3 Interrupt Disable Bit More... | |
| #define | XDMAC_GID_ID4 (0x1u << 4) |
| (XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit More... | |
| #define | XDMAC_GID_ID5 (0x1u << 5) |
| (XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit More... | |
| #define | XDMAC_GID_ID6 (0x1u << 6) |
| (XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit More... | |
| #define | XDMAC_GID_ID7 (0x1u << 7) |
| (XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit More... | |
| #define | XDMAC_GID_ID8 (0x1u << 8) |
| (XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit More... | |
| #define | XDMAC_GID_ID9 (0x1u << 9) |
| (XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit More... | |
| #define | XDMAC_GIE_IE0 (0x1u << 0) |
| (XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit More... | |
| #define | XDMAC_GIE_IE1 (0x1u << 1) |
| (XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit More... | |
| #define | XDMAC_GIE_IE10 (0x1u << 10) |
| (XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit More... | |
| #define | XDMAC_GIE_IE11 (0x1u << 11) |
| (XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit More... | |
| #define | XDMAC_GIE_IE12 (0x1u << 12) |
| (XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit More... | |
| #define | XDMAC_GIE_IE13 (0x1u << 13) |
| (XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit More... | |
| #define | XDMAC_GIE_IE14 (0x1u << 14) |
| (XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit More... | |
| #define | XDMAC_GIE_IE15 (0x1u << 15) |
| (XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit More... | |
| #define | XDMAC_GIE_IE16 (0x1u << 16) |
| (XDMAC_GIE) XDMAC Channel 16 Interrupt Enable Bit More... | |
| #define | XDMAC_GIE_IE17 (0x1u << 17) |
| (XDMAC_GIE) XDMAC Channel 17 Interrupt Enable Bit More... | |
| #define | XDMAC_GIE_IE18 (0x1u << 18) |
| (XDMAC_GIE) XDMAC Channel 18 Interrupt Enable Bit More... | |
| #define | XDMAC_GIE_IE19 (0x1u << 19) |
| (XDMAC_GIE) XDMAC Channel 19 Interrupt Enable Bit More... | |
| #define | XDMAC_GIE_IE2 (0x1u << 2) |
| (XDMAC_GIE) XDMAC Channel 2 Interrupt Enable Bit More... | |
| #define | XDMAC_GIE_IE20 (0x1u << 20) |
| (XDMAC_GIE) XDMAC Channel 20 Interrupt Enable Bit More... | |
| #define | XDMAC_GIE_IE21 (0x1u << 21) |
| (XDMAC_GIE) XDMAC Channel 21 Interrupt Enable Bit More... | |
| #define | XDMAC_GIE_IE22 (0x1u << 22) |
| (XDMAC_GIE) XDMAC Channel 22 Interrupt Enable Bit More... | |
| #define | XDMAC_GIE_IE23 (0x1u << 23) |
| (XDMAC_GIE) XDMAC Channel 23 Interrupt Enable Bit More... | |
| #define | XDMAC_GIE_IE3 (0x1u << 3) |
| (XDMAC_GIE) XDMAC Channel 3 Interrupt Enable Bit More... | |
| #define | XDMAC_GIE_IE4 (0x1u << 4) |
| (XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit More... | |
| #define | XDMAC_GIE_IE5 (0x1u << 5) |
| (XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit More... | |
| #define | XDMAC_GIE_IE6 (0x1u << 6) |
| (XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit More... | |
| #define | XDMAC_GIE_IE7 (0x1u << 7) |
| (XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit More... | |
| #define | XDMAC_GIE_IE8 (0x1u << 8) |
| (XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit More... | |
| #define | XDMAC_GIE_IE9 (0x1u << 9) |
| (XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit More... | |
| #define | XDMAC_GIM_IM0 (0x1u << 0) |
| (XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit More... | |
| #define | XDMAC_GIM_IM1 (0x1u << 1) |
| (XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit More... | |
| #define | XDMAC_GIM_IM10 (0x1u << 10) |
| (XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit More... | |
| #define | XDMAC_GIM_IM11 (0x1u << 11) |
| (XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit More... | |
| #define | XDMAC_GIM_IM12 (0x1u << 12) |
| (XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit More... | |
| #define | XDMAC_GIM_IM13 (0x1u << 13) |
| (XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit More... | |
| #define | XDMAC_GIM_IM14 (0x1u << 14) |
| (XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit More... | |
| #define | XDMAC_GIM_IM15 (0x1u << 15) |
| (XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit More... | |
| #define | XDMAC_GIM_IM16 (0x1u << 16) |
| (XDMAC_GIM) XDMAC Channel 16 Interrupt Mask Bit More... | |
| #define | XDMAC_GIM_IM17 (0x1u << 17) |
| (XDMAC_GIM) XDMAC Channel 17 Interrupt Mask Bit More... | |
| #define | XDMAC_GIM_IM18 (0x1u << 18) |
| (XDMAC_GIM) XDMAC Channel 18 Interrupt Mask Bit More... | |
| #define | XDMAC_GIM_IM19 (0x1u << 19) |
| (XDMAC_GIM) XDMAC Channel 19 Interrupt Mask Bit More... | |
| #define | XDMAC_GIM_IM2 (0x1u << 2) |
| (XDMAC_GIM) XDMAC Channel 2 Interrupt Mask Bit More... | |
| #define | XDMAC_GIM_IM20 (0x1u << 20) |
| (XDMAC_GIM) XDMAC Channel 20 Interrupt Mask Bit More... | |
| #define | XDMAC_GIM_IM21 (0x1u << 21) |
| (XDMAC_GIM) XDMAC Channel 21 Interrupt Mask Bit More... | |
| #define | XDMAC_GIM_IM22 (0x1u << 22) |
| (XDMAC_GIM) XDMAC Channel 22 Interrupt Mask Bit More... | |
| #define | XDMAC_GIM_IM23 (0x1u << 23) |
| (XDMAC_GIM) XDMAC Channel 23 Interrupt Mask Bit More... | |
| #define | XDMAC_GIM_IM3 (0x1u << 3) |
| (XDMAC_GIM) XDMAC Channel 3 Interrupt Mask Bit More... | |
| #define | XDMAC_GIM_IM4 (0x1u << 4) |
| (XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit More... | |
| #define | XDMAC_GIM_IM5 (0x1u << 5) |
| (XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit More... | |
| #define | XDMAC_GIM_IM6 (0x1u << 6) |
| (XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit More... | |
| #define | XDMAC_GIM_IM7 (0x1u << 7) |
| (XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit More... | |
| #define | XDMAC_GIM_IM8 (0x1u << 8) |
| (XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit More... | |
| #define | XDMAC_GIM_IM9 (0x1u << 9) |
| (XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit More... | |
| #define | XDMAC_GIS_IS0 (0x1u << 0) |
| (XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit More... | |
| #define | XDMAC_GIS_IS1 (0x1u << 1) |
| (XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit More... | |
| #define | XDMAC_GIS_IS10 (0x1u << 10) |
| (XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit More... | |
| #define | XDMAC_GIS_IS11 (0x1u << 11) |
| (XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit More... | |
| #define | XDMAC_GIS_IS12 (0x1u << 12) |
| (XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit More... | |
| #define | XDMAC_GIS_IS13 (0x1u << 13) |
| (XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit More... | |
| #define | XDMAC_GIS_IS14 (0x1u << 14) |
| (XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit More... | |
| #define | XDMAC_GIS_IS15 (0x1u << 15) |
| (XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit More... | |
| #define | XDMAC_GIS_IS16 (0x1u << 16) |
| (XDMAC_GIS) XDMAC Channel 16 Interrupt Status Bit More... | |
| #define | XDMAC_GIS_IS17 (0x1u << 17) |
| (XDMAC_GIS) XDMAC Channel 17 Interrupt Status Bit More... | |
| #define | XDMAC_GIS_IS18 (0x1u << 18) |
| (XDMAC_GIS) XDMAC Channel 18 Interrupt Status Bit More... | |
| #define | XDMAC_GIS_IS19 (0x1u << 19) |
| (XDMAC_GIS) XDMAC Channel 19 Interrupt Status Bit More... | |
| #define | XDMAC_GIS_IS2 (0x1u << 2) |
| (XDMAC_GIS) XDMAC Channel 2 Interrupt Status Bit More... | |
| #define | XDMAC_GIS_IS20 (0x1u << 20) |
| (XDMAC_GIS) XDMAC Channel 20 Interrupt Status Bit More... | |
| #define | XDMAC_GIS_IS21 (0x1u << 21) |
| (XDMAC_GIS) XDMAC Channel 21 Interrupt Status Bit More... | |
| #define | XDMAC_GIS_IS22 (0x1u << 22) |
| (XDMAC_GIS) XDMAC Channel 22 Interrupt Status Bit More... | |
| #define | XDMAC_GIS_IS23 (0x1u << 23) |
| (XDMAC_GIS) XDMAC Channel 23 Interrupt Status Bit More... | |
| #define | XDMAC_GIS_IS3 (0x1u << 3) |
| (XDMAC_GIS) XDMAC Channel 3 Interrupt Status Bit More... | |
| #define | XDMAC_GIS_IS4 (0x1u << 4) |
| (XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit More... | |
| #define | XDMAC_GIS_IS5 (0x1u << 5) |
| (XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit More... | |
| #define | XDMAC_GIS_IS6 (0x1u << 6) |
| (XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit More... | |
| #define | XDMAC_GIS_IS7 (0x1u << 7) |
| (XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit More... | |
| #define | XDMAC_GIS_IS8 (0x1u << 8) |
| (XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit More... | |
| #define | XDMAC_GIS_IS9 (0x1u << 9) |
| (XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit More... | |
| #define | XDMAC_GRS_RS0 (0x1u << 0) |
| (XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit More... | |
| #define | XDMAC_GRS_RS1 (0x1u << 1) |
| (XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit More... | |
| #define | XDMAC_GRS_RS10 (0x1u << 10) |
| (XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit More... | |
| #define | XDMAC_GRS_RS11 (0x1u << 11) |
| (XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit More... | |
| #define | XDMAC_GRS_RS12 (0x1u << 12) |
| (XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit More... | |
| #define | XDMAC_GRS_RS13 (0x1u << 13) |
| (XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit More... | |
| #define | XDMAC_GRS_RS14 (0x1u << 14) |
| (XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit More... | |
| #define | XDMAC_GRS_RS15 (0x1u << 15) |
| (XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit More... | |
| #define | XDMAC_GRS_RS16 (0x1u << 16) |
| (XDMAC_GRS) XDMAC Channel 16 Read Suspend Bit More... | |
| #define | XDMAC_GRS_RS17 (0x1u << 17) |
| (XDMAC_GRS) XDMAC Channel 17 Read Suspend Bit More... | |
| #define | XDMAC_GRS_RS18 (0x1u << 18) |
| (XDMAC_GRS) XDMAC Channel 18 Read Suspend Bit More... | |
| #define | XDMAC_GRS_RS19 (0x1u << 19) |
| (XDMAC_GRS) XDMAC Channel 19 Read Suspend Bit More... | |
| #define | XDMAC_GRS_RS2 (0x1u << 2) |
| (XDMAC_GRS) XDMAC Channel 2 Read Suspend Bit More... | |
| #define | XDMAC_GRS_RS20 (0x1u << 20) |
| (XDMAC_GRS) XDMAC Channel 20 Read Suspend Bit More... | |
| #define | XDMAC_GRS_RS21 (0x1u << 21) |
| (XDMAC_GRS) XDMAC Channel 21 Read Suspend Bit More... | |
| #define | XDMAC_GRS_RS22 (0x1u << 22) |
| (XDMAC_GRS) XDMAC Channel 22 Read Suspend Bit More... | |
| #define | XDMAC_GRS_RS23 (0x1u << 23) |
| (XDMAC_GRS) XDMAC Channel 23 Read Suspend Bit More... | |
| #define | XDMAC_GRS_RS3 (0x1u << 3) |
| (XDMAC_GRS) XDMAC Channel 3 Read Suspend Bit More... | |
| #define | XDMAC_GRS_RS4 (0x1u << 4) |
| (XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit More... | |
| #define | XDMAC_GRS_RS5 (0x1u << 5) |
| (XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit More... | |
| #define | XDMAC_GRS_RS6 (0x1u << 6) |
| (XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit More... | |
| #define | XDMAC_GRS_RS7 (0x1u << 7) |
| (XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit More... | |
| #define | XDMAC_GRS_RS8 (0x1u << 8) |
| (XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit More... | |
| #define | XDMAC_GRS_RS9 (0x1u << 9) |
| (XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit More... | |
| #define | XDMAC_GRWR_RWR0 (0x1u << 0) |
| (XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit More... | |
| #define | XDMAC_GRWR_RWR1 (0x1u << 1) |
| (XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit More... | |
| #define | XDMAC_GRWR_RWR10 (0x1u << 10) |
| (XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit More... | |
| #define | XDMAC_GRWR_RWR11 (0x1u << 11) |
| (XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit More... | |
| #define | XDMAC_GRWR_RWR12 (0x1u << 12) |
| (XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit More... | |
| #define | XDMAC_GRWR_RWR13 (0x1u << 13) |
| (XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit More... | |
| #define | XDMAC_GRWR_RWR14 (0x1u << 14) |
| (XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit More... | |
| #define | XDMAC_GRWR_RWR15 (0x1u << 15) |
| (XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit More... | |
| #define | XDMAC_GRWR_RWR16 (0x1u << 16) |
| (XDMAC_GRWR) XDMAC Channel 16 Read Write Resume Bit More... | |
| #define | XDMAC_GRWR_RWR17 (0x1u << 17) |
| (XDMAC_GRWR) XDMAC Channel 17 Read Write Resume Bit More... | |
| #define | XDMAC_GRWR_RWR18 (0x1u << 18) |
| (XDMAC_GRWR) XDMAC Channel 18 Read Write Resume Bit More... | |
| #define | XDMAC_GRWR_RWR19 (0x1u << 19) |
| (XDMAC_GRWR) XDMAC Channel 19 Read Write Resume Bit More... | |
| #define | XDMAC_GRWR_RWR2 (0x1u << 2) |
| (XDMAC_GRWR) XDMAC Channel 2 Read Write Resume Bit More... | |
| #define | XDMAC_GRWR_RWR20 (0x1u << 20) |
| (XDMAC_GRWR) XDMAC Channel 20 Read Write Resume Bit More... | |
| #define | XDMAC_GRWR_RWR21 (0x1u << 21) |
| (XDMAC_GRWR) XDMAC Channel 21 Read Write Resume Bit More... | |
| #define | XDMAC_GRWR_RWR22 (0x1u << 22) |
| (XDMAC_GRWR) XDMAC Channel 22 Read Write Resume Bit More... | |
| #define | XDMAC_GRWR_RWR23 (0x1u << 23) |
| (XDMAC_GRWR) XDMAC Channel 23 Read Write Resume Bit More... | |
| #define | XDMAC_GRWR_RWR3 (0x1u << 3) |
| (XDMAC_GRWR) XDMAC Channel 3 Read Write Resume Bit More... | |
| #define | XDMAC_GRWR_RWR4 (0x1u << 4) |
| (XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit More... | |
| #define | XDMAC_GRWR_RWR5 (0x1u << 5) |
| (XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit More... | |
| #define | XDMAC_GRWR_RWR6 (0x1u << 6) |
| (XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit More... | |
| #define | XDMAC_GRWR_RWR7 (0x1u << 7) |
| (XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit More... | |
| #define | XDMAC_GRWR_RWR8 (0x1u << 8) |
| (XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit More... | |
| #define | XDMAC_GRWR_RWR9 (0x1u << 9) |
| (XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit More... | |
| #define | XDMAC_GRWS_RWS0 (0x1u << 0) |
| (XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit More... | |
| #define | XDMAC_GRWS_RWS1 (0x1u << 1) |
| (XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit More... | |
| #define | XDMAC_GRWS_RWS10 (0x1u << 10) |
| (XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit More... | |
| #define | XDMAC_GRWS_RWS11 (0x1u << 11) |
| (XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit More... | |
| #define | XDMAC_GRWS_RWS12 (0x1u << 12) |
| (XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit More... | |
| #define | XDMAC_GRWS_RWS13 (0x1u << 13) |
| (XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit More... | |
| #define | XDMAC_GRWS_RWS14 (0x1u << 14) |
| (XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit More... | |
| #define | XDMAC_GRWS_RWS15 (0x1u << 15) |
| (XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit More... | |
| #define | XDMAC_GRWS_RWS16 (0x1u << 16) |
| (XDMAC_GRWS) XDMAC Channel 16 Read Write Suspend Bit More... | |
| #define | XDMAC_GRWS_RWS17 (0x1u << 17) |
| (XDMAC_GRWS) XDMAC Channel 17 Read Write Suspend Bit More... | |
| #define | XDMAC_GRWS_RWS18 (0x1u << 18) |
| (XDMAC_GRWS) XDMAC Channel 18 Read Write Suspend Bit More... | |
| #define | XDMAC_GRWS_RWS19 (0x1u << 19) |
| (XDMAC_GRWS) XDMAC Channel 19 Read Write Suspend Bit More... | |
| #define | XDMAC_GRWS_RWS2 (0x1u << 2) |
| (XDMAC_GRWS) XDMAC Channel 2 Read Write Suspend Bit More... | |
| #define | XDMAC_GRWS_RWS20 (0x1u << 20) |
| (XDMAC_GRWS) XDMAC Channel 20 Read Write Suspend Bit More... | |
| #define | XDMAC_GRWS_RWS21 (0x1u << 21) |
| (XDMAC_GRWS) XDMAC Channel 21 Read Write Suspend Bit More... | |
| #define | XDMAC_GRWS_RWS22 (0x1u << 22) |
| (XDMAC_GRWS) XDMAC Channel 22 Read Write Suspend Bit More... | |
| #define | XDMAC_GRWS_RWS23 (0x1u << 23) |
| (XDMAC_GRWS) XDMAC Channel 23 Read Write Suspend Bit More... | |
| #define | XDMAC_GRWS_RWS3 (0x1u << 3) |
| (XDMAC_GRWS) XDMAC Channel 3 Read Write Suspend Bit More... | |
| #define | XDMAC_GRWS_RWS4 (0x1u << 4) |
| (XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit More... | |
| #define | XDMAC_GRWS_RWS5 (0x1u << 5) |
| (XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit More... | |
| #define | XDMAC_GRWS_RWS6 (0x1u << 6) |
| (XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit More... | |
| #define | XDMAC_GRWS_RWS7 (0x1u << 7) |
| (XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit More... | |
| #define | XDMAC_GRWS_RWS8 (0x1u << 8) |
| (XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit More... | |
| #define | XDMAC_GRWS_RWS9 (0x1u << 9) |
| (XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit More... | |
| #define | XDMAC_GS_ST0 (0x1u << 0) |
| (XDMAC_GS) XDMAC Channel 0 Status Bit More... | |
| #define | XDMAC_GS_ST1 (0x1u << 1) |
| (XDMAC_GS) XDMAC Channel 1 Status Bit More... | |
| #define | XDMAC_GS_ST10 (0x1u << 10) |
| (XDMAC_GS) XDMAC Channel 10 Status Bit More... | |
| #define | XDMAC_GS_ST11 (0x1u << 11) |
| (XDMAC_GS) XDMAC Channel 11 Status Bit More... | |
| #define | XDMAC_GS_ST12 (0x1u << 12) |
| (XDMAC_GS) XDMAC Channel 12 Status Bit More... | |
| #define | XDMAC_GS_ST13 (0x1u << 13) |
| (XDMAC_GS) XDMAC Channel 13 Status Bit More... | |
| #define | XDMAC_GS_ST14 (0x1u << 14) |
| (XDMAC_GS) XDMAC Channel 14 Status Bit More... | |
| #define | XDMAC_GS_ST15 (0x1u << 15) |
| (XDMAC_GS) XDMAC Channel 15 Status Bit More... | |
| #define | XDMAC_GS_ST16 (0x1u << 16) |
| (XDMAC_GS) XDMAC Channel 16 Status Bit More... | |
| #define | XDMAC_GS_ST17 (0x1u << 17) |
| (XDMAC_GS) XDMAC Channel 17 Status Bit More... | |
| #define | XDMAC_GS_ST18 (0x1u << 18) |
| (XDMAC_GS) XDMAC Channel 18 Status Bit More... | |
| #define | XDMAC_GS_ST19 (0x1u << 19) |
| (XDMAC_GS) XDMAC Channel 19 Status Bit More... | |
| #define | XDMAC_GS_ST2 (0x1u << 2) |
| (XDMAC_GS) XDMAC Channel 2 Status Bit More... | |
| #define | XDMAC_GS_ST20 (0x1u << 20) |
| (XDMAC_GS) XDMAC Channel 20 Status Bit More... | |
| #define | XDMAC_GS_ST21 (0x1u << 21) |
| (XDMAC_GS) XDMAC Channel 21 Status Bit More... | |
| #define | XDMAC_GS_ST22 (0x1u << 22) |
| (XDMAC_GS) XDMAC Channel 22 Status Bit More... | |
| #define | XDMAC_GS_ST23 (0x1u << 23) |
| (XDMAC_GS) XDMAC Channel 23 Status Bit More... | |
| #define | XDMAC_GS_ST3 (0x1u << 3) |
| (XDMAC_GS) XDMAC Channel 3 Status Bit More... | |
| #define | XDMAC_GS_ST4 (0x1u << 4) |
| (XDMAC_GS) XDMAC Channel 4 Status Bit More... | |
| #define | XDMAC_GS_ST5 (0x1u << 5) |
| (XDMAC_GS) XDMAC Channel 5 Status Bit More... | |
| #define | XDMAC_GS_ST6 (0x1u << 6) |
| (XDMAC_GS) XDMAC Channel 6 Status Bit More... | |
| #define | XDMAC_GS_ST7 (0x1u << 7) |
| (XDMAC_GS) XDMAC Channel 7 Status Bit More... | |
| #define | XDMAC_GS_ST8 (0x1u << 8) |
| (XDMAC_GS) XDMAC Channel 8 Status Bit More... | |
| #define | XDMAC_GS_ST9 (0x1u << 9) |
| (XDMAC_GS) XDMAC Channel 9 Status Bit More... | |
| #define | XDMAC_GSWF_SWF0 (0x1u << 0) |
| (XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit More... | |
| #define | XDMAC_GSWF_SWF1 (0x1u << 1) |
| (XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit More... | |
| #define | XDMAC_GSWF_SWF10 (0x1u << 10) |
| (XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit More... | |
| #define | XDMAC_GSWF_SWF11 (0x1u << 11) |
| (XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit More... | |
| #define | XDMAC_GSWF_SWF12 (0x1u << 12) |
| (XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit More... | |
| #define | XDMAC_GSWF_SWF13 (0x1u << 13) |
| (XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit More... | |
| #define | XDMAC_GSWF_SWF14 (0x1u << 14) |
| (XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit More... | |
| #define | XDMAC_GSWF_SWF15 (0x1u << 15) |
| (XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit More... | |
| #define | XDMAC_GSWF_SWF16 (0x1u << 16) |
| (XDMAC_GSWF) XDMAC Channel 16 Software Flush Request Bit More... | |
| #define | XDMAC_GSWF_SWF17 (0x1u << 17) |
| (XDMAC_GSWF) XDMAC Channel 17 Software Flush Request Bit More... | |
| #define | XDMAC_GSWF_SWF18 (0x1u << 18) |
| (XDMAC_GSWF) XDMAC Channel 18 Software Flush Request Bit More... | |
| #define | XDMAC_GSWF_SWF19 (0x1u << 19) |
| (XDMAC_GSWF) XDMAC Channel 19 Software Flush Request Bit More... | |
| #define | XDMAC_GSWF_SWF2 (0x1u << 2) |
| (XDMAC_GSWF) XDMAC Channel 2 Software Flush Request Bit More... | |
| #define | XDMAC_GSWF_SWF20 (0x1u << 20) |
| (XDMAC_GSWF) XDMAC Channel 20 Software Flush Request Bit More... | |
| #define | XDMAC_GSWF_SWF21 (0x1u << 21) |
| (XDMAC_GSWF) XDMAC Channel 21 Software Flush Request Bit More... | |
| #define | XDMAC_GSWF_SWF22 (0x1u << 22) |
| (XDMAC_GSWF) XDMAC Channel 22 Software Flush Request Bit More... | |
| #define | XDMAC_GSWF_SWF23 (0x1u << 23) |
| (XDMAC_GSWF) XDMAC Channel 23 Software Flush Request Bit More... | |
| #define | XDMAC_GSWF_SWF3 (0x1u << 3) |
| (XDMAC_GSWF) XDMAC Channel 3 Software Flush Request Bit More... | |
| #define | XDMAC_GSWF_SWF4 (0x1u << 4) |
| (XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit More... | |
| #define | XDMAC_GSWF_SWF5 (0x1u << 5) |
| (XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit More... | |
| #define | XDMAC_GSWF_SWF6 (0x1u << 6) |
| (XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit More... | |
| #define | XDMAC_GSWF_SWF7 (0x1u << 7) |
| (XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit More... | |
| #define | XDMAC_GSWF_SWF8 (0x1u << 8) |
| (XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit More... | |
| #define | XDMAC_GSWF_SWF9 (0x1u << 9) |
| (XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit More... | |
| #define | XDMAC_GSWR_SWREQ0 (0x1u << 0) |
| (XDMAC_GSWR) XDMAC Channel 0 Software Request Bit More... | |
| #define | XDMAC_GSWR_SWREQ1 (0x1u << 1) |
| (XDMAC_GSWR) XDMAC Channel 1 Software Request Bit More... | |
| #define | XDMAC_GSWR_SWREQ10 (0x1u << 10) |
| (XDMAC_GSWR) XDMAC Channel 10 Software Request Bit More... | |
| #define | XDMAC_GSWR_SWREQ11 (0x1u << 11) |
| (XDMAC_GSWR) XDMAC Channel 11 Software Request Bit More... | |
| #define | XDMAC_GSWR_SWREQ12 (0x1u << 12) |
| (XDMAC_GSWR) XDMAC Channel 12 Software Request Bit More... | |
| #define | XDMAC_GSWR_SWREQ13 (0x1u << 13) |
| (XDMAC_GSWR) XDMAC Channel 13 Software Request Bit More... | |
| #define | XDMAC_GSWR_SWREQ14 (0x1u << 14) |
| (XDMAC_GSWR) XDMAC Channel 14 Software Request Bit More... | |
| #define | XDMAC_GSWR_SWREQ15 (0x1u << 15) |
| (XDMAC_GSWR) XDMAC Channel 15 Software Request Bit More... | |
| #define | XDMAC_GSWR_SWREQ16 (0x1u << 16) |
| (XDMAC_GSWR) XDMAC Channel 16 Software Request Bit More... | |
| #define | XDMAC_GSWR_SWREQ17 (0x1u << 17) |
| (XDMAC_GSWR) XDMAC Channel 17 Software Request Bit More... | |
| #define | XDMAC_GSWR_SWREQ18 (0x1u << 18) |
| (XDMAC_GSWR) XDMAC Channel 18 Software Request Bit More... | |
| #define | XDMAC_GSWR_SWREQ19 (0x1u << 19) |
| (XDMAC_GSWR) XDMAC Channel 19 Software Request Bit More... | |
| #define | XDMAC_GSWR_SWREQ2 (0x1u << 2) |
| (XDMAC_GSWR) XDMAC Channel 2 Software Request Bit More... | |
| #define | XDMAC_GSWR_SWREQ20 (0x1u << 20) |
| (XDMAC_GSWR) XDMAC Channel 20 Software Request Bit More... | |
| #define | XDMAC_GSWR_SWREQ21 (0x1u << 21) |
| (XDMAC_GSWR) XDMAC Channel 21 Software Request Bit More... | |
| #define | XDMAC_GSWR_SWREQ22 (0x1u << 22) |
| (XDMAC_GSWR) XDMAC Channel 22 Software Request Bit More... | |
| #define | XDMAC_GSWR_SWREQ23 (0x1u << 23) |
| (XDMAC_GSWR) XDMAC Channel 23 Software Request Bit More... | |
| #define | XDMAC_GSWR_SWREQ3 (0x1u << 3) |
| (XDMAC_GSWR) XDMAC Channel 3 Software Request Bit More... | |
| #define | XDMAC_GSWR_SWREQ4 (0x1u << 4) |
| (XDMAC_GSWR) XDMAC Channel 4 Software Request Bit More... | |
| #define | XDMAC_GSWR_SWREQ5 (0x1u << 5) |
| (XDMAC_GSWR) XDMAC Channel 5 Software Request Bit More... | |
| #define | XDMAC_GSWR_SWREQ6 (0x1u << 6) |
| (XDMAC_GSWR) XDMAC Channel 6 Software Request Bit More... | |
| #define | XDMAC_GSWR_SWREQ7 (0x1u << 7) |
| (XDMAC_GSWR) XDMAC Channel 7 Software Request Bit More... | |
| #define | XDMAC_GSWR_SWREQ8 (0x1u << 8) |
| (XDMAC_GSWR) XDMAC Channel 8 Software Request Bit More... | |
| #define | XDMAC_GSWR_SWREQ9 (0x1u << 9) |
| (XDMAC_GSWR) XDMAC Channel 9 Software Request Bit More... | |
| #define | XDMAC_GSWS_SWRS0 (0x1u << 0) |
| (XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit More... | |
| #define | XDMAC_GSWS_SWRS1 (0x1u << 1) |
| (XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit More... | |
| #define | XDMAC_GSWS_SWRS10 (0x1u << 10) |
| (XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit More... | |
| #define | XDMAC_GSWS_SWRS11 (0x1u << 11) |
| (XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit More... | |
| #define | XDMAC_GSWS_SWRS12 (0x1u << 12) |
| (XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit More... | |
| #define | XDMAC_GSWS_SWRS13 (0x1u << 13) |
| (XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit More... | |
| #define | XDMAC_GSWS_SWRS14 (0x1u << 14) |
| (XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit More... | |
| #define | XDMAC_GSWS_SWRS15 (0x1u << 15) |
| (XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit More... | |
| #define | XDMAC_GSWS_SWRS16 (0x1u << 16) |
| (XDMAC_GSWS) XDMAC Channel 16 Software Request Status Bit More... | |
| #define | XDMAC_GSWS_SWRS17 (0x1u << 17) |
| (XDMAC_GSWS) XDMAC Channel 17 Software Request Status Bit More... | |
| #define | XDMAC_GSWS_SWRS18 (0x1u << 18) |
| (XDMAC_GSWS) XDMAC Channel 18 Software Request Status Bit More... | |
| #define | XDMAC_GSWS_SWRS19 (0x1u << 19) |
| (XDMAC_GSWS) XDMAC Channel 19 Software Request Status Bit More... | |
| #define | XDMAC_GSWS_SWRS2 (0x1u << 2) |
| (XDMAC_GSWS) XDMAC Channel 2 Software Request Status Bit More... | |
| #define | XDMAC_GSWS_SWRS20 (0x1u << 20) |
| (XDMAC_GSWS) XDMAC Channel 20 Software Request Status Bit More... | |
| #define | XDMAC_GSWS_SWRS21 (0x1u << 21) |
| (XDMAC_GSWS) XDMAC Channel 21 Software Request Status Bit More... | |
| #define | XDMAC_GSWS_SWRS22 (0x1u << 22) |
| (XDMAC_GSWS) XDMAC Channel 22 Software Request Status Bit More... | |
| #define | XDMAC_GSWS_SWRS23 (0x1u << 23) |
| (XDMAC_GSWS) XDMAC Channel 23 Software Request Status Bit More... | |
| #define | XDMAC_GSWS_SWRS3 (0x1u << 3) |
| (XDMAC_GSWS) XDMAC Channel 3 Software Request Status Bit More... | |
| #define | XDMAC_GSWS_SWRS4 (0x1u << 4) |
| (XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit More... | |
| #define | XDMAC_GSWS_SWRS5 (0x1u << 5) |
| (XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit More... | |
| #define | XDMAC_GSWS_SWRS6 (0x1u << 6) |
| (XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit More... | |
| #define | XDMAC_GSWS_SWRS7 (0x1u << 7) |
| (XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit More... | |
| #define | XDMAC_GSWS_SWRS8 (0x1u << 8) |
| (XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit More... | |
| #define | XDMAC_GSWS_SWRS9 (0x1u << 9) |
| (XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit More... | |
| #define | XDMAC_GTYPE_FIFO_SZ(value) ((XDMAC_GTYPE_FIFO_SZ_Msk & ((value) << XDMAC_GTYPE_FIFO_SZ_Pos))) |
| #define | XDMAC_GTYPE_FIFO_SZ_Msk (0x7ffu << XDMAC_GTYPE_FIFO_SZ_Pos) |
| (XDMAC_GTYPE) Number of Bytes More... | |
| #define | XDMAC_GTYPE_FIFO_SZ_Pos 5 |
| #define | XDMAC_GTYPE_NB_CH(value) ((XDMAC_GTYPE_NB_CH_Msk & ((value) << XDMAC_GTYPE_NB_CH_Pos))) |
| #define | XDMAC_GTYPE_NB_CH_Msk (0x1fu << XDMAC_GTYPE_NB_CH_Pos) |
| (XDMAC_GTYPE) Number of Channels Minus One More... | |
| #define | XDMAC_GTYPE_NB_CH_Pos 0 |
| #define | XDMAC_GTYPE_NB_REQ(value) ((XDMAC_GTYPE_NB_REQ_Msk & ((value) << XDMAC_GTYPE_NB_REQ_Pos))) |
| #define | XDMAC_GTYPE_NB_REQ_Msk (0x7fu << XDMAC_GTYPE_NB_REQ_Pos) |
| (XDMAC_GTYPE) Number of Peripheral Requests Minus One More... | |
| #define | XDMAC_GTYPE_NB_REQ_Pos 16 |
| #define | XDMAC_GWAC_PW0(value) ((XDMAC_GWAC_PW0_Msk & ((value) << XDMAC_GWAC_PW0_Pos))) |
| #define | XDMAC_GWAC_PW0_Msk (0xfu << XDMAC_GWAC_PW0_Pos) |
| (XDMAC_GWAC) Pool Weight 0 More... | |
| #define | XDMAC_GWAC_PW0_Pos 0 |
| #define | XDMAC_GWAC_PW1(value) ((XDMAC_GWAC_PW1_Msk & ((value) << XDMAC_GWAC_PW1_Pos))) |
| #define | XDMAC_GWAC_PW1_Msk (0xfu << XDMAC_GWAC_PW1_Pos) |
| (XDMAC_GWAC) Pool Weight 1 More... | |
| #define | XDMAC_GWAC_PW1_Pos 4 |
| #define | XDMAC_GWAC_PW2(value) ((XDMAC_GWAC_PW2_Msk & ((value) << XDMAC_GWAC_PW2_Pos))) |
| #define | XDMAC_GWAC_PW2_Msk (0xfu << XDMAC_GWAC_PW2_Pos) |
| (XDMAC_GWAC) Pool Weight 2 More... | |
| #define | XDMAC_GWAC_PW2_Pos 8 |
| #define | XDMAC_GWAC_PW3(value) ((XDMAC_GWAC_PW3_Msk & ((value) << XDMAC_GWAC_PW3_Pos))) |
| #define | XDMAC_GWAC_PW3_Msk (0xfu << XDMAC_GWAC_PW3_Pos) |
| (XDMAC_GWAC) Pool Weight 3 More... | |
| #define | XDMAC_GWAC_PW3_Pos 12 |
| #define | XDMAC_GWS_WS0 (0x1u << 0) |
| (XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit More... | |
| #define | XDMAC_GWS_WS1 (0x1u << 1) |
| (XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit More... | |
| #define | XDMAC_GWS_WS10 (0x1u << 10) |
| (XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit More... | |
| #define | XDMAC_GWS_WS11 (0x1u << 11) |
| (XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit More... | |
| #define | XDMAC_GWS_WS12 (0x1u << 12) |
| (XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit More... | |
| #define | XDMAC_GWS_WS13 (0x1u << 13) |
| (XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit More... | |
| #define | XDMAC_GWS_WS14 (0x1u << 14) |
| (XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit More... | |
| #define | XDMAC_GWS_WS15 (0x1u << 15) |
| (XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit More... | |
| #define | XDMAC_GWS_WS16 (0x1u << 16) |
| (XDMAC_GWS) XDMAC Channel 16 Write Suspend Bit More... | |
| #define | XDMAC_GWS_WS17 (0x1u << 17) |
| (XDMAC_GWS) XDMAC Channel 17 Write Suspend Bit More... | |
| #define | XDMAC_GWS_WS18 (0x1u << 18) |
| (XDMAC_GWS) XDMAC Channel 18 Write Suspend Bit More... | |
| #define | XDMAC_GWS_WS19 (0x1u << 19) |
| (XDMAC_GWS) XDMAC Channel 19 Write Suspend Bit More... | |
| #define | XDMAC_GWS_WS2 (0x1u << 2) |
| (XDMAC_GWS) XDMAC Channel 2 Write Suspend Bit More... | |
| #define | XDMAC_GWS_WS20 (0x1u << 20) |
| (XDMAC_GWS) XDMAC Channel 20 Write Suspend Bit More... | |
| #define | XDMAC_GWS_WS21 (0x1u << 21) |
| (XDMAC_GWS) XDMAC Channel 21 Write Suspend Bit More... | |
| #define | XDMAC_GWS_WS22 (0x1u << 22) |
| (XDMAC_GWS) XDMAC Channel 22 Write Suspend Bit More... | |
| #define | XDMAC_GWS_WS23 (0x1u << 23) |
| (XDMAC_GWS) XDMAC Channel 23 Write Suspend Bit More... | |
| #define | XDMAC_GWS_WS3 (0x1u << 3) |
| (XDMAC_GWS) XDMAC Channel 3 Write Suspend Bit More... | |
| #define | XDMAC_GWS_WS4 (0x1u << 4) |
| (XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit More... | |
| #define | XDMAC_GWS_WS5 (0x1u << 5) |
| (XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit More... | |
| #define | XDMAC_GWS_WS6 (0x1u << 6) |
| (XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit More... | |
| #define | XDMAC_GWS_WS7 (0x1u << 7) |
| (XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit More... | |
| #define | XDMAC_GWS_WS8 (0x1u << 8) |
| (XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit More... | |
| #define | XDMAC_GWS_WS9 (0x1u << 9) |
| (XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit More... | |
| #define | XDMAC_VERSION_MFN(value) ((XDMAC_VERSION_MFN_Msk & ((value) << XDMAC_VERSION_MFN_Pos))) |
| #define | XDMAC_VERSION_MFN_Msk (0x7u << XDMAC_VERSION_MFN_Pos) |
| (XDMAC_VERSION) Metal Fix Number More... | |
| #define | XDMAC_VERSION_MFN_Pos 16 |
| #define | XDMAC_VERSION_VERSION(value) ((XDMAC_VERSION_VERSION_Msk & ((value) << XDMAC_VERSION_VERSION_Pos))) |
| #define | XDMAC_VERSION_VERSION_Msk (0xfffu << XDMAC_VERSION_VERSION_Pos) |
| (XDMAC_VERSION) Version of the Hardware Module More... | |
| #define | XDMAC_VERSION_VERSION_Pos 0 |
| #define | XDMACCHID_NUMBER 24 |
| Xdmac hardware registers. More... | |
SOFTWARE API DEFINITION FOR Extensible DMA Controller
| #define XDMAC_CBC_BLEN | ( | value | ) | ((XDMAC_CBC_BLEN_Msk & ((value) << XDMAC_CBC_BLEN_Pos))) |
Definition at line 537 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CBC_BLEN_Msk (0xfffu << XDMAC_CBC_BLEN_Pos) |
(XDMAC_CBC) Channel x Block Length
Definition at line 536 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CBC_BLEN_Pos 0 |
Definition at line 535 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_CSIZE | ( | value | ) | ((XDMAC_CC_CSIZE_Msk & ((value) << XDMAC_CC_CSIZE_Pos))) |
Definition at line 563 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_CSIZE_CHK_1 (0x0u << 8) |
(XDMAC_CC) 1 data transferred
Definition at line 564 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_CSIZE_CHK_16 (0x4u << 8) |
(XDMAC_CC) 16 data transferred
Definition at line 568 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_CSIZE_CHK_2 (0x1u << 8) |
(XDMAC_CC) 2 data transferred
Definition at line 565 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_CSIZE_CHK_4 (0x2u << 8) |
(XDMAC_CC) 4 data transferred
Definition at line 566 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_CSIZE_CHK_8 (0x3u << 8) |
(XDMAC_CC) 8 data transferred
Definition at line 567 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_CSIZE_Msk (0x7u << XDMAC_CC_CSIZE_Pos) |
(XDMAC_CC) Channel x Chunk Size
Definition at line 562 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_CSIZE_Pos 8 |
Definition at line 561 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_DAM | ( | value | ) | ((XDMAC_CC_DAM_Msk & ((value) << XDMAC_CC_DAM_Pos))) |
Definition at line 590 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_DAM_FIXED_AM (0x0u << 18) |
(XDMAC_CC) The address remains unchanged.
Definition at line 591 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_DAM_INCREMENTED_AM (0x1u << 18) |
(XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size).
Definition at line 592 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_DAM_Msk (0x3u << XDMAC_CC_DAM_Pos) |
(XDMAC_CC) Channel x Destination Addressing Mode
Definition at line 589 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_DAM_Pos 18 |
Definition at line 588 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_DAM_UBS_AM (0x2u << 18) |
(XDMAC_CC) The microblock stride is added at the microblock boundary.
Definition at line 593 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_DAM_UBS_DS_AM (0x3u << 18) |
(XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.
Definition at line 594 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_DIF (0x1u << 14) |
(XDMAC_CC) Channel x Destination Interface Identifier
Definition at line 578 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_DIF_AHB_IF0 (0x0u << 14) |
(XDMAC_CC) The data is written through the system bus interface 0
Definition at line 579 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_DIF_AHB_IF1 (0x1u << 14) |
(XDMAC_CC) The data is written though the system bus interface 1
Definition at line 580 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_DSYNC (0x1u << 4) |
(XDMAC_CC) Channel x Synchronization
Definition at line 549 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_DSYNC_MEM2PER (0x1u << 4) |
(XDMAC_CC) Memory to Peripheral transfer
Definition at line 551 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_DSYNC_PER2MEM (0x0u << 4) |
(XDMAC_CC) Peripheral to Memory transfer
Definition at line 550 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_DWIDTH | ( | value | ) | ((XDMAC_CC_DWIDTH_Msk & ((value) << XDMAC_CC_DWIDTH_Pos))) |
Definition at line 571 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_DWIDTH_BYTE (0x0u << 11) |
(XDMAC_CC) The data size is set to 8 bits
Definition at line 572 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_DWIDTH_HALFWORD (0x1u << 11) |
(XDMAC_CC) The data size is set to 16 bits
Definition at line 573 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_DWIDTH_Msk (0x3u << XDMAC_CC_DWIDTH_Pos) |
(XDMAC_CC) Channel x Data Width
Definition at line 570 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_DWIDTH_Pos 11 |
Definition at line 569 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_DWIDTH_WORD (0x2u << 11) |
(XDMAC_CC) The data size is set to 32 bits
Definition at line 574 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_INITD (0x1u << 21) |
(XDMAC_CC) Channel Initialization Terminated (this bit is read-only)
Definition at line 595 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_INITD_IN_PROGRESS (0x0u << 21) |
(XDMAC_CC) Channel initialization is in progress.
Definition at line 596 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_INITD_TERMINATED (0x1u << 21) |
(XDMAC_CC) Channel initialization is completed.
Definition at line 597 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_MBSIZE | ( | value | ) | ((XDMAC_CC_MBSIZE_Msk & ((value) << XDMAC_CC_MBSIZE_Pos))) |
Definition at line 544 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_MBSIZE_EIGHT (0x2u << 1) |
(XDMAC_CC) The memory burst size is set to eight.
Definition at line 547 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_MBSIZE_FOUR (0x1u << 1) |
(XDMAC_CC) The memory burst size is set to four.
Definition at line 546 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_MBSIZE_Msk (0x3u << XDMAC_CC_MBSIZE_Pos) |
(XDMAC_CC) Channel x Memory Burst Size
Definition at line 543 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_MBSIZE_Pos 1 |
Definition at line 542 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_MBSIZE_SINGLE (0x0u << 1) |
(XDMAC_CC) The memory burst size is set to one.
Definition at line 545 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_MBSIZE_SIXTEEN (0x3u << 1) |
(XDMAC_CC) The memory burst size is set to sixteen.
Definition at line 548 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_MEMSET (0x1u << 7) |
(XDMAC_CC) Channel x Fill Block of memory
Definition at line 558 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_MEMSET_HW_MODE (0x1u << 7) |
(XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis.
Definition at line 560 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_MEMSET_NORMAL_MODE (0x0u << 7) |
(XDMAC_CC) Memset is not activated
Definition at line 559 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_PERID | ( | value | ) | ((XDMAC_CC_PERID_Msk & ((value) << XDMAC_CC_PERID_Pos))) |
Definition at line 606 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_PERID_Msk (0x7fu << XDMAC_CC_PERID_Pos) |
(XDMAC_CC) Channel x Peripheral Identifier
Definition at line 605 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_PERID_Pos 24 |
Definition at line 604 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_PROT (0x1u << 5) |
(XDMAC_CC) Channel x Protection
Definition at line 552 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_PROT_SEC (0x0u << 5) |
(XDMAC_CC) Channel is secured
Definition at line 553 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_PROT_UNSEC (0x1u << 5) |
(XDMAC_CC) Channel is unsecured
Definition at line 554 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_RDIP (0x1u << 22) |
(XDMAC_CC) Read in Progress (this bit is read-only)
Definition at line 598 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_RDIP_DONE (0x0u << 22) |
(XDMAC_CC) No Active read transaction on the bus.
Definition at line 599 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_RDIP_IN_PROGRESS (0x1u << 22) |
(XDMAC_CC) A read transaction is in progress.
Definition at line 600 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_SAM | ( | value | ) | ((XDMAC_CC_SAM_Msk & ((value) << XDMAC_CC_SAM_Pos))) |
Definition at line 583 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_SAM_FIXED_AM (0x0u << 16) |
(XDMAC_CC) The address remains unchanged.
Definition at line 584 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_SAM_INCREMENTED_AM (0x1u << 16) |
(XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size).
Definition at line 585 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_SAM_Msk (0x3u << XDMAC_CC_SAM_Pos) |
(XDMAC_CC) Channel x Source Addressing Mode
Definition at line 582 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_SAM_Pos 16 |
Definition at line 581 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_SAM_UBS_AM (0x2u << 16) |
(XDMAC_CC) The microblock stride is added at the microblock boundary.
Definition at line 586 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_SAM_UBS_DS_AM (0x3u << 16) |
(XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.
Definition at line 587 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_SIF (0x1u << 13) |
(XDMAC_CC) Channel x Source Interface Identifier
Definition at line 575 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_SIF_AHB_IF0 (0x0u << 13) |
(XDMAC_CC) The data is read through the system bus interface 0
Definition at line 576 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_SIF_AHB_IF1 (0x1u << 13) |
(XDMAC_CC) The data is read through the system bus interface 1
Definition at line 577 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_SWREQ (0x1u << 6) |
(XDMAC_CC) Channel x Software Request Trigger
Definition at line 555 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_SWREQ_HWR_CONNECTED (0x0u << 6) |
(XDMAC_CC) Hardware request line is connected to the peripheral request line.
Definition at line 556 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_SWREQ_SWR_CONNECTED (0x1u << 6) |
(XDMAC_CC) Software request is connected to the peripheral request line.
Definition at line 557 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_TYPE (0x1u << 0) |
(XDMAC_CC) Channel x Transfer Type
Definition at line 539 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_TYPE_MEM_TRAN (0x0u << 0) |
(XDMAC_CC) Self triggered mode (Memory to Memory Transfer).
Definition at line 540 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_TYPE_PER_TRAN (0x1u << 0) |
(XDMAC_CC) Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).
Definition at line 541 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_WRIP (0x1u << 23) |
(XDMAC_CC) Write in Progress (this bit is read-only)
Definition at line 601 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_WRIP_DONE (0x0u << 23) |
(XDMAC_CC) No Active write transaction on the bus.
Definition at line 602 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CC_WRIP_IN_PROGRESS (0x1u << 23) |
(XDMAC_CC) A Write transaction is in progress.
Definition at line 603 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CDA_DA | ( | value | ) | ((XDMAC_CDA_DA_Msk & ((value) << XDMAC_CDA_DA_Pos))) |
Definition at line 507 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CDA_DA_Msk (0xffffffffu << XDMAC_CDA_DA_Pos) |
(XDMAC_CDA) Channel x Destination Address
Definition at line 506 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CDA_DA_Pos 0 |
Definition at line 505 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CDS_MSP_DDS_MSP | ( | value | ) | ((XDMAC_CDS_MSP_DDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_DDS_MSP_Pos))) |
Definition at line 613 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CDS_MSP_DDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_DDS_MSP_Pos) |
(XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern
Definition at line 612 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CDS_MSP_DDS_MSP_Pos 16 |
Definition at line 611 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CDS_MSP_SDS_MSP | ( | value | ) | ((XDMAC_CDS_MSP_SDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_SDS_MSP_Pos))) |
Definition at line 610 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CDS_MSP_SDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_SDS_MSP_Pos) |
(XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern
Definition at line 609 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CDS_MSP_SDS_MSP_Pos 0 |
Definition at line 608 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CDUS_DUBS | ( | value | ) | ((XDMAC_CDUS_DUBS_Msk & ((value) << XDMAC_CDUS_DUBS_Pos))) |
Definition at line 621 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CDUS_DUBS_Msk (0xffffffu << XDMAC_CDUS_DUBS_Pos) |
(XDMAC_CDUS) Channel x Destination Microblock Stride
Definition at line 620 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CDUS_DUBS_Pos 0 |
Definition at line 619 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CID_BID (0x1u << 0) |
(XDMAC_CID) End of Block Interrupt Disable Bit
Definition at line 477 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CID_DID (0x1u << 2) |
(XDMAC_CID) End of Disable Interrupt Disable Bit
Definition at line 479 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CID_FID (0x1u << 3) |
(XDMAC_CID) End of Flush Interrupt Disable Bit
Definition at line 480 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CID_LID (0x1u << 1) |
(XDMAC_CID) End of Linked List Interrupt Disable Bit
Definition at line 478 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CID_RBEID (0x1u << 4) |
(XDMAC_CID) Read Bus Error Interrupt Disable Bit
Definition at line 481 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CID_ROID (0x1u << 6) |
(XDMAC_CID) Request Overflow Error Interrupt Disable Bit
Definition at line 483 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CID_WBEID (0x1u << 5) |
(XDMAC_CID) Write Bus Error Interrupt Disable Bit
Definition at line 482 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CIE_BIE (0x1u << 0) |
(XDMAC_CIE) End of Block Interrupt Enable Bit
Definition at line 469 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CIE_DIE (0x1u << 2) |
(XDMAC_CIE) End of Disable Interrupt Enable Bit
Definition at line 471 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CIE_FIE (0x1u << 3) |
(XDMAC_CIE) End of Flush Interrupt Enable Bit
Definition at line 472 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CIE_LIE (0x1u << 1) |
(XDMAC_CIE) End of Linked List Interrupt Enable Bit
Definition at line 470 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CIE_RBIE (0x1u << 4) |
(XDMAC_CIE) Read Bus Error Interrupt Enable Bit
Definition at line 473 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CIE_ROIE (0x1u << 6) |
(XDMAC_CIE) Request Overflow Error Interrupt Enable Bit
Definition at line 475 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CIE_WBIE (0x1u << 5) |
(XDMAC_CIE) Write Bus Error Interrupt Enable Bit
Definition at line 474 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CIM_BIM (0x1u << 0) |
(XDMAC_CIM) End of Block Interrupt Mask Bit
Definition at line 485 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CIM_DIM (0x1u << 2) |
(XDMAC_CIM) End of Disable Interrupt Mask Bit
Definition at line 487 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CIM_FIM (0x1u << 3) |
(XDMAC_CIM) End of Flush Interrupt Mask Bit
Definition at line 488 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CIM_LIM (0x1u << 1) |
(XDMAC_CIM) End of Linked List Interrupt Mask Bit
Definition at line 486 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CIM_RBEIM (0x1u << 4) |
(XDMAC_CIM) Read Bus Error Interrupt Mask Bit
Definition at line 489 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CIM_ROIM (0x1u << 6) |
(XDMAC_CIM) Request Overflow Error Interrupt Mask Bit
Definition at line 491 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CIM_WBEIM (0x1u << 5) |
(XDMAC_CIM) Write Bus Error Interrupt Mask Bit
Definition at line 490 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CIS_BIS (0x1u << 0) |
(XDMAC_CIS) End of Block Interrupt Status Bit
Definition at line 493 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CIS_DIS (0x1u << 2) |
(XDMAC_CIS) End of Disable Interrupt Status Bit
Definition at line 495 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CIS_FIS (0x1u << 3) |
(XDMAC_CIS) End of Flush Interrupt Status Bit
Definition at line 496 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CIS_LIS (0x1u << 1) |
(XDMAC_CIS) End of Linked List Interrupt Status Bit
Definition at line 494 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CIS_RBEIS (0x1u << 4) |
(XDMAC_CIS) Read Bus Error Interrupt Status Bit
Definition at line 497 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CIS_ROIS (0x1u << 6) |
(XDMAC_CIS) Request Overflow Error Interrupt Status Bit
Definition at line 499 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CIS_WBEIS (0x1u << 5) |
(XDMAC_CIS) Write Bus Error Interrupt Status Bit
Definition at line 498 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CNDA_NDA | ( | value | ) | (XDMAC_CNDA_NDA_Msk & (value)) |
Definition at line 512 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CNDA_NDA_Msk (0x3fffffffu << XDMAC_CNDA_NDA_Pos) |
(XDMAC_CNDA) Channel x Next Descriptor Address
Definition at line 511 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CNDA_NDA_Pos 2 |
Definition at line 510 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CNDA_NDAIF (0x1u << 0) |
(XDMAC_CNDA) Channel x Next Descriptor Interface
Definition at line 509 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CNDC_NDDUP (0x1u << 2) |
(XDMAC_CNDC) Channel x Next Descriptor Destination Update
Definition at line 520 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED (0x0u << 2) |
(XDMAC_CNDC) Destination parameters remain unchanged.
Definition at line 521 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED (0x1u << 2) |
(XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved.
Definition at line 522 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CNDC_NDE (0x1u << 0) |
(XDMAC_CNDC) Channel x Next Descriptor Enable
Definition at line 514 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CNDC_NDE_DSCR_FETCH_DIS (0x0u << 0) |
(XDMAC_CNDC) Descriptor fetch is disabled
Definition at line 515 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CNDC_NDE_DSCR_FETCH_EN (0x1u << 0) |
(XDMAC_CNDC) Descriptor fetch is enabled
Definition at line 516 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CNDC_NDSUP (0x1u << 1) |
(XDMAC_CNDC) Channel x Next Descriptor Source Update
Definition at line 517 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED (0x0u << 1) |
(XDMAC_CNDC) Source parameters remain unchanged.
Definition at line 518 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED (0x1u << 1) |
(XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved.
Definition at line 519 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CNDC_NDVIEW | ( | value | ) | ((XDMAC_CNDC_NDVIEW_Msk & ((value) << XDMAC_CNDC_NDVIEW_Pos))) |
Definition at line 525 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CNDC_NDVIEW_Msk (0x3u << XDMAC_CNDC_NDVIEW_Pos) |
(XDMAC_CNDC) Channel x Next Descriptor View
Definition at line 524 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CNDC_NDVIEW_NDV0 (0x0u << 3) |
(XDMAC_CNDC) Next Descriptor View 0
Definition at line 526 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CNDC_NDVIEW_NDV1 (0x1u << 3) |
(XDMAC_CNDC) Next Descriptor View 1
Definition at line 527 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CNDC_NDVIEW_NDV2 (0x2u << 3) |
(XDMAC_CNDC) Next Descriptor View 2
Definition at line 528 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CNDC_NDVIEW_NDV3 (0x3u << 3) |
(XDMAC_CNDC) Next Descriptor View 3
Definition at line 529 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CNDC_NDVIEW_Pos 3 |
Definition at line 523 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CSA_SA | ( | value | ) | ((XDMAC_CSA_SA_Msk & ((value) << XDMAC_CSA_SA_Pos))) |
Definition at line 503 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CSA_SA_Msk (0xffffffffu << XDMAC_CSA_SA_Pos) |
(XDMAC_CSA) Channel x Source Address
Definition at line 502 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CSA_SA_Pos 0 |
Definition at line 501 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CSUS_SUBS | ( | value | ) | ((XDMAC_CSUS_SUBS_Msk & ((value) << XDMAC_CSUS_SUBS_Pos))) |
Definition at line 617 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CSUS_SUBS_Msk (0xffffffu << XDMAC_CSUS_SUBS_Pos) |
(XDMAC_CSUS) Channel x Source Microblock Stride
Definition at line 616 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CSUS_SUBS_Pos 0 |
Definition at line 615 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CUBC_UBLEN | ( | value | ) | ((XDMAC_CUBC_UBLEN_Msk & ((value) << XDMAC_CUBC_UBLEN_Pos))) |
Definition at line 533 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CUBC_UBLEN_Msk (0xffffffu << XDMAC_CUBC_UBLEN_Pos) |
(XDMAC_CUBC) Channel x Microblock Length
Definition at line 532 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_CUBC_UBLEN_Pos 0 |
Definition at line 531 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GCFG_BXKBEN (0x1u << 8) |
(XDMAC_GCFG) Boundary X Kilo byte Enable
Definition at line 104 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GCFG_CGDISFIFO (0x1u << 2) |
(XDMAC_GCFG) FIFO Clock Gating Disable
Definition at line 102 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GCFG_CGDISIF (0x1u << 3) |
(XDMAC_GCFG) Bus Interface Clock Gating Disable
Definition at line 103 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GCFG_CGDISPIPE (0x1u << 1) |
(XDMAC_GCFG) Pipeline Clock Gating Disable
Definition at line 101 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GCFG_CGDISREG (0x1u << 0) |
(XDMAC_GCFG) Configuration Registers Clock Gating Disable
Definition at line 100 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GD_DI0 (0x1u << 0) |
(XDMAC_GD) XDMAC Channel 0 Disable Bit
Definition at line 244 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GD_DI1 (0x1u << 1) |
(XDMAC_GD) XDMAC Channel 1 Disable Bit
Definition at line 245 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GD_DI10 (0x1u << 10) |
(XDMAC_GD) XDMAC Channel 10 Disable Bit
Definition at line 254 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GD_DI11 (0x1u << 11) |
(XDMAC_GD) XDMAC Channel 11 Disable Bit
Definition at line 255 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GD_DI12 (0x1u << 12) |
(XDMAC_GD) XDMAC Channel 12 Disable Bit
Definition at line 256 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GD_DI13 (0x1u << 13) |
(XDMAC_GD) XDMAC Channel 13 Disable Bit
Definition at line 257 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GD_DI14 (0x1u << 14) |
(XDMAC_GD) XDMAC Channel 14 Disable Bit
Definition at line 258 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GD_DI15 (0x1u << 15) |
(XDMAC_GD) XDMAC Channel 15 Disable Bit
Definition at line 259 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GD_DI16 (0x1u << 16) |
(XDMAC_GD) XDMAC Channel 16 Disable Bit
Definition at line 260 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GD_DI17 (0x1u << 17) |
(XDMAC_GD) XDMAC Channel 17 Disable Bit
Definition at line 261 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GD_DI18 (0x1u << 18) |
(XDMAC_GD) XDMAC Channel 18 Disable Bit
Definition at line 262 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GD_DI19 (0x1u << 19) |
(XDMAC_GD) XDMAC Channel 19 Disable Bit
Definition at line 263 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GD_DI2 (0x1u << 2) |
(XDMAC_GD) XDMAC Channel 2 Disable Bit
Definition at line 246 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GD_DI20 (0x1u << 20) |
(XDMAC_GD) XDMAC Channel 20 Disable Bit
Definition at line 264 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GD_DI21 (0x1u << 21) |
(XDMAC_GD) XDMAC Channel 21 Disable Bit
Definition at line 265 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GD_DI22 (0x1u << 22) |
(XDMAC_GD) XDMAC Channel 22 Disable Bit
Definition at line 266 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GD_DI23 (0x1u << 23) |
(XDMAC_GD) XDMAC Channel 23 Disable Bit
Definition at line 267 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GD_DI3 (0x1u << 3) |
(XDMAC_GD) XDMAC Channel 3 Disable Bit
Definition at line 247 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GD_DI4 (0x1u << 4) |
(XDMAC_GD) XDMAC Channel 4 Disable Bit
Definition at line 248 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GD_DI5 (0x1u << 5) |
(XDMAC_GD) XDMAC Channel 5 Disable Bit
Definition at line 249 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GD_DI6 (0x1u << 6) |
(XDMAC_GD) XDMAC Channel 6 Disable Bit
Definition at line 250 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GD_DI7 (0x1u << 7) |
(XDMAC_GD) XDMAC Channel 7 Disable Bit
Definition at line 251 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GD_DI8 (0x1u << 8) |
(XDMAC_GD) XDMAC Channel 8 Disable Bit
Definition at line 252 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GD_DI9 (0x1u << 9) |
(XDMAC_GD) XDMAC Channel 9 Disable Bit
Definition at line 253 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GE_EN0 (0x1u << 0) |
(XDMAC_GE) XDMAC Channel 0 Enable Bit
Definition at line 219 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GE_EN1 (0x1u << 1) |
(XDMAC_GE) XDMAC Channel 1 Enable Bit
Definition at line 220 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GE_EN10 (0x1u << 10) |
(XDMAC_GE) XDMAC Channel 10 Enable Bit
Definition at line 229 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GE_EN11 (0x1u << 11) |
(XDMAC_GE) XDMAC Channel 11 Enable Bit
Definition at line 230 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GE_EN12 (0x1u << 12) |
(XDMAC_GE) XDMAC Channel 12 Enable Bit
Definition at line 231 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GE_EN13 (0x1u << 13) |
(XDMAC_GE) XDMAC Channel 13 Enable Bit
Definition at line 232 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GE_EN14 (0x1u << 14) |
(XDMAC_GE) XDMAC Channel 14 Enable Bit
Definition at line 233 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GE_EN15 (0x1u << 15) |
(XDMAC_GE) XDMAC Channel 15 Enable Bit
Definition at line 234 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GE_EN16 (0x1u << 16) |
(XDMAC_GE) XDMAC Channel 16 Enable Bit
Definition at line 235 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GE_EN17 (0x1u << 17) |
(XDMAC_GE) XDMAC Channel 17 Enable Bit
Definition at line 236 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GE_EN18 (0x1u << 18) |
(XDMAC_GE) XDMAC Channel 18 Enable Bit
Definition at line 237 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GE_EN19 (0x1u << 19) |
(XDMAC_GE) XDMAC Channel 19 Enable Bit
Definition at line 238 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GE_EN2 (0x1u << 2) |
(XDMAC_GE) XDMAC Channel 2 Enable Bit
Definition at line 221 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GE_EN20 (0x1u << 20) |
(XDMAC_GE) XDMAC Channel 20 Enable Bit
Definition at line 239 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GE_EN21 (0x1u << 21) |
(XDMAC_GE) XDMAC Channel 21 Enable Bit
Definition at line 240 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GE_EN22 (0x1u << 22) |
(XDMAC_GE) XDMAC Channel 22 Enable Bit
Definition at line 241 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GE_EN23 (0x1u << 23) |
(XDMAC_GE) XDMAC Channel 23 Enable Bit
Definition at line 242 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GE_EN3 (0x1u << 3) |
(XDMAC_GE) XDMAC Channel 3 Enable Bit
Definition at line 222 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GE_EN4 (0x1u << 4) |
(XDMAC_GE) XDMAC Channel 4 Enable Bit
Definition at line 223 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GE_EN5 (0x1u << 5) |
(XDMAC_GE) XDMAC Channel 5 Enable Bit
Definition at line 224 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GE_EN6 (0x1u << 6) |
(XDMAC_GE) XDMAC Channel 6 Enable Bit
Definition at line 225 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GE_EN7 (0x1u << 7) |
(XDMAC_GE) XDMAC Channel 7 Enable Bit
Definition at line 226 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GE_EN8 (0x1u << 8) |
(XDMAC_GE) XDMAC Channel 8 Enable Bit
Definition at line 227 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GE_EN9 (0x1u << 9) |
(XDMAC_GE) XDMAC Channel 9 Enable Bit
Definition at line 228 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GID_ID0 (0x1u << 0) |
(XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit
Definition at line 144 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GID_ID1 (0x1u << 1) |
(XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit
Definition at line 145 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GID_ID10 (0x1u << 10) |
(XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit
Definition at line 154 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GID_ID11 (0x1u << 11) |
(XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit
Definition at line 155 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GID_ID12 (0x1u << 12) |
(XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit
Definition at line 156 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GID_ID13 (0x1u << 13) |
(XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit
Definition at line 157 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GID_ID14 (0x1u << 14) |
(XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit
Definition at line 158 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GID_ID15 (0x1u << 15) |
(XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit
Definition at line 159 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GID_ID16 (0x1u << 16) |
(XDMAC_GID) XDMAC Channel 16 Interrupt Disable Bit
Definition at line 160 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GID_ID17 (0x1u << 17) |
(XDMAC_GID) XDMAC Channel 17 Interrupt Disable Bit
Definition at line 161 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GID_ID18 (0x1u << 18) |
(XDMAC_GID) XDMAC Channel 18 Interrupt Disable Bit
Definition at line 162 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GID_ID19 (0x1u << 19) |
(XDMAC_GID) XDMAC Channel 19 Interrupt Disable Bit
Definition at line 163 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GID_ID2 (0x1u << 2) |
(XDMAC_GID) XDMAC Channel 2 Interrupt Disable Bit
Definition at line 146 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GID_ID20 (0x1u << 20) |
(XDMAC_GID) XDMAC Channel 20 Interrupt Disable Bit
Definition at line 164 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GID_ID21 (0x1u << 21) |
(XDMAC_GID) XDMAC Channel 21 Interrupt Disable Bit
Definition at line 165 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GID_ID22 (0x1u << 22) |
(XDMAC_GID) XDMAC Channel 22 Interrupt Disable Bit
Definition at line 166 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GID_ID23 (0x1u << 23) |
(XDMAC_GID) XDMAC Channel 23 Interrupt Disable Bit
Definition at line 167 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GID_ID3 (0x1u << 3) |
(XDMAC_GID) XDMAC Channel 3 Interrupt Disable Bit
Definition at line 147 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GID_ID4 (0x1u << 4) |
(XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit
Definition at line 148 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GID_ID5 (0x1u << 5) |
(XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit
Definition at line 149 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GID_ID6 (0x1u << 6) |
(XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit
Definition at line 150 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GID_ID7 (0x1u << 7) |
(XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit
Definition at line 151 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GID_ID8 (0x1u << 8) |
(XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit
Definition at line 152 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GID_ID9 (0x1u << 9) |
(XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit
Definition at line 153 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIE_IE0 (0x1u << 0) |
(XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit
Definition at line 119 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIE_IE1 (0x1u << 1) |
(XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit
Definition at line 120 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIE_IE10 (0x1u << 10) |
(XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit
Definition at line 129 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIE_IE11 (0x1u << 11) |
(XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit
Definition at line 130 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIE_IE12 (0x1u << 12) |
(XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit
Definition at line 131 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIE_IE13 (0x1u << 13) |
(XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit
Definition at line 132 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIE_IE14 (0x1u << 14) |
(XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit
Definition at line 133 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIE_IE15 (0x1u << 15) |
(XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit
Definition at line 134 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIE_IE16 (0x1u << 16) |
(XDMAC_GIE) XDMAC Channel 16 Interrupt Enable Bit
Definition at line 135 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIE_IE17 (0x1u << 17) |
(XDMAC_GIE) XDMAC Channel 17 Interrupt Enable Bit
Definition at line 136 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIE_IE18 (0x1u << 18) |
(XDMAC_GIE) XDMAC Channel 18 Interrupt Enable Bit
Definition at line 137 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIE_IE19 (0x1u << 19) |
(XDMAC_GIE) XDMAC Channel 19 Interrupt Enable Bit
Definition at line 138 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIE_IE2 (0x1u << 2) |
(XDMAC_GIE) XDMAC Channel 2 Interrupt Enable Bit
Definition at line 121 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIE_IE20 (0x1u << 20) |
(XDMAC_GIE) XDMAC Channel 20 Interrupt Enable Bit
Definition at line 139 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIE_IE21 (0x1u << 21) |
(XDMAC_GIE) XDMAC Channel 21 Interrupt Enable Bit
Definition at line 140 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIE_IE22 (0x1u << 22) |
(XDMAC_GIE) XDMAC Channel 22 Interrupt Enable Bit
Definition at line 141 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIE_IE23 (0x1u << 23) |
(XDMAC_GIE) XDMAC Channel 23 Interrupt Enable Bit
Definition at line 142 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIE_IE3 (0x1u << 3) |
(XDMAC_GIE) XDMAC Channel 3 Interrupt Enable Bit
Definition at line 122 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIE_IE4 (0x1u << 4) |
(XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit
Definition at line 123 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIE_IE5 (0x1u << 5) |
(XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit
Definition at line 124 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIE_IE6 (0x1u << 6) |
(XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit
Definition at line 125 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIE_IE7 (0x1u << 7) |
(XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit
Definition at line 126 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIE_IE8 (0x1u << 8) |
(XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit
Definition at line 127 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIE_IE9 (0x1u << 9) |
(XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit
Definition at line 128 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIM_IM0 (0x1u << 0) |
(XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit
Definition at line 169 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIM_IM1 (0x1u << 1) |
(XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit
Definition at line 170 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIM_IM10 (0x1u << 10) |
(XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit
Definition at line 179 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIM_IM11 (0x1u << 11) |
(XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit
Definition at line 180 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIM_IM12 (0x1u << 12) |
(XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit
Definition at line 181 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIM_IM13 (0x1u << 13) |
(XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit
Definition at line 182 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIM_IM14 (0x1u << 14) |
(XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit
Definition at line 183 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIM_IM15 (0x1u << 15) |
(XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit
Definition at line 184 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIM_IM16 (0x1u << 16) |
(XDMAC_GIM) XDMAC Channel 16 Interrupt Mask Bit
Definition at line 185 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIM_IM17 (0x1u << 17) |
(XDMAC_GIM) XDMAC Channel 17 Interrupt Mask Bit
Definition at line 186 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIM_IM18 (0x1u << 18) |
(XDMAC_GIM) XDMAC Channel 18 Interrupt Mask Bit
Definition at line 187 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIM_IM19 (0x1u << 19) |
(XDMAC_GIM) XDMAC Channel 19 Interrupt Mask Bit
Definition at line 188 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIM_IM2 (0x1u << 2) |
(XDMAC_GIM) XDMAC Channel 2 Interrupt Mask Bit
Definition at line 171 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIM_IM20 (0x1u << 20) |
(XDMAC_GIM) XDMAC Channel 20 Interrupt Mask Bit
Definition at line 189 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIM_IM21 (0x1u << 21) |
(XDMAC_GIM) XDMAC Channel 21 Interrupt Mask Bit
Definition at line 190 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIM_IM22 (0x1u << 22) |
(XDMAC_GIM) XDMAC Channel 22 Interrupt Mask Bit
Definition at line 191 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIM_IM23 (0x1u << 23) |
(XDMAC_GIM) XDMAC Channel 23 Interrupt Mask Bit
Definition at line 192 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIM_IM3 (0x1u << 3) |
(XDMAC_GIM) XDMAC Channel 3 Interrupt Mask Bit
Definition at line 172 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIM_IM4 (0x1u << 4) |
(XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit
Definition at line 173 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIM_IM5 (0x1u << 5) |
(XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit
Definition at line 174 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIM_IM6 (0x1u << 6) |
(XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit
Definition at line 175 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIM_IM7 (0x1u << 7) |
(XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit
Definition at line 176 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIM_IM8 (0x1u << 8) |
(XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit
Definition at line 177 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIM_IM9 (0x1u << 9) |
(XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit
Definition at line 178 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIS_IS0 (0x1u << 0) |
(XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit
Definition at line 194 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIS_IS1 (0x1u << 1) |
(XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit
Definition at line 195 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIS_IS10 (0x1u << 10) |
(XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit
Definition at line 204 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIS_IS11 (0x1u << 11) |
(XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit
Definition at line 205 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIS_IS12 (0x1u << 12) |
(XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit
Definition at line 206 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIS_IS13 (0x1u << 13) |
(XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit
Definition at line 207 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIS_IS14 (0x1u << 14) |
(XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit
Definition at line 208 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIS_IS15 (0x1u << 15) |
(XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit
Definition at line 209 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIS_IS16 (0x1u << 16) |
(XDMAC_GIS) XDMAC Channel 16 Interrupt Status Bit
Definition at line 210 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIS_IS17 (0x1u << 17) |
(XDMAC_GIS) XDMAC Channel 17 Interrupt Status Bit
Definition at line 211 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIS_IS18 (0x1u << 18) |
(XDMAC_GIS) XDMAC Channel 18 Interrupt Status Bit
Definition at line 212 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIS_IS19 (0x1u << 19) |
(XDMAC_GIS) XDMAC Channel 19 Interrupt Status Bit
Definition at line 213 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIS_IS2 (0x1u << 2) |
(XDMAC_GIS) XDMAC Channel 2 Interrupt Status Bit
Definition at line 196 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIS_IS20 (0x1u << 20) |
(XDMAC_GIS) XDMAC Channel 20 Interrupt Status Bit
Definition at line 214 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIS_IS21 (0x1u << 21) |
(XDMAC_GIS) XDMAC Channel 21 Interrupt Status Bit
Definition at line 215 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIS_IS22 (0x1u << 22) |
(XDMAC_GIS) XDMAC Channel 22 Interrupt Status Bit
Definition at line 216 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIS_IS23 (0x1u << 23) |
(XDMAC_GIS) XDMAC Channel 23 Interrupt Status Bit
Definition at line 217 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIS_IS3 (0x1u << 3) |
(XDMAC_GIS) XDMAC Channel 3 Interrupt Status Bit
Definition at line 197 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIS_IS4 (0x1u << 4) |
(XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit
Definition at line 198 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIS_IS5 (0x1u << 5) |
(XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit
Definition at line 199 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIS_IS6 (0x1u << 6) |
(XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit
Definition at line 200 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIS_IS7 (0x1u << 7) |
(XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit
Definition at line 201 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIS_IS8 (0x1u << 8) |
(XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit
Definition at line 202 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GIS_IS9 (0x1u << 9) |
(XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit
Definition at line 203 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRS_RS0 (0x1u << 0) |
(XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit
Definition at line 294 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRS_RS1 (0x1u << 1) |
(XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit
Definition at line 295 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRS_RS10 (0x1u << 10) |
(XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit
Definition at line 304 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRS_RS11 (0x1u << 11) |
(XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit
Definition at line 305 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRS_RS12 (0x1u << 12) |
(XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit
Definition at line 306 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRS_RS13 (0x1u << 13) |
(XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit
Definition at line 307 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRS_RS14 (0x1u << 14) |
(XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit
Definition at line 308 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRS_RS15 (0x1u << 15) |
(XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit
Definition at line 309 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRS_RS16 (0x1u << 16) |
(XDMAC_GRS) XDMAC Channel 16 Read Suspend Bit
Definition at line 310 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRS_RS17 (0x1u << 17) |
(XDMAC_GRS) XDMAC Channel 17 Read Suspend Bit
Definition at line 311 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRS_RS18 (0x1u << 18) |
(XDMAC_GRS) XDMAC Channel 18 Read Suspend Bit
Definition at line 312 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRS_RS19 (0x1u << 19) |
(XDMAC_GRS) XDMAC Channel 19 Read Suspend Bit
Definition at line 313 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRS_RS2 (0x1u << 2) |
(XDMAC_GRS) XDMAC Channel 2 Read Suspend Bit
Definition at line 296 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRS_RS20 (0x1u << 20) |
(XDMAC_GRS) XDMAC Channel 20 Read Suspend Bit
Definition at line 314 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRS_RS21 (0x1u << 21) |
(XDMAC_GRS) XDMAC Channel 21 Read Suspend Bit
Definition at line 315 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRS_RS22 (0x1u << 22) |
(XDMAC_GRS) XDMAC Channel 22 Read Suspend Bit
Definition at line 316 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRS_RS23 (0x1u << 23) |
(XDMAC_GRS) XDMAC Channel 23 Read Suspend Bit
Definition at line 317 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRS_RS3 (0x1u << 3) |
(XDMAC_GRS) XDMAC Channel 3 Read Suspend Bit
Definition at line 297 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRS_RS4 (0x1u << 4) |
(XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit
Definition at line 298 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRS_RS5 (0x1u << 5) |
(XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit
Definition at line 299 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRS_RS6 (0x1u << 6) |
(XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit
Definition at line 300 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRS_RS7 (0x1u << 7) |
(XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit
Definition at line 301 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRS_RS8 (0x1u << 8) |
(XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit
Definition at line 302 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRS_RS9 (0x1u << 9) |
(XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit
Definition at line 303 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWR_RWR0 (0x1u << 0) |
(XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit
Definition at line 369 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWR_RWR1 (0x1u << 1) |
(XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit
Definition at line 370 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWR_RWR10 (0x1u << 10) |
(XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit
Definition at line 379 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWR_RWR11 (0x1u << 11) |
(XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit
Definition at line 380 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWR_RWR12 (0x1u << 12) |
(XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit
Definition at line 381 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWR_RWR13 (0x1u << 13) |
(XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit
Definition at line 382 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWR_RWR14 (0x1u << 14) |
(XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit
Definition at line 383 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWR_RWR15 (0x1u << 15) |
(XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit
Definition at line 384 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWR_RWR16 (0x1u << 16) |
(XDMAC_GRWR) XDMAC Channel 16 Read Write Resume Bit
Definition at line 385 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWR_RWR17 (0x1u << 17) |
(XDMAC_GRWR) XDMAC Channel 17 Read Write Resume Bit
Definition at line 386 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWR_RWR18 (0x1u << 18) |
(XDMAC_GRWR) XDMAC Channel 18 Read Write Resume Bit
Definition at line 387 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWR_RWR19 (0x1u << 19) |
(XDMAC_GRWR) XDMAC Channel 19 Read Write Resume Bit
Definition at line 388 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWR_RWR2 (0x1u << 2) |
(XDMAC_GRWR) XDMAC Channel 2 Read Write Resume Bit
Definition at line 371 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWR_RWR20 (0x1u << 20) |
(XDMAC_GRWR) XDMAC Channel 20 Read Write Resume Bit
Definition at line 389 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWR_RWR21 (0x1u << 21) |
(XDMAC_GRWR) XDMAC Channel 21 Read Write Resume Bit
Definition at line 390 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWR_RWR22 (0x1u << 22) |
(XDMAC_GRWR) XDMAC Channel 22 Read Write Resume Bit
Definition at line 391 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWR_RWR23 (0x1u << 23) |
(XDMAC_GRWR) XDMAC Channel 23 Read Write Resume Bit
Definition at line 392 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWR_RWR3 (0x1u << 3) |
(XDMAC_GRWR) XDMAC Channel 3 Read Write Resume Bit
Definition at line 372 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWR_RWR4 (0x1u << 4) |
(XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit
Definition at line 373 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWR_RWR5 (0x1u << 5) |
(XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit
Definition at line 374 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWR_RWR6 (0x1u << 6) |
(XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit
Definition at line 375 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWR_RWR7 (0x1u << 7) |
(XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit
Definition at line 376 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWR_RWR8 (0x1u << 8) |
(XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit
Definition at line 377 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWR_RWR9 (0x1u << 9) |
(XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit
Definition at line 378 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWS_RWS0 (0x1u << 0) |
(XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit
Definition at line 344 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWS_RWS1 (0x1u << 1) |
(XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit
Definition at line 345 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWS_RWS10 (0x1u << 10) |
(XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit
Definition at line 354 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWS_RWS11 (0x1u << 11) |
(XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit
Definition at line 355 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWS_RWS12 (0x1u << 12) |
(XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit
Definition at line 356 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWS_RWS13 (0x1u << 13) |
(XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit
Definition at line 357 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWS_RWS14 (0x1u << 14) |
(XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit
Definition at line 358 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWS_RWS15 (0x1u << 15) |
(XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit
Definition at line 359 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWS_RWS16 (0x1u << 16) |
(XDMAC_GRWS) XDMAC Channel 16 Read Write Suspend Bit
Definition at line 360 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWS_RWS17 (0x1u << 17) |
(XDMAC_GRWS) XDMAC Channel 17 Read Write Suspend Bit
Definition at line 361 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWS_RWS18 (0x1u << 18) |
(XDMAC_GRWS) XDMAC Channel 18 Read Write Suspend Bit
Definition at line 362 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWS_RWS19 (0x1u << 19) |
(XDMAC_GRWS) XDMAC Channel 19 Read Write Suspend Bit
Definition at line 363 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWS_RWS2 (0x1u << 2) |
(XDMAC_GRWS) XDMAC Channel 2 Read Write Suspend Bit
Definition at line 346 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWS_RWS20 (0x1u << 20) |
(XDMAC_GRWS) XDMAC Channel 20 Read Write Suspend Bit
Definition at line 364 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWS_RWS21 (0x1u << 21) |
(XDMAC_GRWS) XDMAC Channel 21 Read Write Suspend Bit
Definition at line 365 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWS_RWS22 (0x1u << 22) |
(XDMAC_GRWS) XDMAC Channel 22 Read Write Suspend Bit
Definition at line 366 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWS_RWS23 (0x1u << 23) |
(XDMAC_GRWS) XDMAC Channel 23 Read Write Suspend Bit
Definition at line 367 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWS_RWS3 (0x1u << 3) |
(XDMAC_GRWS) XDMAC Channel 3 Read Write Suspend Bit
Definition at line 347 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWS_RWS4 (0x1u << 4) |
(XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit
Definition at line 348 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWS_RWS5 (0x1u << 5) |
(XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit
Definition at line 349 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWS_RWS6 (0x1u << 6) |
(XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit
Definition at line 350 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWS_RWS7 (0x1u << 7) |
(XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit
Definition at line 351 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWS_RWS8 (0x1u << 8) |
(XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit
Definition at line 352 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GRWS_RWS9 (0x1u << 9) |
(XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit
Definition at line 353 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GS_ST0 (0x1u << 0) |
(XDMAC_GS) XDMAC Channel 0 Status Bit
Definition at line 269 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GS_ST1 (0x1u << 1) |
(XDMAC_GS) XDMAC Channel 1 Status Bit
Definition at line 270 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GS_ST10 (0x1u << 10) |
(XDMAC_GS) XDMAC Channel 10 Status Bit
Definition at line 279 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GS_ST11 (0x1u << 11) |
(XDMAC_GS) XDMAC Channel 11 Status Bit
Definition at line 280 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GS_ST12 (0x1u << 12) |
(XDMAC_GS) XDMAC Channel 12 Status Bit
Definition at line 281 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GS_ST13 (0x1u << 13) |
(XDMAC_GS) XDMAC Channel 13 Status Bit
Definition at line 282 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GS_ST14 (0x1u << 14) |
(XDMAC_GS) XDMAC Channel 14 Status Bit
Definition at line 283 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GS_ST15 (0x1u << 15) |
(XDMAC_GS) XDMAC Channel 15 Status Bit
Definition at line 284 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GS_ST16 (0x1u << 16) |
(XDMAC_GS) XDMAC Channel 16 Status Bit
Definition at line 285 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GS_ST17 (0x1u << 17) |
(XDMAC_GS) XDMAC Channel 17 Status Bit
Definition at line 286 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GS_ST18 (0x1u << 18) |
(XDMAC_GS) XDMAC Channel 18 Status Bit
Definition at line 287 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GS_ST19 (0x1u << 19) |
(XDMAC_GS) XDMAC Channel 19 Status Bit
Definition at line 288 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GS_ST2 (0x1u << 2) |
(XDMAC_GS) XDMAC Channel 2 Status Bit
Definition at line 271 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GS_ST20 (0x1u << 20) |
(XDMAC_GS) XDMAC Channel 20 Status Bit
Definition at line 289 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GS_ST21 (0x1u << 21) |
(XDMAC_GS) XDMAC Channel 21 Status Bit
Definition at line 290 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GS_ST22 (0x1u << 22) |
(XDMAC_GS) XDMAC Channel 22 Status Bit
Definition at line 291 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GS_ST23 (0x1u << 23) |
(XDMAC_GS) XDMAC Channel 23 Status Bit
Definition at line 292 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GS_ST3 (0x1u << 3) |
(XDMAC_GS) XDMAC Channel 3 Status Bit
Definition at line 272 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GS_ST4 (0x1u << 4) |
(XDMAC_GS) XDMAC Channel 4 Status Bit
Definition at line 273 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GS_ST5 (0x1u << 5) |
(XDMAC_GS) XDMAC Channel 5 Status Bit
Definition at line 274 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GS_ST6 (0x1u << 6) |
(XDMAC_GS) XDMAC Channel 6 Status Bit
Definition at line 275 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GS_ST7 (0x1u << 7) |
(XDMAC_GS) XDMAC Channel 7 Status Bit
Definition at line 276 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GS_ST8 (0x1u << 8) |
(XDMAC_GS) XDMAC Channel 8 Status Bit
Definition at line 277 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GS_ST9 (0x1u << 9) |
(XDMAC_GS) XDMAC Channel 9 Status Bit
Definition at line 278 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWF_SWF0 (0x1u << 0) |
(XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit
Definition at line 444 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWF_SWF1 (0x1u << 1) |
(XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit
Definition at line 445 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWF_SWF10 (0x1u << 10) |
(XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit
Definition at line 454 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWF_SWF11 (0x1u << 11) |
(XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit
Definition at line 455 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWF_SWF12 (0x1u << 12) |
(XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit
Definition at line 456 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWF_SWF13 (0x1u << 13) |
(XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit
Definition at line 457 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWF_SWF14 (0x1u << 14) |
(XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit
Definition at line 458 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWF_SWF15 (0x1u << 15) |
(XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit
Definition at line 459 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWF_SWF16 (0x1u << 16) |
(XDMAC_GSWF) XDMAC Channel 16 Software Flush Request Bit
Definition at line 460 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWF_SWF17 (0x1u << 17) |
(XDMAC_GSWF) XDMAC Channel 17 Software Flush Request Bit
Definition at line 461 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWF_SWF18 (0x1u << 18) |
(XDMAC_GSWF) XDMAC Channel 18 Software Flush Request Bit
Definition at line 462 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWF_SWF19 (0x1u << 19) |
(XDMAC_GSWF) XDMAC Channel 19 Software Flush Request Bit
Definition at line 463 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWF_SWF2 (0x1u << 2) |
(XDMAC_GSWF) XDMAC Channel 2 Software Flush Request Bit
Definition at line 446 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWF_SWF20 (0x1u << 20) |
(XDMAC_GSWF) XDMAC Channel 20 Software Flush Request Bit
Definition at line 464 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWF_SWF21 (0x1u << 21) |
(XDMAC_GSWF) XDMAC Channel 21 Software Flush Request Bit
Definition at line 465 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWF_SWF22 (0x1u << 22) |
(XDMAC_GSWF) XDMAC Channel 22 Software Flush Request Bit
Definition at line 466 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWF_SWF23 (0x1u << 23) |
(XDMAC_GSWF) XDMAC Channel 23 Software Flush Request Bit
Definition at line 467 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWF_SWF3 (0x1u << 3) |
(XDMAC_GSWF) XDMAC Channel 3 Software Flush Request Bit
Definition at line 447 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWF_SWF4 (0x1u << 4) |
(XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit
Definition at line 448 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWF_SWF5 (0x1u << 5) |
(XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit
Definition at line 449 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWF_SWF6 (0x1u << 6) |
(XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit
Definition at line 450 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWF_SWF7 (0x1u << 7) |
(XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit
Definition at line 451 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWF_SWF8 (0x1u << 8) |
(XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit
Definition at line 452 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWF_SWF9 (0x1u << 9) |
(XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit
Definition at line 453 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWR_SWREQ0 (0x1u << 0) |
(XDMAC_GSWR) XDMAC Channel 0 Software Request Bit
Definition at line 394 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWR_SWREQ1 (0x1u << 1) |
(XDMAC_GSWR) XDMAC Channel 1 Software Request Bit
Definition at line 395 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWR_SWREQ10 (0x1u << 10) |
(XDMAC_GSWR) XDMAC Channel 10 Software Request Bit
Definition at line 404 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWR_SWREQ11 (0x1u << 11) |
(XDMAC_GSWR) XDMAC Channel 11 Software Request Bit
Definition at line 405 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWR_SWREQ12 (0x1u << 12) |
(XDMAC_GSWR) XDMAC Channel 12 Software Request Bit
Definition at line 406 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWR_SWREQ13 (0x1u << 13) |
(XDMAC_GSWR) XDMAC Channel 13 Software Request Bit
Definition at line 407 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWR_SWREQ14 (0x1u << 14) |
(XDMAC_GSWR) XDMAC Channel 14 Software Request Bit
Definition at line 408 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWR_SWREQ15 (0x1u << 15) |
(XDMAC_GSWR) XDMAC Channel 15 Software Request Bit
Definition at line 409 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWR_SWREQ16 (0x1u << 16) |
(XDMAC_GSWR) XDMAC Channel 16 Software Request Bit
Definition at line 410 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWR_SWREQ17 (0x1u << 17) |
(XDMAC_GSWR) XDMAC Channel 17 Software Request Bit
Definition at line 411 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWR_SWREQ18 (0x1u << 18) |
(XDMAC_GSWR) XDMAC Channel 18 Software Request Bit
Definition at line 412 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWR_SWREQ19 (0x1u << 19) |
(XDMAC_GSWR) XDMAC Channel 19 Software Request Bit
Definition at line 413 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWR_SWREQ2 (0x1u << 2) |
(XDMAC_GSWR) XDMAC Channel 2 Software Request Bit
Definition at line 396 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWR_SWREQ20 (0x1u << 20) |
(XDMAC_GSWR) XDMAC Channel 20 Software Request Bit
Definition at line 414 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWR_SWREQ21 (0x1u << 21) |
(XDMAC_GSWR) XDMAC Channel 21 Software Request Bit
Definition at line 415 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWR_SWREQ22 (0x1u << 22) |
(XDMAC_GSWR) XDMAC Channel 22 Software Request Bit
Definition at line 416 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWR_SWREQ23 (0x1u << 23) |
(XDMAC_GSWR) XDMAC Channel 23 Software Request Bit
Definition at line 417 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWR_SWREQ3 (0x1u << 3) |
(XDMAC_GSWR) XDMAC Channel 3 Software Request Bit
Definition at line 397 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWR_SWREQ4 (0x1u << 4) |
(XDMAC_GSWR) XDMAC Channel 4 Software Request Bit
Definition at line 398 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWR_SWREQ5 (0x1u << 5) |
(XDMAC_GSWR) XDMAC Channel 5 Software Request Bit
Definition at line 399 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWR_SWREQ6 (0x1u << 6) |
(XDMAC_GSWR) XDMAC Channel 6 Software Request Bit
Definition at line 400 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWR_SWREQ7 (0x1u << 7) |
(XDMAC_GSWR) XDMAC Channel 7 Software Request Bit
Definition at line 401 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWR_SWREQ8 (0x1u << 8) |
(XDMAC_GSWR) XDMAC Channel 8 Software Request Bit
Definition at line 402 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWR_SWREQ9 (0x1u << 9) |
(XDMAC_GSWR) XDMAC Channel 9 Software Request Bit
Definition at line 403 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWS_SWRS0 (0x1u << 0) |
(XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit
Definition at line 419 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWS_SWRS1 (0x1u << 1) |
(XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit
Definition at line 420 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWS_SWRS10 (0x1u << 10) |
(XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit
Definition at line 429 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWS_SWRS11 (0x1u << 11) |
(XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit
Definition at line 430 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWS_SWRS12 (0x1u << 12) |
(XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit
Definition at line 431 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWS_SWRS13 (0x1u << 13) |
(XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit
Definition at line 432 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWS_SWRS14 (0x1u << 14) |
(XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit
Definition at line 433 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWS_SWRS15 (0x1u << 15) |
(XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit
Definition at line 434 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWS_SWRS16 (0x1u << 16) |
(XDMAC_GSWS) XDMAC Channel 16 Software Request Status Bit
Definition at line 435 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWS_SWRS17 (0x1u << 17) |
(XDMAC_GSWS) XDMAC Channel 17 Software Request Status Bit
Definition at line 436 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWS_SWRS18 (0x1u << 18) |
(XDMAC_GSWS) XDMAC Channel 18 Software Request Status Bit
Definition at line 437 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWS_SWRS19 (0x1u << 19) |
(XDMAC_GSWS) XDMAC Channel 19 Software Request Status Bit
Definition at line 438 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWS_SWRS2 (0x1u << 2) |
(XDMAC_GSWS) XDMAC Channel 2 Software Request Status Bit
Definition at line 421 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWS_SWRS20 (0x1u << 20) |
(XDMAC_GSWS) XDMAC Channel 20 Software Request Status Bit
Definition at line 439 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWS_SWRS21 (0x1u << 21) |
(XDMAC_GSWS) XDMAC Channel 21 Software Request Status Bit
Definition at line 440 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWS_SWRS22 (0x1u << 22) |
(XDMAC_GSWS) XDMAC Channel 22 Software Request Status Bit
Definition at line 441 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWS_SWRS23 (0x1u << 23) |
(XDMAC_GSWS) XDMAC Channel 23 Software Request Status Bit
Definition at line 442 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWS_SWRS3 (0x1u << 3) |
(XDMAC_GSWS) XDMAC Channel 3 Software Request Status Bit
Definition at line 422 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWS_SWRS4 (0x1u << 4) |
(XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit
Definition at line 423 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWS_SWRS5 (0x1u << 5) |
(XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit
Definition at line 424 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWS_SWRS6 (0x1u << 6) |
(XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit
Definition at line 425 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWS_SWRS7 (0x1u << 7) |
(XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit
Definition at line 426 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWS_SWRS8 (0x1u << 8) |
(XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit
Definition at line 427 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GSWS_SWRS9 (0x1u << 9) |
(XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit
Definition at line 428 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GTYPE_FIFO_SZ | ( | value | ) | ((XDMAC_GTYPE_FIFO_SZ_Msk & ((value) << XDMAC_GTYPE_FIFO_SZ_Pos))) |
Definition at line 95 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GTYPE_FIFO_SZ_Msk (0x7ffu << XDMAC_GTYPE_FIFO_SZ_Pos) |
(XDMAC_GTYPE) Number of Bytes
Definition at line 94 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GTYPE_FIFO_SZ_Pos 5 |
Definition at line 93 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GTYPE_NB_CH | ( | value | ) | ((XDMAC_GTYPE_NB_CH_Msk & ((value) << XDMAC_GTYPE_NB_CH_Pos))) |
Definition at line 92 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GTYPE_NB_CH_Msk (0x1fu << XDMAC_GTYPE_NB_CH_Pos) |
(XDMAC_GTYPE) Number of Channels Minus One
Definition at line 91 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GTYPE_NB_CH_Pos 0 |
Definition at line 90 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GTYPE_NB_REQ | ( | value | ) | ((XDMAC_GTYPE_NB_REQ_Msk & ((value) << XDMAC_GTYPE_NB_REQ_Pos))) |
Definition at line 98 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GTYPE_NB_REQ_Msk (0x7fu << XDMAC_GTYPE_NB_REQ_Pos) |
(XDMAC_GTYPE) Number of Peripheral Requests Minus One
Definition at line 97 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GTYPE_NB_REQ_Pos 16 |
Definition at line 96 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWAC_PW0 | ( | value | ) | ((XDMAC_GWAC_PW0_Msk & ((value) << XDMAC_GWAC_PW0_Pos))) |
Definition at line 108 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWAC_PW0_Msk (0xfu << XDMAC_GWAC_PW0_Pos) |
(XDMAC_GWAC) Pool Weight 0
Definition at line 107 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWAC_PW0_Pos 0 |
Definition at line 106 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWAC_PW1 | ( | value | ) | ((XDMAC_GWAC_PW1_Msk & ((value) << XDMAC_GWAC_PW1_Pos))) |
Definition at line 111 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWAC_PW1_Msk (0xfu << XDMAC_GWAC_PW1_Pos) |
(XDMAC_GWAC) Pool Weight 1
Definition at line 110 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWAC_PW1_Pos 4 |
Definition at line 109 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWAC_PW2 | ( | value | ) | ((XDMAC_GWAC_PW2_Msk & ((value) << XDMAC_GWAC_PW2_Pos))) |
Definition at line 114 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWAC_PW2_Msk (0xfu << XDMAC_GWAC_PW2_Pos) |
(XDMAC_GWAC) Pool Weight 2
Definition at line 113 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWAC_PW2_Pos 8 |
Definition at line 112 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWAC_PW3 | ( | value | ) | ((XDMAC_GWAC_PW3_Msk & ((value) << XDMAC_GWAC_PW3_Pos))) |
Definition at line 117 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWAC_PW3_Msk (0xfu << XDMAC_GWAC_PW3_Pos) |
(XDMAC_GWAC) Pool Weight 3
Definition at line 116 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWAC_PW3_Pos 12 |
Definition at line 115 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWS_WS0 (0x1u << 0) |
(XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit
Definition at line 319 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWS_WS1 (0x1u << 1) |
(XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit
Definition at line 320 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWS_WS10 (0x1u << 10) |
(XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit
Definition at line 329 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWS_WS11 (0x1u << 11) |
(XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit
Definition at line 330 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWS_WS12 (0x1u << 12) |
(XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit
Definition at line 331 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWS_WS13 (0x1u << 13) |
(XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit
Definition at line 332 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWS_WS14 (0x1u << 14) |
(XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit
Definition at line 333 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWS_WS15 (0x1u << 15) |
(XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit
Definition at line 334 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWS_WS16 (0x1u << 16) |
(XDMAC_GWS) XDMAC Channel 16 Write Suspend Bit
Definition at line 335 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWS_WS17 (0x1u << 17) |
(XDMAC_GWS) XDMAC Channel 17 Write Suspend Bit
Definition at line 336 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWS_WS18 (0x1u << 18) |
(XDMAC_GWS) XDMAC Channel 18 Write Suspend Bit
Definition at line 337 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWS_WS19 (0x1u << 19) |
(XDMAC_GWS) XDMAC Channel 19 Write Suspend Bit
Definition at line 338 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWS_WS2 (0x1u << 2) |
(XDMAC_GWS) XDMAC Channel 2 Write Suspend Bit
Definition at line 321 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWS_WS20 (0x1u << 20) |
(XDMAC_GWS) XDMAC Channel 20 Write Suspend Bit
Definition at line 339 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWS_WS21 (0x1u << 21) |
(XDMAC_GWS) XDMAC Channel 21 Write Suspend Bit
Definition at line 340 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWS_WS22 (0x1u << 22) |
(XDMAC_GWS) XDMAC Channel 22 Write Suspend Bit
Definition at line 341 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWS_WS23 (0x1u << 23) |
(XDMAC_GWS) XDMAC Channel 23 Write Suspend Bit
Definition at line 342 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWS_WS3 (0x1u << 3) |
(XDMAC_GWS) XDMAC Channel 3 Write Suspend Bit
Definition at line 322 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWS_WS4 (0x1u << 4) |
(XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit
Definition at line 323 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWS_WS5 (0x1u << 5) |
(XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit
Definition at line 324 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWS_WS6 (0x1u << 6) |
(XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit
Definition at line 325 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWS_WS7 (0x1u << 7) |
(XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit
Definition at line 326 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWS_WS8 (0x1u << 8) |
(XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit
Definition at line 327 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_GWS_WS9 (0x1u << 9) |
(XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit
Definition at line 328 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_VERSION_MFN | ( | value | ) | ((XDMAC_VERSION_MFN_Msk & ((value) << XDMAC_VERSION_MFN_Pos))) |
Definition at line 628 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_VERSION_MFN_Msk (0x7u << XDMAC_VERSION_MFN_Pos) |
(XDMAC_VERSION) Metal Fix Number
Definition at line 627 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_VERSION_MFN_Pos 16 |
Definition at line 626 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_VERSION_VERSION | ( | value | ) | ((XDMAC_VERSION_VERSION_Msk & ((value) << XDMAC_VERSION_VERSION_Pos))) |
Definition at line 625 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_VERSION_VERSION_Msk (0xfffu << XDMAC_VERSION_VERSION_Pos) |
(XDMAC_VERSION) Version of the Hardware Module
Definition at line 624 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMAC_VERSION_VERSION_Pos 0 |
Definition at line 623 of file utils/cmsis/same70/include/component/xdmac.h.
| #define XDMACCHID_NUMBER 24 |
Xdmac hardware registers.
Definition at line 64 of file utils/cmsis/same70/include/component/xdmac.h.