Classes | |
| struct | Rswdt |
| Rswdt hardware registers. More... | |
Macros | |
| #define | RSWDT_CR_KEY(value) ((RSWDT_CR_KEY_Msk & ((value) << RSWDT_CR_KEY_Pos))) |
| #define | RSWDT_CR_KEY_Msk (0xffu << RSWDT_CR_KEY_Pos) |
| (RSWDT_CR) Password More... | |
| #define | RSWDT_CR_KEY_PASSWD (0xC4u << 24) |
| (RSWDT_CR) Writing any other value in this field aborts the write operation. More... | |
| #define | RSWDT_CR_KEY_Pos 24 |
| #define | RSWDT_CR_WDRSTT (0x1u << 0) |
| (RSWDT_CR) Watchdog Restart More... | |
| #define | RSWDT_MR_ALLONES(value) ((RSWDT_MR_ALLONES_Msk & ((value) << RSWDT_MR_ALLONES_Pos))) |
| #define | RSWDT_MR_ALLONES_Msk (0xfffu << RSWDT_MR_ALLONES_Pos) |
| (RSWDT_MR) Must Always Be Written with 0xFFF More... | |
| #define | RSWDT_MR_ALLONES_Pos 16 |
| #define | RSWDT_MR_WDDBGHLT (0x1u << 28) |
| (RSWDT_MR) Watchdog Debug Halt More... | |
| #define | RSWDT_MR_WDDIS (0x1u << 15) |
| (RSWDT_MR) Watchdog Disable More... | |
| #define | RSWDT_MR_WDFIEN (0x1u << 12) |
| (RSWDT_MR) Watchdog Fault Interrupt Enable More... | |
| #define | RSWDT_MR_WDIDLEHLT (0x1u << 29) |
| (RSWDT_MR) Watchdog Idle Halt More... | |
| #define | RSWDT_MR_WDRPROC (0x1u << 14) |
| (RSWDT_MR) Watchdog Reset Processor More... | |
| #define | RSWDT_MR_WDRSTEN (0x1u << 13) |
| (RSWDT_MR) Watchdog Reset Enable More... | |
| #define | RSWDT_MR_WDV(value) ((RSWDT_MR_WDV_Msk & ((value) << RSWDT_MR_WDV_Pos))) |
| #define | RSWDT_MR_WDV_Msk (0xfffu << RSWDT_MR_WDV_Pos) |
| (RSWDT_MR) Watchdog Counter Value More... | |
| #define | RSWDT_MR_WDV_Pos 0 |
| #define | RSWDT_SR_WDUNF (0x1u << 0) |
| (RSWDT_SR) Watchdog Underflow More... | |
SOFTWARE API DEFINITION FOR Reinforced Safety Watchdog Timer
| #define RSWDT_CR_KEY | ( | value | ) | ((RSWDT_CR_KEY_Msk & ((value) << RSWDT_CR_KEY_Pos))) |
Definition at line 56 of file component/rswdt.h.
| #define RSWDT_CR_KEY_Msk (0xffu << RSWDT_CR_KEY_Pos) |
(RSWDT_CR) Password
Definition at line 55 of file component/rswdt.h.
| #define RSWDT_CR_KEY_PASSWD (0xC4u << 24) |
(RSWDT_CR) Writing any other value in this field aborts the write operation.
Definition at line 57 of file component/rswdt.h.
| #define RSWDT_CR_KEY_Pos 24 |
Definition at line 54 of file component/rswdt.h.
| #define RSWDT_CR_WDRSTT (0x1u << 0) |
(RSWDT_CR) Watchdog Restart
Definition at line 53 of file component/rswdt.h.
| #define RSWDT_MR_ALLONES | ( | value | ) | ((RSWDT_MR_ALLONES_Msk & ((value) << RSWDT_MR_ALLONES_Pos))) |
Definition at line 68 of file component/rswdt.h.
| #define RSWDT_MR_ALLONES_Msk (0xfffu << RSWDT_MR_ALLONES_Pos) |
(RSWDT_MR) Must Always Be Written with 0xFFF
Definition at line 67 of file component/rswdt.h.
| #define RSWDT_MR_ALLONES_Pos 16 |
Definition at line 66 of file component/rswdt.h.
| #define RSWDT_MR_WDDBGHLT (0x1u << 28) |
(RSWDT_MR) Watchdog Debug Halt
Definition at line 69 of file component/rswdt.h.
| #define RSWDT_MR_WDDIS (0x1u << 15) |
(RSWDT_MR) Watchdog Disable
Definition at line 65 of file component/rswdt.h.
| #define RSWDT_MR_WDFIEN (0x1u << 12) |
(RSWDT_MR) Watchdog Fault Interrupt Enable
Definition at line 62 of file component/rswdt.h.
| #define RSWDT_MR_WDIDLEHLT (0x1u << 29) |
(RSWDT_MR) Watchdog Idle Halt
Definition at line 70 of file component/rswdt.h.
| #define RSWDT_MR_WDRPROC (0x1u << 14) |
(RSWDT_MR) Watchdog Reset Processor
Definition at line 64 of file component/rswdt.h.
| #define RSWDT_MR_WDRSTEN (0x1u << 13) |
(RSWDT_MR) Watchdog Reset Enable
Definition at line 63 of file component/rswdt.h.
| #define RSWDT_MR_WDV | ( | value | ) | ((RSWDT_MR_WDV_Msk & ((value) << RSWDT_MR_WDV_Pos))) |
Definition at line 61 of file component/rswdt.h.
| #define RSWDT_MR_WDV_Msk (0xfffu << RSWDT_MR_WDV_Pos) |
(RSWDT_MR) Watchdog Counter Value
Definition at line 60 of file component/rswdt.h.
| #define RSWDT_MR_WDV_Pos 0 |
Definition at line 59 of file component/rswdt.h.
| #define RSWDT_SR_WDUNF (0x1u << 0) |
(RSWDT_SR) Watchdog Underflow
Definition at line 72 of file component/rswdt.h.