component/rswdt.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_RSWDT_COMPONENT_
36 #define _SAME70_RSWDT_COMPONENT_
37 
38 /* ============================================================================= */
40 /* ============================================================================= */
43 
44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
45 
46 typedef struct {
47  __O uint32_t RSWDT_CR;
48  __IO uint32_t RSWDT_MR;
49  __I uint32_t RSWDT_SR;
50 } Rswdt;
51 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
52 /* -------- RSWDT_CR : (RSWDT Offset: 0x00) Control Register -------- */
53 #define RSWDT_CR_WDRSTT (0x1u << 0)
54 #define RSWDT_CR_KEY_Pos 24
55 #define RSWDT_CR_KEY_Msk (0xffu << RSWDT_CR_KEY_Pos)
56 #define RSWDT_CR_KEY(value) ((RSWDT_CR_KEY_Msk & ((value) << RSWDT_CR_KEY_Pos)))
57 #define RSWDT_CR_KEY_PASSWD (0xC4u << 24)
58 /* -------- RSWDT_MR : (RSWDT Offset: 0x04) Mode Register -------- */
59 #define RSWDT_MR_WDV_Pos 0
60 #define RSWDT_MR_WDV_Msk (0xfffu << RSWDT_MR_WDV_Pos)
61 #define RSWDT_MR_WDV(value) ((RSWDT_MR_WDV_Msk & ((value) << RSWDT_MR_WDV_Pos)))
62 #define RSWDT_MR_WDFIEN (0x1u << 12)
63 #define RSWDT_MR_WDRSTEN (0x1u << 13)
64 #define RSWDT_MR_WDRPROC (0x1u << 14)
65 #define RSWDT_MR_WDDIS (0x1u << 15)
66 #define RSWDT_MR_ALLONES_Pos 16
67 #define RSWDT_MR_ALLONES_Msk (0xfffu << RSWDT_MR_ALLONES_Pos)
68 #define RSWDT_MR_ALLONES(value) ((RSWDT_MR_ALLONES_Msk & ((value) << RSWDT_MR_ALLONES_Pos)))
69 #define RSWDT_MR_WDDBGHLT (0x1u << 28)
70 #define RSWDT_MR_WDIDLEHLT (0x1u << 29)
71 /* -------- RSWDT_SR : (RSWDT Offset: 0x08) Status Register -------- */
72 #define RSWDT_SR_WDUNF (0x1u << 0)
75 
76 
77 #endif /* _SAME70_RSWDT_COMPONENT_ */
#define __IO
Definition: core_cm7.h:266
#define __O
Definition: core_cm7.h:265
__IO uint32_t RSWDT_MR
(Rswdt Offset: 0x04) Mode Register
Rswdt hardware registers.
__I uint32_t RSWDT_SR
(Rswdt Offset: 0x08) Status Register
__O uint32_t RSWDT_CR
(Rswdt Offset: 0x00) Control Register
#define __I
Definition: core_cm7.h:263


inertial_sense_ros
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autogenerated on Sat Sep 19 2020 03:19:04