component/isi.h
Go to the documentation of this file.
1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_ISI_COMPONENT_
36 #define _SAME70_ISI_COMPONENT_
37 
38 /* ============================================================================= */
40 /* ============================================================================= */
43 
44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
45 
46 typedef struct {
47  __IO uint32_t ISI_CFG1;
48  __IO uint32_t ISI_CFG2;
49  __IO uint32_t ISI_PSIZE;
50  __IO uint32_t ISI_PDECF;
51  __IO uint32_t ISI_Y2R_SET0;
52  __IO uint32_t ISI_Y2R_SET1;
53  __IO uint32_t ISI_R2Y_SET0;
54  __IO uint32_t ISI_R2Y_SET1;
55  __IO uint32_t ISI_R2Y_SET2;
56  __O uint32_t ISI_CR;
57  __I uint32_t ISI_SR;
58  __O uint32_t ISI_IER;
59  __O uint32_t ISI_IDR;
60  __I uint32_t ISI_IMR;
61  __O uint32_t ISI_DMA_CHER;
62  __O uint32_t ISI_DMA_CHDR;
63  __I uint32_t ISI_DMA_CHSR;
64  __IO uint32_t ISI_DMA_P_ADDR;
65  __IO uint32_t ISI_DMA_P_CTRL;
66  __IO uint32_t ISI_DMA_P_DSCR;
67  __IO uint32_t ISI_DMA_C_ADDR;
68  __IO uint32_t ISI_DMA_C_CTRL;
69  __IO uint32_t ISI_DMA_C_DSCR;
70  __I uint32_t Reserved1[34];
71  __IO uint32_t ISI_WPMR;
72  __I uint32_t ISI_WPSR;
73  __I uint32_t Reserved2[4];
74  __I uint32_t ISI_VERSION;
75 } Isi;
76 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
77 /* -------- ISI_CFG1 : (ISI Offset: 0x00) ISI Configuration 1 Register -------- */
78 #define ISI_CFG1_HSYNC_POL (0x1u << 2)
79 #define ISI_CFG1_VSYNC_POL (0x1u << 3)
80 #define ISI_CFG1_PIXCLK_POL (0x1u << 4)
81 #define ISI_CFG1_GRAYLE (0x1u << 5)
82 #define ISI_CFG1_EMB_SYNC (0x1u << 6)
83 #define ISI_CFG1_CRC_SYNC (0x1u << 7)
84 #define ISI_CFG1_FRATE_Pos 8
85 #define ISI_CFG1_FRATE_Msk (0x7u << ISI_CFG1_FRATE_Pos)
86 #define ISI_CFG1_FRATE(value) ((ISI_CFG1_FRATE_Msk & ((value) << ISI_CFG1_FRATE_Pos)))
87 #define ISI_CFG1_DISCR (0x1u << 11)
88 #define ISI_CFG1_FULL (0x1u << 12)
89 #define ISI_CFG1_THMASK_Pos 13
90 #define ISI_CFG1_THMASK_Msk (0x3u << ISI_CFG1_THMASK_Pos)
91 #define ISI_CFG1_THMASK(value) ((ISI_CFG1_THMASK_Msk & ((value) << ISI_CFG1_THMASK_Pos)))
92 #define ISI_CFG1_THMASK_BEATS_4 (0x0u << 13)
93 #define ISI_CFG1_THMASK_BEATS_8 (0x1u << 13)
94 #define ISI_CFG1_THMASK_BEATS_16 (0x2u << 13)
95 #define ISI_CFG1_SLD_Pos 16
96 #define ISI_CFG1_SLD_Msk (0xffu << ISI_CFG1_SLD_Pos)
97 #define ISI_CFG1_SLD(value) ((ISI_CFG1_SLD_Msk & ((value) << ISI_CFG1_SLD_Pos)))
98 #define ISI_CFG1_SFD_Pos 24
99 #define ISI_CFG1_SFD_Msk (0xffu << ISI_CFG1_SFD_Pos)
100 #define ISI_CFG1_SFD(value) ((ISI_CFG1_SFD_Msk & ((value) << ISI_CFG1_SFD_Pos)))
101 /* -------- ISI_CFG2 : (ISI Offset: 0x04) ISI Configuration 2 Register -------- */
102 #define ISI_CFG2_IM_VSIZE_Pos 0
103 #define ISI_CFG2_IM_VSIZE_Msk (0x7ffu << ISI_CFG2_IM_VSIZE_Pos)
104 #define ISI_CFG2_IM_VSIZE(value) ((ISI_CFG2_IM_VSIZE_Msk & ((value) << ISI_CFG2_IM_VSIZE_Pos)))
105 #define ISI_CFG2_GS_MODE (0x1u << 11)
106 #define ISI_CFG2_RGB_MODE (0x1u << 12)
107 #define ISI_CFG2_GRAYSCALE (0x1u << 13)
108 #define ISI_CFG2_RGB_SWAP (0x1u << 14)
109 #define ISI_CFG2_COL_SPACE (0x1u << 15)
110 #define ISI_CFG2_IM_HSIZE_Pos 16
111 #define ISI_CFG2_IM_HSIZE_Msk (0x7ffu << ISI_CFG2_IM_HSIZE_Pos)
112 #define ISI_CFG2_IM_HSIZE(value) ((ISI_CFG2_IM_HSIZE_Msk & ((value) << ISI_CFG2_IM_HSIZE_Pos)))
113 #define ISI_CFG2_YCC_SWAP_Pos 28
114 #define ISI_CFG2_YCC_SWAP_Msk (0x3u << ISI_CFG2_YCC_SWAP_Pos)
115 #define ISI_CFG2_YCC_SWAP(value) ((ISI_CFG2_YCC_SWAP_Msk & ((value) << ISI_CFG2_YCC_SWAP_Pos)))
116 #define ISI_CFG2_YCC_SWAP_DEFAULT (0x0u << 28)
117 #define ISI_CFG2_YCC_SWAP_MODE1 (0x1u << 28)
118 #define ISI_CFG2_YCC_SWAP_MODE2 (0x2u << 28)
119 #define ISI_CFG2_YCC_SWAP_MODE3 (0x3u << 28)
120 #define ISI_CFG2_RGB_CFG_Pos 30
121 #define ISI_CFG2_RGB_CFG_Msk (0x3u << ISI_CFG2_RGB_CFG_Pos)
122 #define ISI_CFG2_RGB_CFG(value) ((ISI_CFG2_RGB_CFG_Msk & ((value) << ISI_CFG2_RGB_CFG_Pos)))
123 #define ISI_CFG2_RGB_CFG_DEFAULT (0x0u << 30)
124 #define ISI_CFG2_RGB_CFG_MODE1 (0x1u << 30)
125 #define ISI_CFG2_RGB_CFG_MODE2 (0x2u << 30)
126 #define ISI_CFG2_RGB_CFG_MODE3 (0x3u << 30)
127 /* -------- ISI_PSIZE : (ISI Offset: 0x08) ISI Preview Size Register -------- */
128 #define ISI_PSIZE_PREV_VSIZE_Pos 0
129 #define ISI_PSIZE_PREV_VSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_VSIZE_Pos)
130 #define ISI_PSIZE_PREV_VSIZE(value) ((ISI_PSIZE_PREV_VSIZE_Msk & ((value) << ISI_PSIZE_PREV_VSIZE_Pos)))
131 #define ISI_PSIZE_PREV_HSIZE_Pos 16
132 #define ISI_PSIZE_PREV_HSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_HSIZE_Pos)
133 #define ISI_PSIZE_PREV_HSIZE(value) ((ISI_PSIZE_PREV_HSIZE_Msk & ((value) << ISI_PSIZE_PREV_HSIZE_Pos)))
134 /* -------- ISI_PDECF : (ISI Offset: 0x0C) ISI Preview Decimation Factor Register -------- */
135 #define ISI_PDECF_DEC_FACTOR_Pos 0
136 #define ISI_PDECF_DEC_FACTOR_Msk (0xffu << ISI_PDECF_DEC_FACTOR_Pos)
137 #define ISI_PDECF_DEC_FACTOR(value) ((ISI_PDECF_DEC_FACTOR_Msk & ((value) << ISI_PDECF_DEC_FACTOR_Pos)))
138 /* -------- ISI_Y2R_SET0 : (ISI Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register -------- */
139 #define ISI_Y2R_SET0_C0_Pos 0
140 #define ISI_Y2R_SET0_C0_Msk (0xffu << ISI_Y2R_SET0_C0_Pos)
141 #define ISI_Y2R_SET0_C0(value) ((ISI_Y2R_SET0_C0_Msk & ((value) << ISI_Y2R_SET0_C0_Pos)))
142 #define ISI_Y2R_SET0_C1_Pos 8
143 #define ISI_Y2R_SET0_C1_Msk (0xffu << ISI_Y2R_SET0_C1_Pos)
144 #define ISI_Y2R_SET0_C1(value) ((ISI_Y2R_SET0_C1_Msk & ((value) << ISI_Y2R_SET0_C1_Pos)))
145 #define ISI_Y2R_SET0_C2_Pos 16
146 #define ISI_Y2R_SET0_C2_Msk (0xffu << ISI_Y2R_SET0_C2_Pos)
147 #define ISI_Y2R_SET0_C2(value) ((ISI_Y2R_SET0_C2_Msk & ((value) << ISI_Y2R_SET0_C2_Pos)))
148 #define ISI_Y2R_SET0_C3_Pos 24
149 #define ISI_Y2R_SET0_C3_Msk (0xffu << ISI_Y2R_SET0_C3_Pos)
150 #define ISI_Y2R_SET0_C3(value) ((ISI_Y2R_SET0_C3_Msk & ((value) << ISI_Y2R_SET0_C3_Pos)))
151 /* -------- ISI_Y2R_SET1 : (ISI Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register -------- */
152 #define ISI_Y2R_SET1_C4_Pos 0
153 #define ISI_Y2R_SET1_C4_Msk (0x1ffu << ISI_Y2R_SET1_C4_Pos)
154 #define ISI_Y2R_SET1_C4(value) ((ISI_Y2R_SET1_C4_Msk & ((value) << ISI_Y2R_SET1_C4_Pos)))
155 #define ISI_Y2R_SET1_Yoff (0x1u << 12)
156 #define ISI_Y2R_SET1_Croff (0x1u << 13)
157 #define ISI_Y2R_SET1_Cboff (0x1u << 14)
158 /* -------- ISI_R2Y_SET0 : (ISI Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register -------- */
159 #define ISI_R2Y_SET0_C0_Pos 0
160 #define ISI_R2Y_SET0_C0_Msk (0x7fu << ISI_R2Y_SET0_C0_Pos)
161 #define ISI_R2Y_SET0_C0(value) ((ISI_R2Y_SET0_C0_Msk & ((value) << ISI_R2Y_SET0_C0_Pos)))
162 #define ISI_R2Y_SET0_C1_Pos 8
163 #define ISI_R2Y_SET0_C1_Msk (0x7fu << ISI_R2Y_SET0_C1_Pos)
164 #define ISI_R2Y_SET0_C1(value) ((ISI_R2Y_SET0_C1_Msk & ((value) << ISI_R2Y_SET0_C1_Pos)))
165 #define ISI_R2Y_SET0_C2_Pos 16
166 #define ISI_R2Y_SET0_C2_Msk (0x7fu << ISI_R2Y_SET0_C2_Pos)
167 #define ISI_R2Y_SET0_C2(value) ((ISI_R2Y_SET0_C2_Msk & ((value) << ISI_R2Y_SET0_C2_Pos)))
168 #define ISI_R2Y_SET0_Roff (0x1u << 24)
169 /* -------- ISI_R2Y_SET1 : (ISI Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register -------- */
170 #define ISI_R2Y_SET1_C3_Pos 0
171 #define ISI_R2Y_SET1_C3_Msk (0x7fu << ISI_R2Y_SET1_C3_Pos)
172 #define ISI_R2Y_SET1_C3(value) ((ISI_R2Y_SET1_C3_Msk & ((value) << ISI_R2Y_SET1_C3_Pos)))
173 #define ISI_R2Y_SET1_C4_Pos 8
174 #define ISI_R2Y_SET1_C4_Msk (0x7fu << ISI_R2Y_SET1_C4_Pos)
175 #define ISI_R2Y_SET1_C4(value) ((ISI_R2Y_SET1_C4_Msk & ((value) << ISI_R2Y_SET1_C4_Pos)))
176 #define ISI_R2Y_SET1_C5_Pos 16
177 #define ISI_R2Y_SET1_C5_Msk (0x7fu << ISI_R2Y_SET1_C5_Pos)
178 #define ISI_R2Y_SET1_C5(value) ((ISI_R2Y_SET1_C5_Msk & ((value) << ISI_R2Y_SET1_C5_Pos)))
179 #define ISI_R2Y_SET1_Goff (0x1u << 24)
180 /* -------- ISI_R2Y_SET2 : (ISI Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register -------- */
181 #define ISI_R2Y_SET2_C6_Pos 0
182 #define ISI_R2Y_SET2_C6_Msk (0x7fu << ISI_R2Y_SET2_C6_Pos)
183 #define ISI_R2Y_SET2_C6(value) ((ISI_R2Y_SET2_C6_Msk & ((value) << ISI_R2Y_SET2_C6_Pos)))
184 #define ISI_R2Y_SET2_C7_Pos 8
185 #define ISI_R2Y_SET2_C7_Msk (0x7fu << ISI_R2Y_SET2_C7_Pos)
186 #define ISI_R2Y_SET2_C7(value) ((ISI_R2Y_SET2_C7_Msk & ((value) << ISI_R2Y_SET2_C7_Pos)))
187 #define ISI_R2Y_SET2_C8_Pos 16
188 #define ISI_R2Y_SET2_C8_Msk (0x7fu << ISI_R2Y_SET2_C8_Pos)
189 #define ISI_R2Y_SET2_C8(value) ((ISI_R2Y_SET2_C8_Msk & ((value) << ISI_R2Y_SET2_C8_Pos)))
190 #define ISI_R2Y_SET2_Boff (0x1u << 24)
191 /* -------- ISI_CR : (ISI Offset: 0x24) ISI Control Register -------- */
192 #define ISI_CR_ISI_EN (0x1u << 0)
193 #define ISI_CR_ISI_DIS (0x1u << 1)
194 #define ISI_CR_ISI_SRST (0x1u << 2)
195 #define ISI_CR_ISI_CDC (0x1u << 8)
196 /* -------- ISI_SR : (ISI Offset: 0x28) ISI Status Register -------- */
197 #define ISI_SR_ENABLE (0x1u << 0)
198 #define ISI_SR_DIS_DONE (0x1u << 1)
199 #define ISI_SR_SRST (0x1u << 2)
200 #define ISI_SR_CDC_PND (0x1u << 8)
201 #define ISI_SR_VSYNC (0x1u << 10)
202 #define ISI_SR_PXFR_DONE (0x1u << 16)
203 #define ISI_SR_CXFR_DONE (0x1u << 17)
204 #define ISI_SR_SIP (0x1u << 19)
205 #define ISI_SR_P_OVR (0x1u << 24)
206 #define ISI_SR_C_OVR (0x1u << 25)
207 #define ISI_SR_CRC_ERR (0x1u << 26)
208 #define ISI_SR_FR_OVR (0x1u << 27)
209 /* -------- ISI_IER : (ISI Offset: 0x2C) ISI Interrupt Enable Register -------- */
210 #define ISI_IER_DIS_DONE (0x1u << 1)
211 #define ISI_IER_SRST (0x1u << 2)
212 #define ISI_IER_VSYNC (0x1u << 10)
213 #define ISI_IER_PXFR_DONE (0x1u << 16)
214 #define ISI_IER_CXFR_DONE (0x1u << 17)
215 #define ISI_IER_P_OVR (0x1u << 24)
216 #define ISI_IER_C_OVR (0x1u << 25)
217 #define ISI_IER_CRC_ERR (0x1u << 26)
218 #define ISI_IER_FR_OVR (0x1u << 27)
219 /* -------- ISI_IDR : (ISI Offset: 0x30) ISI Interrupt Disable Register -------- */
220 #define ISI_IDR_DIS_DONE (0x1u << 1)
221 #define ISI_IDR_SRST (0x1u << 2)
222 #define ISI_IDR_VSYNC (0x1u << 10)
223 #define ISI_IDR_PXFR_DONE (0x1u << 16)
224 #define ISI_IDR_CXFR_DONE (0x1u << 17)
225 #define ISI_IDR_P_OVR (0x1u << 24)
226 #define ISI_IDR_C_OVR (0x1u << 25)
227 #define ISI_IDR_CRC_ERR (0x1u << 26)
228 #define ISI_IDR_FR_OVR (0x1u << 27)
229 /* -------- ISI_IMR : (ISI Offset: 0x34) ISI Interrupt Mask Register -------- */
230 #define ISI_IMR_DIS_DONE (0x1u << 1)
231 #define ISI_IMR_SRST (0x1u << 2)
232 #define ISI_IMR_VSYNC (0x1u << 10)
233 #define ISI_IMR_PXFR_DONE (0x1u << 16)
234 #define ISI_IMR_CXFR_DONE (0x1u << 17)
235 #define ISI_IMR_P_OVR (0x1u << 24)
236 #define ISI_IMR_C_OVR (0x1u << 25)
237 #define ISI_IMR_CRC_ERR (0x1u << 26)
238 #define ISI_IMR_FR_OVR (0x1u << 27)
239 /* -------- ISI_DMA_CHER : (ISI Offset: 0x38) DMA Channel Enable Register -------- */
240 #define ISI_DMA_CHER_P_CH_EN (0x1u << 0)
241 #define ISI_DMA_CHER_C_CH_EN (0x1u << 1)
242 /* -------- ISI_DMA_CHDR : (ISI Offset: 0x3C) DMA Channel Disable Register -------- */
243 #define ISI_DMA_CHDR_P_CH_DIS (0x1u << 0)
244 #define ISI_DMA_CHDR_C_CH_DIS (0x1u << 1)
245 /* -------- ISI_DMA_CHSR : (ISI Offset: 0x40) DMA Channel Status Register -------- */
246 #define ISI_DMA_CHSR_P_CH_S (0x1u << 0)
247 #define ISI_DMA_CHSR_C_CH_S (0x1u << 1)
248 /* -------- ISI_DMA_P_ADDR : (ISI Offset: 0x44) DMA Preview Base Address Register -------- */
249 #define ISI_DMA_P_ADDR_P_ADDR_Pos 2
250 #define ISI_DMA_P_ADDR_P_ADDR_Msk (0x3fffffffu << ISI_DMA_P_ADDR_P_ADDR_Pos)
251 #define ISI_DMA_P_ADDR_P_ADDR(value) ((ISI_DMA_P_ADDR_P_ADDR_Msk & ((value) << ISI_DMA_P_ADDR_P_ADDR_Pos)))
252 /* -------- ISI_DMA_P_CTRL : (ISI Offset: 0x48) DMA Preview Control Register -------- */
253 #define ISI_DMA_P_CTRL_P_FETCH (0x1u << 0)
254 #define ISI_DMA_P_CTRL_P_WB (0x1u << 1)
255 #define ISI_DMA_P_CTRL_P_IEN (0x1u << 2)
256 #define ISI_DMA_P_CTRL_P_DONE (0x1u << 3)
257 /* -------- ISI_DMA_P_DSCR : (ISI Offset: 0x4C) DMA Preview Descriptor Address Register -------- */
258 #define ISI_DMA_P_DSCR_P_DSCR_Pos 2
259 #define ISI_DMA_P_DSCR_P_DSCR_Msk (0x3fffffffu << ISI_DMA_P_DSCR_P_DSCR_Pos)
260 #define ISI_DMA_P_DSCR_P_DSCR(value) ((ISI_DMA_P_DSCR_P_DSCR_Msk & ((value) << ISI_DMA_P_DSCR_P_DSCR_Pos)))
261 /* -------- ISI_DMA_C_ADDR : (ISI Offset: 0x50) DMA Codec Base Address Register -------- */
262 #define ISI_DMA_C_ADDR_C_ADDR_Pos 2
263 #define ISI_DMA_C_ADDR_C_ADDR_Msk (0x3fffffffu << ISI_DMA_C_ADDR_C_ADDR_Pos)
264 #define ISI_DMA_C_ADDR_C_ADDR(value) ((ISI_DMA_C_ADDR_C_ADDR_Msk & ((value) << ISI_DMA_C_ADDR_C_ADDR_Pos)))
265 /* -------- ISI_DMA_C_CTRL : (ISI Offset: 0x54) DMA Codec Control Register -------- */
266 #define ISI_DMA_C_CTRL_C_FETCH (0x1u << 0)
267 #define ISI_DMA_C_CTRL_C_WB (0x1u << 1)
268 #define ISI_DMA_C_CTRL_C_IEN (0x1u << 2)
269 #define ISI_DMA_C_CTRL_C_DONE (0x1u << 3)
270 /* -------- ISI_DMA_C_DSCR : (ISI Offset: 0x58) DMA Codec Descriptor Address Register -------- */
271 #define ISI_DMA_C_DSCR_C_DSCR_Pos 2
272 #define ISI_DMA_C_DSCR_C_DSCR_Msk (0x3fffffffu << ISI_DMA_C_DSCR_C_DSCR_Pos)
273 #define ISI_DMA_C_DSCR_C_DSCR(value) ((ISI_DMA_C_DSCR_C_DSCR_Msk & ((value) << ISI_DMA_C_DSCR_C_DSCR_Pos)))
274 /* -------- ISI_WPMR : (ISI Offset: 0xE4) Write Protection Mode Register -------- */
275 #define ISI_WPMR_WPEN (0x1u << 0)
276 #define ISI_WPMR_WPKEY_Pos 8
277 #define ISI_WPMR_WPKEY_Msk (0xffffffu << ISI_WPMR_WPKEY_Pos)
278 #define ISI_WPMR_WPKEY(value) ((ISI_WPMR_WPKEY_Msk & ((value) << ISI_WPMR_WPKEY_Pos)))
279 #define ISI_WPMR_WPKEY_PASSWD (0x495349u << 8)
280 /* -------- ISI_WPSR : (ISI Offset: 0xE8) Write Protection Status Register -------- */
281 #define ISI_WPSR_WPVS (0x1u << 0)
282 #define ISI_WPSR_WPVSRC_Pos 8
283 #define ISI_WPSR_WPVSRC_Msk (0xffffu << ISI_WPSR_WPVSRC_Pos)
284 /* -------- ISI_VERSION : (ISI Offset: 0xFC) Version Register -------- */
285 #define ISI_VERSION_VERSION_Pos 0
286 #define ISI_VERSION_VERSION_Msk (0xfffu << ISI_VERSION_VERSION_Pos)
287 #define ISI_VERSION_MFN_Pos 16
288 #define ISI_VERSION_MFN_Msk (0x7u << ISI_VERSION_MFN_Pos)
291 
292 
293 #endif /* _SAME70_ISI_COMPONENT_ */
__O uint32_t ISI_DMA_CHER
(Isi Offset: 0x38) DMA Channel Enable Register
Definition: component/isi.h:61
__IO uint32_t ISI_DMA_P_CTRL
(Isi Offset: 0x48) DMA Preview Control Register
Definition: component/isi.h:65
__IO uint32_t ISI_WPMR
(Isi Offset: 0xE4) Write Protection Mode Register
Definition: component/isi.h:71
__IO uint32_t ISI_PDECF
(Isi Offset: 0x0C) ISI Preview Decimation Factor Register
Definition: component/isi.h:50
#define __IO
Definition: core_cm7.h:266
__I uint32_t ISI_IMR
(Isi Offset: 0x34) ISI Interrupt Mask Register
Definition: component/isi.h:60
__I uint32_t ISI_VERSION
(Isi Offset: 0xFC) Version Register
Definition: component/isi.h:74
#define __O
Definition: core_cm7.h:265
__IO uint32_t ISI_DMA_C_DSCR
(Isi Offset: 0x58) DMA Codec Descriptor Address Register
Definition: component/isi.h:69
__IO uint32_t ISI_DMA_C_CTRL
(Isi Offset: 0x54) DMA Codec Control Register
Definition: component/isi.h:68
__IO uint32_t ISI_R2Y_SET2
(Isi Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register
Definition: component/isi.h:55
__IO uint32_t ISI_CFG2
(Isi Offset: 0x04) ISI Configuration 2 Register
Definition: component/isi.h:48
__I uint32_t ISI_DMA_CHSR
(Isi Offset: 0x40) DMA Channel Status Register
Definition: component/isi.h:63
__I uint32_t ISI_SR
(Isi Offset: 0x28) ISI Status Register
Definition: component/isi.h:57
__IO uint32_t ISI_PSIZE
(Isi Offset: 0x08) ISI Preview Size Register
Definition: component/isi.h:49
__IO uint32_t ISI_Y2R_SET0
(Isi Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register
Definition: component/isi.h:51
__O uint32_t ISI_DMA_CHDR
(Isi Offset: 0x3C) DMA Channel Disable Register
Definition: component/isi.h:62
__IO uint32_t ISI_Y2R_SET1
(Isi Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register
Definition: component/isi.h:52
__IO uint32_t ISI_R2Y_SET0
(Isi Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register
Definition: component/isi.h:53
__O uint32_t ISI_IDR
(Isi Offset: 0x30) ISI Interrupt Disable Register
Definition: component/isi.h:59
__O uint32_t ISI_CR
(Isi Offset: 0x24) ISI Control Register
Definition: component/isi.h:56
__IO uint32_t ISI_R2Y_SET1
(Isi Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register
Definition: component/isi.h:54
__IO uint32_t ISI_DMA_P_DSCR
(Isi Offset: 0x4C) DMA Preview Descriptor Address Register
Definition: component/isi.h:66
__O uint32_t ISI_IER
(Isi Offset: 0x2C) ISI Interrupt Enable Register
Definition: component/isi.h:58
__I uint32_t ISI_WPSR
(Isi Offset: 0xE8) Write Protection Status Register
Definition: component/isi.h:72
__IO uint32_t ISI_CFG1
(Isi Offset: 0x00) ISI Configuration 1 Register
Definition: component/isi.h:47
#define __I
Definition: core_cm7.h:263
__IO uint32_t ISI_DMA_C_ADDR
(Isi Offset: 0x50) DMA Codec Base Address Register
Definition: component/isi.h:67
__IO uint32_t ISI_DMA_P_ADDR
(Isi Offset: 0x44) DMA Preview Base Address Register
Definition: component/isi.h:64
Isi hardware registers.
Definition: component/isi.h:46


inertial_sense_ros
Author(s):
autogenerated on Sat Sep 19 2020 03:19:04