stm32f4xx_dma.c
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1 
123 /* Includes ------------------------------------------------------------------*/
124 #include "stm32f4xx_dma.h"
125 #include "stm32f4xx_rcc.h"
126 
136 /* Private typedef -----------------------------------------------------------*/
137 /* Private define ------------------------------------------------------------*/
138 
139 /* Masks Definition */
140 #define TRANSFER_IT_ENABLE_MASK (uint32_t)(DMA_SxCR_TCIE | DMA_SxCR_HTIE | \
141  DMA_SxCR_TEIE | DMA_SxCR_DMEIE)
142 
143 #define DMA_Stream0_IT_MASK (uint32_t)(DMA_LISR_FEIF0 | DMA_LISR_DMEIF0 | \
144  DMA_LISR_TEIF0 | DMA_LISR_HTIF0 | \
145  DMA_LISR_TCIF0)
146 
147 #define DMA_Stream1_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 6)
148 #define DMA_Stream2_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 16)
149 #define DMA_Stream3_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 22)
150 #define DMA_Stream4_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK | (uint32_t)0x20000000)
151 #define DMA_Stream5_IT_MASK (uint32_t)(DMA_Stream1_IT_MASK | (uint32_t)0x20000000)
152 #define DMA_Stream6_IT_MASK (uint32_t)(DMA_Stream2_IT_MASK | (uint32_t)0x20000000)
153 #define DMA_Stream7_IT_MASK (uint32_t)(DMA_Stream3_IT_MASK | (uint32_t)0x20000000)
154 #define TRANSFER_IT_MASK (uint32_t)0x0F3C0F3C
155 #define HIGH_ISR_MASK (uint32_t)0x20000000
156 #define RESERVED_MASK (uint32_t)0x0F7D0F7D
157 
158 /* Private macro -------------------------------------------------------------*/
159 /* Private variables ---------------------------------------------------------*/
160 /* Private function prototypes -----------------------------------------------*/
161 /* Private functions ---------------------------------------------------------*/
162 
163 
196 void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx)
197 {
198  /* Check the parameters */
199  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
200 
201  /* Disable the selected DMAy Streamx */
202  DMAy_Streamx->CR &= ~((uint32_t)DMA_SxCR_EN);
203 
204  /* Reset DMAy Streamx control register */
205  DMAy_Streamx->CR = 0;
206 
207  /* Reset DMAy Streamx Number of Data to Transfer register */
208  DMAy_Streamx->NDTR = 0;
209 
210  /* Reset DMAy Streamx peripheral address register */
211  DMAy_Streamx->PAR = 0;
212 
213  /* Reset DMAy Streamx memory 0 address register */
214  DMAy_Streamx->M0AR = 0;
215 
216  /* Reset DMAy Streamx memory 1 address register */
217  DMAy_Streamx->M1AR = 0;
218 
219  /* Reset DMAy Streamx FIFO control register */
220  DMAy_Streamx->FCR = (uint32_t)0x00000021;
221 
222  /* Reset interrupt pending bits for the selected stream */
223  if (DMAy_Streamx == DMA1_Stream0)
224  {
225  /* Reset interrupt pending bits for DMA1 Stream0 */
226  DMA1->LIFCR = DMA_Stream0_IT_MASK;
227  }
228  else if (DMAy_Streamx == DMA1_Stream1)
229  {
230  /* Reset interrupt pending bits for DMA1 Stream1 */
231  DMA1->LIFCR = DMA_Stream1_IT_MASK;
232  }
233  else if (DMAy_Streamx == DMA1_Stream2)
234  {
235  /* Reset interrupt pending bits for DMA1 Stream2 */
236  DMA1->LIFCR = DMA_Stream2_IT_MASK;
237  }
238  else if (DMAy_Streamx == DMA1_Stream3)
239  {
240  /* Reset interrupt pending bits for DMA1 Stream3 */
241  DMA1->LIFCR = DMA_Stream3_IT_MASK;
242  }
243  else if (DMAy_Streamx == DMA1_Stream4)
244  {
245  /* Reset interrupt pending bits for DMA1 Stream4 */
246  DMA1->HIFCR = DMA_Stream4_IT_MASK;
247  }
248  else if (DMAy_Streamx == DMA1_Stream5)
249  {
250  /* Reset interrupt pending bits for DMA1 Stream5 */
251  DMA1->HIFCR = DMA_Stream5_IT_MASK;
252  }
253  else if (DMAy_Streamx == DMA1_Stream6)
254  {
255  /* Reset interrupt pending bits for DMA1 Stream6 */
256  DMA1->HIFCR = (uint32_t)DMA_Stream6_IT_MASK;
257  }
258  else if (DMAy_Streamx == DMA1_Stream7)
259  {
260  /* Reset interrupt pending bits for DMA1 Stream7 */
261  DMA1->HIFCR = DMA_Stream7_IT_MASK;
262  }
263  else if (DMAy_Streamx == DMA2_Stream0)
264  {
265  /* Reset interrupt pending bits for DMA2 Stream0 */
266  DMA2->LIFCR = DMA_Stream0_IT_MASK;
267  }
268  else if (DMAy_Streamx == DMA2_Stream1)
269  {
270  /* Reset interrupt pending bits for DMA2 Stream1 */
271  DMA2->LIFCR = DMA_Stream1_IT_MASK;
272  }
273  else if (DMAy_Streamx == DMA2_Stream2)
274  {
275  /* Reset interrupt pending bits for DMA2 Stream2 */
276  DMA2->LIFCR = DMA_Stream2_IT_MASK;
277  }
278  else if (DMAy_Streamx == DMA2_Stream3)
279  {
280  /* Reset interrupt pending bits for DMA2 Stream3 */
281  DMA2->LIFCR = DMA_Stream3_IT_MASK;
282  }
283  else if (DMAy_Streamx == DMA2_Stream4)
284  {
285  /* Reset interrupt pending bits for DMA2 Stream4 */
286  DMA2->HIFCR = DMA_Stream4_IT_MASK;
287  }
288  else if (DMAy_Streamx == DMA2_Stream5)
289  {
290  /* Reset interrupt pending bits for DMA2 Stream5 */
291  DMA2->HIFCR = DMA_Stream5_IT_MASK;
292  }
293  else if (DMAy_Streamx == DMA2_Stream6)
294  {
295  /* Reset interrupt pending bits for DMA2 Stream6 */
296  DMA2->HIFCR = DMA_Stream6_IT_MASK;
297  }
298  else
299  {
300  if (DMAy_Streamx == DMA2_Stream7)
301  {
302  /* Reset interrupt pending bits for DMA2 Stream7 */
303  DMA2->HIFCR = DMA_Stream7_IT_MASK;
304  }
305  }
306 }
307 
319 void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct)
320 {
321  uint32_t tmpreg = 0;
322 
323  /* Check the parameters */
324  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
325  assert_param(IS_DMA_CHANNEL(DMA_InitStruct->DMA_Channel));
326  assert_param(IS_DMA_DIRECTION(DMA_InitStruct->DMA_DIR));
332  assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
333  assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
338 
339  /*------------------------- DMAy Streamx CR Configuration ------------------*/
340  /* Get the DMAy_Streamx CR value */
341  tmpreg = DMAy_Streamx->CR;
342 
343  /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
344  tmpreg &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
347  DMA_SxCR_DIR));
348 
349  /* Configure DMAy Streamx: */
350  /* Set CHSEL bits according to DMA_CHSEL value */
351  /* Set DIR bits according to DMA_DIR value */
352  /* Set PINC bit according to DMA_PeripheralInc value */
353  /* Set MINC bit according to DMA_MemoryInc value */
354  /* Set PSIZE bits according to DMA_PeripheralDataSize value */
355  /* Set MSIZE bits according to DMA_MemoryDataSize value */
356  /* Set CIRC bit according to DMA_Mode value */
357  /* Set PL bits according to DMA_Priority value */
358  /* Set MBURST bits according to DMA_MemoryBurst value */
359  /* Set PBURST bits according to DMA_PeripheralBurst value */
360  tmpreg |= DMA_InitStruct->DMA_Channel | DMA_InitStruct->DMA_DIR |
361  DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
362  DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
363  DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_Priority |
364  DMA_InitStruct->DMA_MemoryBurst | DMA_InitStruct->DMA_PeripheralBurst;
365 
366  /* Write to DMAy Streamx CR register */
367  DMAy_Streamx->CR = tmpreg;
368 
369  /*------------------------- DMAy Streamx FCR Configuration -----------------*/
370  /* Get the DMAy_Streamx FCR value */
371  tmpreg = DMAy_Streamx->FCR;
372 
373  /* Clear DMDIS and FTH bits */
374  tmpreg &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
375 
376  /* Configure DMAy Streamx FIFO:
377  Set DMDIS bits according to DMA_FIFOMode value
378  Set FTH bits according to DMA_FIFOThreshold value */
379  tmpreg |= DMA_InitStruct->DMA_FIFOMode | DMA_InitStruct->DMA_FIFOThreshold;
380 
381  /* Write to DMAy Streamx CR */
382  DMAy_Streamx->FCR = tmpreg;
383 
384  /*------------------------- DMAy Streamx NDTR Configuration ----------------*/
385  /* Write to DMAy Streamx NDTR register */
386  DMAy_Streamx->NDTR = DMA_InitStruct->DMA_BufferSize;
387 
388  /*------------------------- DMAy Streamx PAR Configuration -----------------*/
389  /* Write to DMAy Streamx PAR */
390  DMAy_Streamx->PAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
391 
392  /*------------------------- DMAy Streamx M0AR Configuration ----------------*/
393  /* Write to DMAy Streamx M0AR */
394  DMAy_Streamx->M0AR = DMA_InitStruct->DMA_Memory0BaseAddr;
395 }
396 
403 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
404 {
405  /*-------------- Reset DMA init structure parameters values ----------------*/
406  /* Initialize the DMA_Channel member */
407  DMA_InitStruct->DMA_Channel = 0;
408 
409  /* Initialize the DMA_PeripheralBaseAddr member */
410  DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
411 
412  /* Initialize the DMA_Memory0BaseAddr member */
413  DMA_InitStruct->DMA_Memory0BaseAddr = 0;
414 
415  /* Initialize the DMA_DIR member */
416  DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralToMemory;
417 
418  /* Initialize the DMA_BufferSize member */
419  DMA_InitStruct->DMA_BufferSize = 0;
420 
421  /* Initialize the DMA_PeripheralInc member */
423 
424  /* Initialize the DMA_MemoryInc member */
425  DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
426 
427  /* Initialize the DMA_PeripheralDataSize member */
429 
430  /* Initialize the DMA_MemoryDataSize member */
432 
433  /* Initialize the DMA_Mode member */
434  DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
435 
436  /* Initialize the DMA_Priority member */
437  DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
438 
439  /* Initialize the DMA_FIFOMode member */
440  DMA_InitStruct->DMA_FIFOMode = DMA_FIFOMode_Disable;
441 
442  /* Initialize the DMA_FIFOThreshold member */
444 
445  /* Initialize the DMA_MemoryBurst member */
446  DMA_InitStruct->DMA_MemoryBurst = DMA_MemoryBurst_Single;
447 
448  /* Initialize the DMA_PeripheralBurst member */
450 }
451 
478 void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState)
479 {
480  /* Check the parameters */
481  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
483 
484  if (NewState != DISABLE)
485  {
486  /* Enable the selected DMAy Streamx by setting EN bit */
487  DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_EN;
488  }
489  else
490  {
491  /* Disable the selected DMAy Streamx by clearing EN bit */
492  DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_EN;
493  }
494 }
495 
514 void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos)
515 {
516  /* Check the parameters */
517  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
518  assert_param(IS_DMA_PINCOS_SIZE(DMA_Pincos));
519 
520  /* Check the needed Peripheral increment offset */
521  if(DMA_Pincos != DMA_PINCOS_Psize)
522  {
523  /* Configure DMA_SxCR_PINCOS bit with the input parameter */
524  DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PINCOS;
525  }
526  else
527  {
528  /* Clear the PINCOS bit: Peripheral address incremented according to PSIZE */
529  DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PINCOS;
530  }
531 }
532 
550 void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl)
551 {
552  /* Check the parameters */
553  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
554  assert_param(IS_DMA_FLOW_CTRL(DMA_FlowCtrl));
555 
556  /* Check the needed flow controller */
557  if(DMA_FlowCtrl != DMA_FlowCtrl_Memory)
558  {
559  /* Configure DMA_SxCR_PFCTRL bit with the input parameter */
560  DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PFCTRL;
561  }
562  else
563  {
564  /* Clear the PFCTRL bit: Memory is the flow controller */
565  DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PFCTRL;
566  }
567 }
632 void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter)
633 {
634  /* Check the parameters */
635  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
636 
637  /* Write the number of data units to be transferred */
638  DMAy_Streamx->NDTR = (uint16_t)Counter;
639 }
640 
648 {
649  /* Check the parameters */
650  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
651 
652  /* Return the number of remaining data units for DMAy Streamx */
653  return ((uint16_t)(DMAy_Streamx->NDTR));
654 }
730 void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
731  uint32_t DMA_CurrentMemory)
732 {
733  /* Check the parameters */
734  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
735  assert_param(IS_DMA_CURRENT_MEM(DMA_CurrentMemory));
736 
737  if (DMA_CurrentMemory != DMA_Memory_0)
738  {
739  /* Set Memory 1 as current memory address */
740  DMAy_Streamx->CR |= (uint32_t)(DMA_SxCR_CT);
741  }
742  else
743  {
744  /* Set Memory 0 as current memory address */
745  DMAy_Streamx->CR &= ~(uint32_t)(DMA_SxCR_CT);
746  }
747 
748  /* Write to DMAy Streamx M1AR */
749  DMAy_Streamx->M1AR = Memory1BaseAddr;
750 }
751 
762 {
763  /* Check the parameters */
764  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
766 
767  /* Configure the Double Buffer mode */
768  if (NewState != DISABLE)
769  {
770  /* Enable the Double buffer mode */
771  DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_DBM;
772  }
773  else
774  {
775  /* Disable the Double buffer mode */
776  DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_DBM;
777  }
778 }
779 
802 void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
803  uint32_t DMA_MemoryTarget)
804 {
805  /* Check the parameters */
806  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
807  assert_param(IS_DMA_CURRENT_MEM(DMA_MemoryTarget));
808 
809  /* Check the Memory target to be configured */
810  if (DMA_MemoryTarget != DMA_Memory_0)
811  {
812  /* Write to DMAy Streamx M1AR */
813  DMAy_Streamx->M1AR = MemoryBaseAddr;
814  }
815  else
816  {
817  /* Write to DMAy Streamx M0AR */
818  DMAy_Streamx->M0AR = MemoryBaseAddr;
819  }
820 }
821 
829 {
830  uint32_t tmp = 0;
831 
832  /* Check the parameters */
833  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
834 
835  /* Get the current memory target */
836  if ((DMAy_Streamx->CR & DMA_SxCR_CT) != 0)
837  {
838  /* Current memory buffer used is Memory 1 */
839  tmp = 1;
840  }
841  else
842  {
843  /* Current memory buffer used is Memory 0 */
844  tmp = 0;
845  }
846  return tmp;
847 }
944 {
945  FunctionalState state = DISABLE;
946 
947  /* Check the parameters */
948  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
949 
950  if ((DMAy_Streamx->CR & (uint32_t)DMA_SxCR_EN) != 0)
951  {
952  /* The selected DMAy Streamx EN bit is set (DMA is still transferring) */
953  state = ENABLE;
954  }
955  else
956  {
957  /* The selected DMAy Streamx EN bit is cleared (DMA is disabled and
958  all transfers are complete) */
959  state = DISABLE;
960  }
961  return state;
962 }
963 
977 uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx)
978 {
979  uint32_t tmpreg = 0;
980 
981  /* Check the parameters */
982  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
983 
984  /* Get the FIFO level bits */
985  tmpreg = (uint32_t)((DMAy_Streamx->FCR & DMA_SxFCR_FS));
986 
987  return tmpreg;
988 }
989 
1004 FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG)
1005 {
1006  FlagStatus bitstatus = RESET;
1007  DMA_TypeDef* DMAy;
1008  uint32_t tmpreg = 0;
1009 
1010  /* Check the parameters */
1011  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
1012  assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
1013 
1014  /* Determine the DMA to which belongs the stream */
1015  if (DMAy_Streamx < DMA2_Stream0)
1016  {
1017  /* DMAy_Streamx belongs to DMA1 */
1018  DMAy = DMA1;
1019  }
1020  else
1021  {
1022  /* DMAy_Streamx belongs to DMA2 */
1023  DMAy = DMA2;
1024  }
1025 
1026  /* Check if the flag is in HISR or LISR */
1027  if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
1028  {
1029  /* Get DMAy HISR register value */
1030  tmpreg = DMAy->HISR;
1031  }
1032  else
1033  {
1034  /* Get DMAy LISR register value */
1035  tmpreg = DMAy->LISR;
1036  }
1037 
1038  /* Mask the reserved bits */
1039  tmpreg &= (uint32_t)RESERVED_MASK;
1040 
1041  /* Check the status of the specified DMA flag */
1042  if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
1043  {
1044  /* DMA_FLAG is set */
1045  bitstatus = SET;
1046  }
1047  else
1048  {
1049  /* DMA_FLAG is reset */
1050  bitstatus = RESET;
1051  }
1052 
1053  /* Return the DMA_FLAG status */
1054  return bitstatus;
1055 }
1056 
1071 void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG)
1072 {
1073  DMA_TypeDef* DMAy;
1074 
1075  /* Check the parameters */
1076  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
1077  assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
1078 
1079  /* Determine the DMA to which belongs the stream */
1080  if (DMAy_Streamx < DMA2_Stream0)
1081  {
1082  /* DMAy_Streamx belongs to DMA1 */
1083  DMAy = DMA1;
1084  }
1085  else
1086  {
1087  /* DMAy_Streamx belongs to DMA2 */
1088  DMAy = DMA2;
1089  }
1090 
1091  /* Check if LIFCR or HIFCR register is targeted */
1092  if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
1093  {
1094  /* Set DMAy HIFCR register clear flag bits */
1095  DMAy->HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
1096  }
1097  else
1098  {
1099  /* Set DMAy LIFCR register clear flag bits */
1100  DMAy->LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
1101  }
1102 }
1103 
1118 void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState)
1119 {
1120  /* Check the parameters */
1121  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
1122  assert_param(IS_DMA_CONFIG_IT(DMA_IT));
1123  assert_param(IS_FUNCTIONAL_STATE(NewState));
1124 
1125  /* Check if the DMA_IT parameter contains a FIFO interrupt */
1126  if ((DMA_IT & DMA_IT_FE) != 0)
1127  {
1128  if (NewState != DISABLE)
1129  {
1130  /* Enable the selected DMA FIFO interrupts */
1131  DMAy_Streamx->FCR |= (uint32_t)DMA_IT_FE;
1132  }
1133  else
1134  {
1135  /* Disable the selected DMA FIFO interrupts */
1136  DMAy_Streamx->FCR &= ~(uint32_t)DMA_IT_FE;
1137  }
1138  }
1139 
1140  /* Check if the DMA_IT parameter contains a Transfer interrupt */
1141  if (DMA_IT != DMA_IT_FE)
1142  {
1143  if (NewState != DISABLE)
1144  {
1145  /* Enable the selected DMA transfer interrupts */
1146  DMAy_Streamx->CR |= (uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK);
1147  }
1148  else
1149  {
1150  /* Disable the selected DMA transfer interrupts */
1151  DMAy_Streamx->CR &= ~(uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK);
1152  }
1153  }
1154 }
1155 
1170 ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT)
1171 {
1172  ITStatus bitstatus = RESET;
1173  DMA_TypeDef* DMAy;
1174  uint32_t tmpreg = 0, enablestatus = 0;
1175 
1176  /* Check the parameters */
1177  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
1178  assert_param(IS_DMA_GET_IT(DMA_IT));
1179 
1180  /* Determine the DMA to which belongs the stream */
1181  if (DMAy_Streamx < DMA2_Stream0)
1182  {
1183  /* DMAy_Streamx belongs to DMA1 */
1184  DMAy = DMA1;
1185  }
1186  else
1187  {
1188  /* DMAy_Streamx belongs to DMA2 */
1189  DMAy = DMA2;
1190  }
1191 
1192  /* Check if the interrupt enable bit is in the CR or FCR register */
1193  if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET)
1194  {
1195  /* Get the interrupt enable position mask in CR register */
1196  tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK);
1197 
1198  /* Check the enable bit in CR register */
1199  enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg);
1200  }
1201  else
1202  {
1203  /* Check the enable bit in FCR register */
1204  enablestatus = (uint32_t)(DMAy_Streamx->FCR & DMA_IT_FE);
1205  }
1206 
1207  /* Check if the interrupt pending flag is in LISR or HISR */
1208  if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)
1209  {
1210  /* Get DMAy HISR register value */
1211  tmpreg = DMAy->HISR ;
1212  }
1213  else
1214  {
1215  /* Get DMAy LISR register value */
1216  tmpreg = DMAy->LISR ;
1217  }
1218 
1219  /* mask all reserved bits */
1220  tmpreg &= (uint32_t)RESERVED_MASK;
1221 
1222  /* Check the status of the specified DMA interrupt */
1223  if (((tmpreg & DMA_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
1224  {
1225  /* DMA_IT is set */
1226  bitstatus = SET;
1227  }
1228  else
1229  {
1230  /* DMA_IT is reset */
1231  bitstatus = RESET;
1232  }
1233 
1234  /* Return the DMA_IT status */
1235  return bitstatus;
1236 }
1237 
1252 void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT)
1253 {
1254  DMA_TypeDef* DMAy;
1255 
1256  /* Check the parameters */
1257  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
1258  assert_param(IS_DMA_CLEAR_IT(DMA_IT));
1259 
1260  /* Determine the DMA to which belongs the stream */
1261  if (DMAy_Streamx < DMA2_Stream0)
1262  {
1263  /* DMAy_Streamx belongs to DMA1 */
1264  DMAy = DMA1;
1265  }
1266  else
1267  {
1268  /* DMAy_Streamx belongs to DMA2 */
1269  DMAy = DMA2;
1270  }
1271 
1272  /* Check if LIFCR or HIFCR register is targeted */
1273  if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)
1274  {
1275  /* Set DMAy HIFCR register clear interrupt bits */
1276  DMAy->HIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);
1277  }
1278  else
1279  {
1280  /* Set DMAy LIFCR register clear interrupt bits */
1281  DMAy->LIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);
1282  }
1283 }
1284 
1301 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
uint32_t DMA_MemoryInc
Definition: stm32f4xx_dma.h:76
FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef *DMAy_Streamx)
Returns the status of EN bit for the specified DMAy Streamx.
FlagStatus
Definition: stm32f4xx.h:706
#define DMA_Priority_Low
uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef *DMAy_Streamx)
Returns the current DMAy Streamx FIFO filled level.
#define TRANSFER_IT_MASK
uint32_t DMA_Channel
Definition: stm32f4xx_dma.h:56
#define DMA1_Stream6
Definition: stm32f4xx.h:2131
#define DMA1_Stream5
Definition: stm32f4xx.h:2130
ITStatus DMA_GetITStatus(DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_IT)
Checks whether the specified DMAy Streamx interrupt has occurred or not.
#define DMA_Stream3_IT_MASK
__IO uint32_t M1AR
Definition: stm32f4xx.h:913
FunctionalState
Definition: stm32f4xx.h:708
#define IS_DMA_FIFO_THRESHOLD(THRESHOLD)
DMA Init structure definition.
Definition: stm32f4xx_dma.h:54
#define DMA_SxCR_CHSEL
Definition: stm32f4xx.h:4081
#define DMA_Stream2_IT_MASK
#define DMA_SxCR_PINCOS
Definition: stm32f4xx.h:4097
#define DMA_MemoryDataSize_Byte
uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef *DMAy_Streamx)
Returns the number of remaining data units in the current DMAy Streamx transfer.
void DMA_ClearFlag(DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_FLAG)
Clears the DMAy Streamx&#39;s pending flags.
void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_Pincos)
Configures, when the PINC (Peripheral Increment address mode) bit is set, if the peripheral address s...
#define DMA_SxCR_CT
Definition: stm32f4xx.h:4092
uint32_t DMA_MemoryBurst
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define DMA_PeripheralInc_Disable
#define DMA_FlowCtrl_Memory
#define DMA1_Stream3
Definition: stm32f4xx.h:2128
uint32_t DMA_MemoryDataSize
Definition: stm32f4xx_dma.h:82
DMA Controller.
Definition: stm32f4xx.h:907
#define DMA_SxCR_MBURST
Definition: stm32f4xx.h:4085
#define IS_DMA_PERIPHERAL_INC_STATE(STATE)
#define DMA2_Stream4
Definition: stm32f4xx.h:2138
void assert_param(int val)
#define IS_DMA_MEMORY_INC_STATE(STATE)
uint32_t DMA_DIR
Definition: stm32f4xx_dma.h:65
__IO uint32_t PAR
Definition: stm32f4xx.h:911
#define DMA_Stream4_IT_MASK
#define DMA_SxCR_PL
Definition: stm32f4xx.h:4094
#define RESERVED_MASK
uint32_t DMA_PeripheralInc
Definition: stm32f4xx_dma.h:73
#define DMA_SxCR_DBM
Definition: stm32f4xx.h:4093
#define DMA_Memory_0
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
#define HIGH_ISR_MASK
void DMA_Init(DMA_Stream_TypeDef *DMAy_Streamx, DMA_InitTypeDef *DMA_InitStruct)
Initializes the DMAy Streamx according to the specified parameters in the DMA_InitStruct structure...
void DMA_DeInit(DMA_Stream_TypeDef *DMAy_Streamx)
Deinitialize the DMAy Streamx registers to their default reset values.
uint32_t DMA_PeripheralDataSize
Definition: stm32f4xx_dma.h:79
#define DMA_Stream6_IT_MASK
#define DMA2_Stream3
Definition: stm32f4xx.h:2137
Definition: stm32f4xx.h:706
#define DMA_Stream1_IT_MASK
void DMA_SetCurrDataCounter(DMA_Stream_TypeDef *DMAy_Streamx, uint16_t Counter)
Writes the number of data units to be transferred on the DMAy Streamx.
enum FlagStatus ITStatus
#define DMA2_Stream6
Definition: stm32f4xx.h:2140
#define IS_DMA_GET_IT(IT)
#define DMA1_Stream0
Definition: stm32f4xx.h:2125
#define DMA_IT_FE
#define DMA1_Stream1
Definition: stm32f4xx.h:2126
#define IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define DMA_SxCR_PINC
Definition: stm32f4xx.h:4105
#define DMA_SxFCR_DMDIS
Definition: stm32f4xx.h:4142
#define IS_DMA_PERIPHERAL_BURST(BURST)
uint32_t DMA_PeripheralBurst
#define DMA_SxCR_PBURST
Definition: stm32f4xx.h:4088
#define DMA_SxCR_PSIZE
Definition: stm32f4xx.h:4101
__IO uint32_t HISR
Definition: stm32f4xx.h:920
#define DMA_SxCR_EN
Definition: stm32f4xx.h:4115
This file contains all the functions prototypes for the DMA firmware library.
#define DMA_FIFOThreshold_1QuarterFull
#define DMA2_Stream7
Definition: stm32f4xx.h:2141
uint32_t DMA_PeripheralBaseAddr
Definition: stm32f4xx_dma.h:59
uint32_t DMA_Memory0BaseAddr
Definition: stm32f4xx_dma.h:61
#define DMA_Stream0_IT_MASK
#define DMA_SxCR_DIR
Definition: stm32f4xx.h:4107
void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef *DMAy_Streamx, uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory)
Configures, when the DMAy Streamx is disabled, the double buffer mode and the current memory target...
__IO uint32_t CR
Definition: stm32f4xx.h:909
__IO uint32_t HIFCR
Definition: stm32f4xx.h:922
#define DMA_MemoryBurst_Single
#define DMA_Stream5_IT_MASK
uint32_t DMA_FIFOThreshold
Definition: stm32f4xx_dma.h:98
#define DMA_SxCR_CIRC
Definition: stm32f4xx.h:4106
__IO uint32_t M0AR
Definition: stm32f4xx.h:912
#define IS_DMA_BUFFER_SIZE(SIZE)
void DMA_MemoryTargetConfig(DMA_Stream_TypeDef *DMAy_Streamx, uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget)
Configures the Memory address for the next buffer transfer in double buffer mode (for dynamic use)...
#define DMA2_Stream2
Definition: stm32f4xx.h:2136
#define DMA2_Stream5
Definition: stm32f4xx.h:2139
#define DMA_Mode_Normal
void DMA_ITConfig(DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState)
Enables or disables the specified DMAy Streamx interrupts.
#define IS_DMA_CURRENT_MEM(MEM)
#define DMA1_Stream2
Definition: stm32f4xx.h:2127
#define DMA_SxCR_PFCTRL
Definition: stm32f4xx.h:4110
#define DMA_FIFOMode_Disable
#define IS_DMA_PINCOS_SIZE(SIZE)
#define IS_DMA_MODE(MODE)
#define IS_DMA_ALL_PERIPH(PERIPH)
uint32_t DMA_FIFOMode
Definition: stm32f4xx_dma.h:93
#define DMA_PeripheralDataSize_Byte
#define IS_DMA_FLOW_CTRL(CTRL)
#define DMA1_Stream4
Definition: stm32f4xx.h:2129
#define DMA_PINCOS_Psize
#define IS_DMA_CLEAR_FLAG(FLAG)
__IO uint32_t NDTR
Definition: stm32f4xx.h:910
#define IS_DMA_CONFIG_IT(IT)
__IO uint32_t FCR
Definition: stm32f4xx.h:914
#define IS_DMA_MEMORY_BURST(BURST)
#define IS_DMA_CHANNEL(CHANNEL)
#define DMA_MemoryInc_Disable
uint32_t DMA_Mode
Definition: stm32f4xx_dma.h:85
#define IS_DMA_CLEAR_IT(IT)
#define DMA2_Stream1
Definition: stm32f4xx.h:2135
#define DMA1
Definition: stm32f4xx.h:2124
void DMA_ClearITPendingBit(DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_IT)
Clears the DMAy Streamx&#39;s interrupt pending bits.
#define IS_DMA_DIRECTION(DIRECTION)
#define DMA_DIR_PeripheralToMemory
uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef *DMAy_Streamx)
Returns the current memory target used by double buffer transfer.
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct)
Fills each DMA_InitStruct member with its default value.
__IO uint32_t LIFCR
Definition: stm32f4xx.h:921
#define DMA_SxCR_MINC
Definition: stm32f4xx.h:4104
uint32_t DMA_BufferSize
Definition: stm32f4xx_dma.h:69
#define DMA_SxCR_MSIZE
Definition: stm32f4xx.h:4098
__IO uint32_t LISR
Definition: stm32f4xx.h:919
uint32_t DMA_Priority
Definition: stm32f4xx_dma.h:90
#define IS_DMA_PRIORITY(PRIORITY)
void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef *DMAy_Streamx, FunctionalState NewState)
Enables or disables the double buffer mode for the selected DMA stream.
#define DMA_SxFCR_FS
Definition: stm32f4xx.h:4138
#define DMA_SxFCR_FTH
Definition: stm32f4xx.h:4143
#define DMA_Stream7_IT_MASK
void DMA_Cmd(DMA_Stream_TypeDef *DMAy_Streamx, FunctionalState NewState)
Enables or disables the specified DMAy Streamx.
#define IS_DMA_GET_FLAG(FLAG)
#define TRANSFER_IT_ENABLE_MASK
FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_FLAG)
Checks whether the specified DMAy Streamx flag is set or not.
void DMA_FlowControllerConfig(DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_FlowCtrl)
Configures, when the DMAy Streamx is disabled, the flow controller for the next transactions (Periphe...
#define DMA2
Definition: stm32f4xx.h:2133
#define DMA1_Stream7
Definition: stm32f4xx.h:2132
#define DMA2_Stream0
Definition: stm32f4xx.h:2134
#define IS_DMA_FIFO_MODE_STATE(STATE)
#define DMA_PeripheralBurst_Single


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19