stm32f10x_fsmc.h
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1 
23 /* Define to prevent recursive inclusion -------------------------------------*/
24 #ifndef __STM32F10x_FSMC_H
25 #define __STM32F10x_FSMC_H
26 
27 #ifdef __cplusplus
28  extern "C" {
29 #endif
30 
31 /* Includes ------------------------------------------------------------------*/
32 #include "stm32f10x.h"
33 
50 typedef struct
51 {
52  uint32_t FSMC_AddressSetupTime;
57  uint32_t FSMC_AddressHoldTime;
62  uint32_t FSMC_DataSetupTime;
67  uint32_t FSMC_BusTurnAroundDuration;
72  uint32_t FSMC_CLKDivision;
76  uint32_t FSMC_DataLatency;
84  uint32_t FSMC_AccessMode;
87 
92 typedef struct
93 {
94  uint32_t FSMC_Bank;
97  uint32_t FSMC_DataAddressMux;
101  uint32_t FSMC_MemoryType;
105  uint32_t FSMC_MemoryDataWidth;
108  uint32_t FSMC_BurstAccessMode;
112  uint32_t FSMC_AsynchronousWait;
116  uint32_t FSMC_WaitSignalPolarity;
120  uint32_t FSMC_WrapMode;
124  uint32_t FSMC_WaitSignalActive;
129  uint32_t FSMC_WriteOperation;
132  uint32_t FSMC_WaitSignal;
136  uint32_t FSMC_ExtendedMode;
139  uint32_t FSMC_WriteBurst;
142  FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct;
144  FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;
146 
151 typedef struct
152 {
153  uint32_t FSMC_SetupTime;
159  uint32_t FSMC_WaitSetupTime;
165  uint32_t FSMC_HoldSetupTime;
172  uint32_t FSMC_HiZSetupTime;
178 
183 typedef struct
184 {
185  uint32_t FSMC_Bank;
188  uint32_t FSMC_Waitfeature;
191  uint32_t FSMC_MemoryDataWidth;
194  uint32_t FSMC_ECC;
197  uint32_t FSMC_ECCPageSize;
200  uint32_t FSMC_TCLRSetupTime;
204  uint32_t FSMC_TARSetupTime;
208  FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;
210  FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct;
212 
217 typedef struct
218 {
219  uint32_t FSMC_Waitfeature;
222  uint32_t FSMC_TCLRSetupTime;
226  uint32_t FSMC_TARSetupTime;
231  FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;
233  FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct;
235  FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct;
237 
249 #define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
250 #define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
251 #define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
252 #define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
253 
260 #define FSMC_Bank2_NAND ((uint32_t)0x00000010)
261 #define FSMC_Bank3_NAND ((uint32_t)0x00000100)
262 
269 #define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
270 
274 #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
275  ((BANK) == FSMC_Bank1_NORSRAM2) || \
276  ((BANK) == FSMC_Bank1_NORSRAM3) || \
277  ((BANK) == FSMC_Bank1_NORSRAM4))
278 
279 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
280  ((BANK) == FSMC_Bank3_NAND))
281 
282 #define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
283  ((BANK) == FSMC_Bank3_NAND) || \
284  ((BANK) == FSMC_Bank4_PCCARD))
285 
286 #define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
287  ((BANK) == FSMC_Bank3_NAND) || \
288  ((BANK) == FSMC_Bank4_PCCARD))
289 
298 #define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
299 #define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
300 #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
301  ((MUX) == FSMC_DataAddressMux_Enable))
302 
311 #define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
312 #define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
313 #define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
314 #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
315  ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
316  ((MEMORY) == FSMC_MemoryType_NOR))
317 
326 #define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
327 #define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
328 #define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
329  ((WIDTH) == FSMC_MemoryDataWidth_16b))
330 
339 #define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
340 #define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
341 #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
342  ((STATE) == FSMC_BurstAccessMode_Enable))
343 
350 #define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
351 #define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
352 #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
353  ((STATE) == FSMC_AsynchronousWait_Enable))
354 
363 #define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
364 #define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
365 #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
366  ((POLARITY) == FSMC_WaitSignalPolarity_High))
367 
376 #define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
377 #define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
378 #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
379  ((MODE) == FSMC_WrapMode_Enable))
380 
389 #define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
390 #define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
391 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
392  ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
393 
402 #define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
403 #define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
404 #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
405  ((OPERATION) == FSMC_WriteOperation_Enable))
406 
415 #define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
416 #define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
417 #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
418  ((SIGNAL) == FSMC_WaitSignal_Enable))
419 
427 #define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
428 #define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
429 
430 #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
431  ((MODE) == FSMC_ExtendedMode_Enable))
432 
441 #define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
442 #define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
443 #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
444  ((BURST) == FSMC_WriteBurst_Enable))
445 
453 #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
454 
463 #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
464 
473 #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
474 
483 #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
484 
493 #define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
494 
503 #define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
504 
513 #define FSMC_AccessMode_A ((uint32_t)0x00000000)
514 #define FSMC_AccessMode_B ((uint32_t)0x10000000)
515 #define FSMC_AccessMode_C ((uint32_t)0x20000000)
516 #define FSMC_AccessMode_D ((uint32_t)0x30000000)
517 #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
518  ((MODE) == FSMC_AccessMode_B) || \
519  ((MODE) == FSMC_AccessMode_C) || \
520  ((MODE) == FSMC_AccessMode_D))
521 
538 #define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
539 #define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
540 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
541  ((FEATURE) == FSMC_Waitfeature_Enable))
542 
552 #define FSMC_ECC_Disable ((uint32_t)0x00000000)
553 #define FSMC_ECC_Enable ((uint32_t)0x00000040)
554 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
555  ((STATE) == FSMC_ECC_Enable))
556 
565 #define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
566 #define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
567 #define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
568 #define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
569 #define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
570 #define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
571 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
572  ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
573  ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
574  ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
575  ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
576  ((SIZE) == FSMC_ECCPageSize_8192Bytes))
577 
586 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
587 
596 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
597 
606 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
607 
616 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
617 
626 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
627 
636 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
637 
646 #define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
647 #define FSMC_IT_Level ((uint32_t)0x00000010)
648 #define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
649 #define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
650 #define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
651  ((IT) == FSMC_IT_Level) || \
652  ((IT) == FSMC_IT_FallingEdge))
653 
661 #define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
662 #define FSMC_FLAG_Level ((uint32_t)0x00000002)
663 #define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
664 #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
665 #define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
666  ((FLAG) == FSMC_FLAG_Level) || \
667  ((FLAG) == FSMC_FLAG_FallingEdge) || \
668  ((FLAG) == FSMC_FLAG_FEMPT))
669 
670 #define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
671 
696 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
697 void FSMC_NANDDeInit(uint32_t FSMC_Bank);
698 void FSMC_PCCARDDeInit(void);
699 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
700 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
701 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
702 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
703 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
704 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
705 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
706 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
707 void FSMC_PCCARDCmd(FunctionalState NewState);
708 void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
709 uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
710 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
711 FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
712 void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
713 ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
714 void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
715 
716 #ifdef __cplusplus
717 }
718 #endif
719 
720 #endif /*__STM32F10x_FSMC_H */
721 
733 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
FlagStatus
Definition: stm32f4xx.h:706
void FSMC_PCCARDDeInit(void)
De-initializes the FSMC PCCARD Bank registers to their default reset values.
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Fills each FSMC_NORSRAMInitStruct member with its default value.
FunctionalState
Definition: stm32f4xx.h:708
void FSMC_NANDInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
Initializes the FSMC NAND Banks according to the specified parameters in the FSMC_NANDInitStruct.
Timing parameters For NOR/SRAM Banks.
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the FSMC NAND ECC feature.
FSMC NOR/SRAM Init structure definition.
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
Initializes the FSMC PCCARD Bank according to the specified parameters in the FSMC_PCCARDInitStruct.
void FSMC_PCCARDCmd(FunctionalState NewState)
Enables or disables the PCCARD Memory Bank.
FSMC NAND Init structure definition.
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the specified NOR/SRAM Memory Bank.
Timing parameters For FSMC NAND and PCCARD Banks.
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
Clears the FSMC&#39;s interrupt pending bits.
enum FlagStatus ITStatus
FSMC PCCARD Init structure definition.
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
Enables or disables the specified FSMC interrupts.
void FSMC_NANDDeInit(uint32_t FSMC_Bank)
De-initializes the FSMC NAND Banks registers to their default reset values.
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
Fills each FSMC_NANDInitStruct member with its default value.
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
Checks whether the specified FSMC interrupt has occurred or not.
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
Checks whether the specified FSMC flag is set or not.
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
Fills each FSMC_PCCARDInitStruct member with its default value.
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the specified NAND Memory Bank.
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Initializes the FSMC NOR/SRAM Banks according to the specified parameters in the FSMC_NORSRAMInitStru...
CMSIS Cortex-M3 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
Returns the error correction code register value.
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
De-initializes the FSMC NOR/SRAM Banks registers to their default reset values.
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
Clears the FSMC&#39;s pending flags.


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19