SPI Configuration Structure definition. More...

#include <stm32f4xx_hal_spi.h>

Public Attributes
uint32_t	BaudRatePrescaler

uint32_t	CLKPhase

uint32_t	CLKPolarity

uint32_t	CRCCalculation

uint32_t	CRCLength

uint32_t	CRCPolynomial

uint32_t	DataSize

uint32_t	Direction

uint32_t	FifoThreshold

uint32_t	FirstBit

uint32_t	IOSwap

uint32_t	MasterInterDataIdleness

uint32_t	MasterKeepIOState

uint32_t	MasterReceiverAutoSusp

uint32_t	MasterSSIdleness

uint32_t	Mode

uint32_t	NSS

uint32_t	NSSPMode

uint32_t	NSSPolarity

uint32_t	RxCRCInitializationPattern

uint32_t	TIMode

uint32_t	TxCRCInitializationPattern

Detailed Description

SPI Configuration Structure definition.

Definition at line 47 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h.

Member Data Documentation

◆ BaudRatePrescaler

uint32_t SPI_InitTypeDef::BaudRatePrescaler

Specifies the Baud Rate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of SPI BaudRate Prescaler

Note: The communication clock is derived from the master clock. The slave clock does not need to be set.

Definition at line 68 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h.

◆ CLKPhase

uint32_t SPI_InitTypeDef::CLKPhase

Specifies the clock active edge for the bit capture. This parameter can be a value of SPI Clock Phase

Definition at line 61 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h.

◆ CLKPolarity

uint32_t SPI_InitTypeDef::CLKPolarity

Specifies the serial clock steady state. This parameter can be a value of SPI Clock Polarity

Definition at line 58 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h.

◆ CRCCalculation

uint32_t SPI_InitTypeDef::CRCCalculation

Specifies if the CRC calculation is enabled or not. This parameter can be a value of SPI CRC Calculation

Definition at line 80 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h.

◆ CRCLength

uint32_t SPI_InitTypeDef::CRCLength

Specifies the CRC Length used for the CRC calculation. CRC Length is only used with Data8 and Data16, not other data size This parameter can be a value of SPI CRC Length

Specifies the CRC Length used for the CRC calculation. This parameter can be a value of SPI CRC Length

Definition at line 86 of file stm32f7xx_hal_spi.h.

◆ CRCPolynomial

uint32_t SPI_InitTypeDef::CRCPolynomial

Specifies the polynomial used for the CRC calculation. This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535

Specifies the polynomial used for the CRC calculation. This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535

Definition at line 83 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h.

◆ DataSize

uint32_t SPI_InitTypeDef::DataSize

Specifies the SPI data size. This parameter can be a value of SPI Data Size

Definition at line 55 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h.

◆ Direction

uint32_t SPI_InitTypeDef::Direction

Specifies the SPI bidirectional mode state. This parameter can be a value of SPI Direction Mode

Definition at line 52 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h.

◆ FifoThreshold

uint32_t SPI_InitTypeDef::FifoThreshold

Specifies the FIFO threshold level. This parameter can be a value of SPI Fifo Threshold

Definition at line 99 of file stm32h7xx_hal_spi.h.

◆ FirstBit

uint32_t SPI_InitTypeDef::FirstBit

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of SPI MSB LSB Transmission

Definition at line 74 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h.

◆ IOSwap

uint32_t SPI_InitTypeDef::IOSwap

Invert MISO/MOSI alternate functions This parameter can be a value of Control SPI IO Swap

Definition at line 123 of file stm32h7xx_hal_spi.h.

◆ MasterInterDataIdleness

uint32_t SPI_InitTypeDef::MasterInterDataIdleness

Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between two consecutive data frames in master mode This parameter can be a value of SPI Master Inter-Data Idleness

Definition at line 112 of file stm32h7xx_hal_spi.h.

◆ MasterKeepIOState

uint32_t SPI_InitTypeDef::MasterKeepIOState

Control of Alternate function GPIOs state This parameter can be a value of Keep IO State

Definition at line 120 of file stm32h7xx_hal_spi.h.

◆ MasterReceiverAutoSusp

uint32_t SPI_InitTypeDef::MasterReceiverAutoSusp

Control continuous SPI transfer in master receiver mode and automatic management in order to avoid overrun condition. This parameter can be a value of SPI Master Receiver AutoSuspend

Definition at line 116 of file stm32h7xx_hal_spi.h.

◆ MasterSSIdleness

uint32_t SPI_InitTypeDef::MasterSSIdleness

Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted additionally between active edge of SS and first data transaction start in master mode. This parameter can be a value of SPI Master SS Idleness

Definition at line 108 of file stm32h7xx_hal_spi.h.

◆ Mode

uint32_t SPI_InitTypeDef::Mode

Specifies the SPI operating mode. This parameter can be a value of SPI Mode

Definition at line 49 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h.

◆ NSS

uint32_t SPI_InitTypeDef::NSS

Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of SPI Slave Select Management

Definition at line 64 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h.

◆ NSSPMode

uint32_t SPI_InitTypeDef::NSSPMode

Specifies whether the NSSP signal is enabled or not . This parameter can be a value of SPI NSS Pulse Mode This mode is activated by the NSSP bit in the SPIx_CR2 register and it takes effect only if the SPI interface is configured as Motorola SPI master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, CPOL setting is ignored)..

Specifies whether the NSSP signal is enabled or not . This parameter can be a value of SPI NSS Pulse Mode This mode is activated by the SSOM bit in the SPIx_CR2 register and it takes effect only if the SPI interface is configured as Motorola SPI master (FRF=0).

Definition at line 90 of file stm32f7xx_hal_spi.h.

◆ NSSPolarity

uint32_t SPI_InitTypeDef::NSSPolarity

Specifies which level of SS input/output external signal (present on SS pin) is considered as active one. This parameter can be a value of SPI NSS Polarity

Definition at line 95 of file stm32h7xx_hal_spi.h.

◆ RxCRCInitializationPattern

uint32_t SPI_InitTypeDef::RxCRCInitializationPattern

Specifies the receiver CRC initialization Pattern used for the CRC calculation. This parameter can be a value of SPI CRC Calculation Initialization Pattern

Definition at line 105 of file stm32h7xx_hal_spi.h.

◆ TIMode

uint32_t SPI_InitTypeDef::TIMode

Specifies if the TI mode is enabled or not. This parameter can be a value of SPI TI Mode

Definition at line 77 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h.

◆ TxCRCInitializationPattern

uint32_t SPI_InitTypeDef::TxCRCInitializationPattern

Specifies the transmitter CRC initialization Pattern used for the CRC calculation. This parameter can be a value of SPI CRC Calculation Initialization Pattern

Definition at line 102 of file stm32h7xx_hal_spi.h.

The documentation for this struct was generated from the following files:

Public Attributes