stm32f7xx_hal_qspi.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32F7xx_HAL_QSPI_H
22 #define STM32F7xx_HAL_QSPI_H
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f7xx_hal_def.h"
30 
31 #if defined(QUADSPI)
32 
41 /* Exported types ------------------------------------------------------------*/
49 typedef struct
50 {
51  uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
52  This parameter can be a number between 0 and 255 */
53  uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
54  This parameter can be a value between 1 and 32 */
55  uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
56  take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
57  This parameter can be a value of @ref QSPI_SampleShifting */
58  uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
59  required to address the flash memory. The flash capacity can be up to 4GB
60  (addressed using 32 bits) in indirect mode, but the addressable space in
61  memory-mapped mode is limited to 256MB
62  This parameter can be a number between 0 and 31 */
63  uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
64  of clock cycles which the chip select must remain high between commands.
65  This parameter can be a value of @ref QSPI_ChipSelectHighTime */
66  uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
67  This parameter can be a value of @ref QSPI_ClockMode */
68  uint32_t FlashID; /* Specifies the Flash which will be used,
69  This parameter can be a value of @ref QSPI_Flash_Select */
70  uint32_t DualFlash; /* Specifies the Dual Flash Mode State
71  This parameter can be a value of @ref QSPI_DualFlash_Mode */
72 }QSPI_InitTypeDef;
73 
77 typedef enum
78 {
79  HAL_QSPI_STATE_RESET = 0x00U,
80  HAL_QSPI_STATE_READY = 0x01U,
81  HAL_QSPI_STATE_BUSY = 0x02U,
82  HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U,
83  HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U,
84  HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U,
85  HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U,
86  HAL_QSPI_STATE_ABORT = 0x08U,
87  HAL_QSPI_STATE_ERROR = 0x04U
88 }HAL_QSPI_StateTypeDef;
89 
93 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
94 typedef struct __QSPI_HandleTypeDef
95 #else
96 typedef struct
97 #endif
98 {
99  QUADSPI_TypeDef *Instance; /* QSPI registers base address */
100  QSPI_InitTypeDef Init; /* QSPI communication parameters */
101  uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
102  __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */
103  __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */
104  uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
105  __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
106  __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
107  DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */
108  __IO HAL_LockTypeDef Lock; /* Locking object */
109  __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
110  __IO uint32_t ErrorCode; /* QSPI Error code */
111  uint32_t Timeout; /* Timeout for the QSPI memory access */
112 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
113  void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi);
114  void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
115  void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi);
116  void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
117  void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
118  void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
119  void (* RxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
120  void (* TxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
121  void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi);
122  void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi);
123 
124  void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi);
125  void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi);
126 #endif
127 }QSPI_HandleTypeDef;
128 
132 typedef struct
133 {
134  uint32_t Instruction; /* Specifies the Instruction to be sent
135  This parameter can be a value (8-bit) between 0x00 and 0xFF */
136  uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
137  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
138  uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
139  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
140  uint32_t AddressSize; /* Specifies the Address Size
141  This parameter can be a value of @ref QSPI_AddressSize */
142  uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
143  This parameter can be a value of @ref QSPI_AlternateBytesSize */
144  uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
145  This parameter can be a number between 0 and 31 */
146  uint32_t InstructionMode; /* Specifies the Instruction Mode
147  This parameter can be a value of @ref QSPI_InstructionMode */
148  uint32_t AddressMode; /* Specifies the Address Mode
149  This parameter can be a value of @ref QSPI_AddressMode */
150  uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
151  This parameter can be a value of @ref QSPI_AlternateBytesMode */
152  uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
153  This parameter can be a value of @ref QSPI_DataMode */
154  uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes)
155  This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
156  until end of memory)*/
157  uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
158  This parameter can be a value of @ref QSPI_DdrMode */
159  uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data
160  output by one half of system clock in DDR mode.
161  This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
162  uint32_t SIOOMode; /* Specifies the send instruction only once mode
163  This parameter can be a value of @ref QSPI_SIOOMode */
164 }QSPI_CommandTypeDef;
165 
169 typedef struct
170 {
171  uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
172  This parameter can be any value between 0 and 0xFFFFFFFF */
173  uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
174  This parameter can be any value between 0 and 0xFFFFFFFF */
175  uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
176  This parameter can be any value between 0 and 0xFFFF */
177  uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
178  This parameter can be any value between 1 and 4 */
179  uint32_t MatchMode; /* Specifies the method used for determining a match.
180  This parameter can be a value of @ref QSPI_MatchMode */
181  uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
182  This parameter can be a value of @ref QSPI_AutomaticStop */
183 }QSPI_AutoPollingTypeDef;
184 
188 typedef struct
189 {
190  uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
191  This parameter can be any value between 0 and 0xFFFF */
192  uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select.
193  This parameter can be a value of @ref QSPI_TimeOutActivation */
194 }QSPI_MemoryMappedTypeDef;
195 
196 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
197 
200 typedef enum
201 {
202  HAL_QSPI_ERROR_CB_ID = 0x00U,
203  HAL_QSPI_ABORT_CB_ID = 0x01U,
204  HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U,
205  HAL_QSPI_CMD_CPLT_CB_ID = 0x03U,
206  HAL_QSPI_RX_CPLT_CB_ID = 0x04U,
207  HAL_QSPI_TX_CPLT_CB_ID = 0x05U,
208  HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U,
209  HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U,
210  HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U,
211  HAL_QSPI_TIMEOUT_CB_ID = 0x09U,
213  HAL_QSPI_MSP_INIT_CB_ID = 0x0AU,
214  HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0
215 }HAL_QSPI_CallbackIDTypeDef;
216 
220 typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
221 #endif
222 
226 /* Exported constants --------------------------------------------------------*/
234 #define HAL_QSPI_ERROR_NONE 0x00000000U
235 #define HAL_QSPI_ERROR_TIMEOUT 0x00000001U
236 #define HAL_QSPI_ERROR_TRANSFER 0x00000002U
237 #define HAL_QSPI_ERROR_DMA 0x00000004U
238 #define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U
239 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
240 #define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U
241 #endif
242 
249 #define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U
250 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT)
258 #define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U
259 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0)
260 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1)
261 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1)
262 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2)
263 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0)
264 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1)
265 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT)
273 #define QSPI_CLOCK_MODE_0 0x00000000U
274 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE)
282 #define QSPI_FLASH_ID_1 0x00000000U
283 #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)
291 #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)
292 #define QSPI_DUALFLASH_DISABLE 0x00000000U
300 #define QSPI_ADDRESS_8_BITS 0x00000000U
301 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0)
302 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1)
303 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE)
311 #define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U
312 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0)
313 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1)
314 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE)
322 #define QSPI_INSTRUCTION_NONE 0x00000000U
323 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0)
324 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1)
325 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE)
333 #define QSPI_ADDRESS_NONE 0x00000000U
334 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0)
335 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1)
336 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE)
344 #define QSPI_ALTERNATE_BYTES_NONE 0x00000000U
345 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0)
346 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1)
347 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE)
355 #define QSPI_DATA_NONE 0x00000000U
356 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0)
357 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1)
358 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE)
366 #define QSPI_DDR_MODE_DISABLE 0x00000000U
367 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM)
375 #define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U
376 #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC)
384 #define QSPI_SIOO_INST_EVERY_CMD 0x00000000U
385 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO)
393 #define QSPI_MATCH_MODE_AND 0x00000000U
394 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM)
402 #define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U
403 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS)
411 #define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U
412 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN)
420 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY
421 #define QSPI_FLAG_TO QUADSPI_SR_TOF
422 #define QSPI_FLAG_SM QUADSPI_SR_SMF
423 #define QSPI_FLAG_FT QUADSPI_SR_FTF
424 #define QSPI_FLAG_TC QUADSPI_SR_TCF
425 #define QSPI_FLAG_TE QUADSPI_SR_TEF
433 #define QSPI_IT_TO QUADSPI_CR_TOIE
434 #define QSPI_IT_SM QUADSPI_CR_SMIE
435 #define QSPI_IT_FT QUADSPI_CR_FTIE
436 #define QSPI_IT_TC QUADSPI_CR_TCIE
437 #define QSPI_IT_TE QUADSPI_CR_TEIE
446 #define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
447 
455 /* Exported macros -----------------------------------------------------------*/
463 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
464 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) do { \
465  (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \
466  (__HANDLE__)->MspInitCallback = NULL; \
467  (__HANDLE__)->MspDeInitCallback = NULL; \
468  } while(0)
469 #else
470 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
471 #endif
472 
477 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
478 
483 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
484 
496 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
497 
498 
510 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
511 
523 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
524 
538 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
539 
550 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
551 
555 /* Exported functions --------------------------------------------------------*/
563 /* Initialization/de-initialization functions ********************************/
564 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
565 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
566 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
567 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
575 /* IO operation functions *****************************************************/
576 /* QSPI IRQ handler method */
577 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
578 
579 /* QSPI indirect mode */
580 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
581 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
582 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
583 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
584 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
585 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
586 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
587 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
588 
589 /* QSPI status flag polling mode */
590 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
591 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
592 
593 /* QSPI memory-mapped mode */
594 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
595 
596 /* Callback functions in non-blocking modes ***********************************/
597 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
598 void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
599 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
600 
601 /* QSPI indirect mode */
602 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
603 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
604 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
605 void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
606 void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
607 
608 /* QSPI status flag polling mode */
609 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
610 
611 /* QSPI memory-mapped mode */
612 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
613 
614 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
615 /* QSPI callback registering/unregistering */
616 HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback);
617 HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId);
618 #endif
619 
626 /* Peripheral Control and State functions ************************************/
627 HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
628 uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
629 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
630 HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
631 void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
632 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
633 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
634 HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID);
642 /* End of exported functions -------------------------------------------------*/
643 
644 /* Private macros ------------------------------------------------------------*/
648 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
649 
650 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U))
651 
652 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
653  ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
654 
655 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))
656 
657 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
658  ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
659  ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
660  ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
661  ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
662  ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
663  ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
664  ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
665 
666 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
667  ((CLKMODE) == QSPI_CLOCK_MODE_3))
668 
669 #define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \
670  ((FLASH_ID) == QSPI_FLASH_ID_2))
671 
672 #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
673  ((MODE) == QSPI_DUALFLASH_DISABLE))
674 
675 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)
676 
677 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
678  ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
679  ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
680  ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
681 
682 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
683  ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
684  ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
685  ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
686 
687 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)
688 
689 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
690  ((MODE) == QSPI_INSTRUCTION_1_LINE) || \
691  ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
692  ((MODE) == QSPI_INSTRUCTION_4_LINES))
693 
694 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
695  ((MODE) == QSPI_ADDRESS_1_LINE) || \
696  ((MODE) == QSPI_ADDRESS_2_LINES) || \
697  ((MODE) == QSPI_ADDRESS_4_LINES))
698 
699 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
700  ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
701  ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
702  ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
703 
704 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
705  ((MODE) == QSPI_DATA_1_LINE) || \
706  ((MODE) == QSPI_DATA_2_LINES) || \
707  ((MODE) == QSPI_DATA_4_LINES))
708 
709 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
710  ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
711 
712 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
713  ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
714 
715 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
716  ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
717 
718 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
719 
720 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
721 
722 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
723  ((MODE) == QSPI_MATCH_MODE_OR))
724 
725 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
726  ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
727 
728 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
729  ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
730 
731 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
732 
735 /* End of private macros -----------------------------------------------------*/
736 
745 #endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */
746 
747 #ifdef __cplusplus
748 }
749 #endif
750 
751 #endif /* STM32F7xx_HAL_QSPI_H */
752 
753 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
__IO
#define __IO
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:237
Init
napi_value Init(napi_env env, napi_value exports)
Definition: porcupine/demo/c/pvrecorder/node/pv_recorder_napi.c:197
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:139
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:51
QUADSPI_TypeDef
QUAD Serial Peripheral Interface.
Definition: stm32f469xx.h:909
stm32f7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.

picovoice_driver
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autogenerated on Fri Apr 1 2022 02:14:53