Macros
RCCEx_Peripheral_Clock_Enable_Disable
STM32F4xx_HAL_Driver | STM32F7xx_HAL_Driver | STM32H7xx_HAL_Driver » RCCEx » RCCEx Exported Macros

Enables or disables the AHB/APB peripheral clock. More...

Collaboration diagram for RCCEx_Peripheral_Clock_Enable_Disable:

Macros

#define __HAL_RCC_ADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
 
#define __HAL_RCC_ADC1_CLK_ENABLE()
 
#define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
 
#define __HAL_RCC_ADC2_CLK_ENABLE()
 
#define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
 
#define __HAL_RCC_ADC3_CLK_ENABLE()
 
#define __HAL_RCC_BKPSRAM_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
 
#define __HAL_RCC_BKPSRAM_CLK_ENABLE()
 Enables or disables the AHB1 peripheral clock. More...
 
#define __HAL_RCC_CAN1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
 
#define __HAL_RCC_CAN1_CLK_ENABLE()
 
#define __HAL_RCC_DAC_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
 
#define __HAL_RCC_DAC_CLK_ENABLE()
 
#define __HAL_RCC_DMA2_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
 
#define __HAL_RCC_DMA2_CLK_ENABLE()
 
#define __HAL_RCC_DTCMRAMEN_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))
 
#define __HAL_RCC_DTCMRAMEN_CLK_ENABLE()
 
#define __HAL_RCC_FMC_CLK_DISABLE()   (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
 
#define __HAL_RCC_FMC_CLK_ENABLE()
 Enables or disables the AHB3 peripheral clock. More...
 
#define __HAL_RCC_GPIOA_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
 
#define __HAL_RCC_GPIOA_CLK_ENABLE()
 
#define __HAL_RCC_GPIOB_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
 
#define __HAL_RCC_GPIOB_CLK_ENABLE()
 
#define __HAL_RCC_GPIOC_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
 
#define __HAL_RCC_GPIOC_CLK_ENABLE()
 
#define __HAL_RCC_GPIOD_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
 
#define __HAL_RCC_GPIOD_CLK_ENABLE()
 
#define __HAL_RCC_GPIOE_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
 
#define __HAL_RCC_GPIOE_CLK_ENABLE()
 
#define __HAL_RCC_GPIOF_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
 
#define __HAL_RCC_GPIOF_CLK_ENABLE()
 
#define __HAL_RCC_GPIOG_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
 
#define __HAL_RCC_GPIOG_CLK_ENABLE()
 
#define __HAL_RCC_GPIOH_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
 
#define __HAL_RCC_GPIOH_CLK_ENABLE()
 
#define __HAL_RCC_GPIOI_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
 
#define __HAL_RCC_GPIOI_CLK_ENABLE()
 
#define __HAL_RCC_I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
 
#define __HAL_RCC_I2C1_CLK_ENABLE()
 
#define __HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
 
#define __HAL_RCC_I2C2_CLK_ENABLE()
 
#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
 
#define __HAL_RCC_I2C3_CLK_ENABLE()
 
#define __HAL_RCC_LPTIM1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
 
#define __HAL_RCC_LPTIM1_CLK_ENABLE()
 
#define __HAL_RCC_QSPI_CLK_DISABLE()   (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
 
#define __HAL_RCC_QSPI_CLK_ENABLE()
 
#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
 
#define __HAL_RCC_RNG_CLK_ENABLE()
 Enable or disable the AHB2 peripheral clock. More...
 
#define __HAL_RCC_SAI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
 
#define __HAL_RCC_SAI1_CLK_ENABLE()
 
#define __HAL_RCC_SAI2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
 
#define __HAL_RCC_SAI2_CLK_ENABLE()
 
#define __HAL_RCC_SDMMC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))
 
#define __HAL_RCC_SDMMC1_CLK_ENABLE()
 
#define __HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
 
#define __HAL_RCC_SPI1_CLK_ENABLE()
 
#define __HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
 
#define __HAL_RCC_SPI2_CLK_ENABLE()
 
#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
 
#define __HAL_RCC_SPI3_CLK_ENABLE()
 
#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
 
#define __HAL_RCC_SPI4_CLK_ENABLE()
 
#define __HAL_RCC_SPI5_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
 
#define __HAL_RCC_SPI5_CLK_ENABLE()
 
#define __HAL_RCC_SPI6_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
 
#define __HAL_RCC_SPI6_CLK_ENABLE()
 
#define __HAL_RCC_TIM10_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
 
#define __HAL_RCC_TIM10_CLK_ENABLE()
 
#define __HAL_RCC_TIM11_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
 
#define __HAL_RCC_TIM11_CLK_ENABLE()
 
#define __HAL_RCC_TIM12_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
 
#define __HAL_RCC_TIM12_CLK_ENABLE()
 
#define __HAL_RCC_TIM13_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
 
#define __HAL_RCC_TIM13_CLK_ENABLE()
 
#define __HAL_RCC_TIM14_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
 
#define __HAL_RCC_TIM14_CLK_ENABLE()
 
#define __HAL_RCC_TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
 
#define __HAL_RCC_TIM1_CLK_ENABLE()
 Enable or disable the High Speed APB (APB2) peripheral clock. More...
 
#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
 
#define __HAL_RCC_TIM2_CLK_ENABLE()
 Enable or disable the Low Speed APB (APB1) peripheral clock. More...
 
#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
 
#define __HAL_RCC_TIM3_CLK_ENABLE()
 
#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
 
#define __HAL_RCC_TIM4_CLK_ENABLE()
 
#define __HAL_RCC_TIM5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
 
#define __HAL_RCC_TIM5_CLK_ENABLE()
 
#define __HAL_RCC_TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
 
#define __HAL_RCC_TIM6_CLK_ENABLE()
 
#define __HAL_RCC_TIM7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
 
#define __HAL_RCC_TIM7_CLK_ENABLE()
 
#define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
 
#define __HAL_RCC_TIM8_CLK_ENABLE()
 
#define __HAL_RCC_TIM9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
 
#define __HAL_RCC_TIM9_CLK_ENABLE()
 
#define __HAL_RCC_UART4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
 
#define __HAL_RCC_UART4_CLK_ENABLE()
 
#define __HAL_RCC_UART5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
 
#define __HAL_RCC_UART5_CLK_ENABLE()
 
#define __HAL_RCC_UART7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
 
#define __HAL_RCC_UART7_CLK_ENABLE()
 
#define __HAL_RCC_UART8_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
 
#define __HAL_RCC_UART8_CLK_ENABLE()
 
#define __HAL_RCC_USART1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
 
#define __HAL_RCC_USART1_CLK_ENABLE()
 
#define __HAL_RCC_USART2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
 
#define __HAL_RCC_USART2_CLK_ENABLE()
 
#define __HAL_RCC_USART3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
 
#define __HAL_RCC_USART3_CLK_ENABLE()
 
#define __HAL_RCC_USART6_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
 
#define __HAL_RCC_USART6_CLK_ENABLE()
 
#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
 
#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()
 
#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
 
#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()
 
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
 
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()
 

Detailed Description

Enables or disables the AHB/APB peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Macro Definition Documentation

◆ __HAL_RCC_ADC1_CLK_DISABLE

#define __HAL_RCC_ADC1_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))

Definition at line 1410 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_ADC1_CLK_ENABLE

#define __HAL_RCC_ADC1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1251 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_ADC2_CLK_DISABLE

#define __HAL_RCC_ADC2_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))

Definition at line 1411 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_ADC2_CLK_ENABLE

#define __HAL_RCC_ADC2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1259 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_ADC3_CLK_DISABLE

#define __HAL_RCC_ADC3_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))

Definition at line 1412 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_ADC3_CLK_ENABLE

#define __HAL_RCC_ADC3_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1267 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_BKPSRAM_CLK_DISABLE

#define __HAL_RCC_BKPSRAM_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))

Definition at line 729 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_BKPSRAM_CLK_ENABLE

#define __HAL_RCC_BKPSRAM_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
UNUSED(tmpreg); \
} while(0)

Enables or disables the AHB1 peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 589 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_CAN1_CLK_DISABLE

#define __HAL_RCC_CAN1_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))

Definition at line 1190 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_CAN1_CLK_ENABLE

#define __HAL_RCC_CAN1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1094 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_DAC_CLK_DISABLE

#define __HAL_RCC_DAC_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))

Definition at line 1191 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_DAC_CLK_ENABLE

#define __HAL_RCC_DAC_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1102 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_DMA2_CLK_DISABLE

#define __HAL_RCC_DMA2_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))

Definition at line 731 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_DMA2_CLK_ENABLE

#define __HAL_RCC_DMA2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 605 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_DTCMRAMEN_CLK_DISABLE

#define __HAL_RCC_DTCMRAMEN_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))

Definition at line 730 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_DTCMRAMEN_CLK_ENABLE

#define __HAL_RCC_DTCMRAMEN_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 597 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_FMC_CLK_DISABLE

#define __HAL_RCC_FMC_CLK_DISABLE ( )    (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))

Definition at line 911 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_FMC_CLK_ENABLE

#define __HAL_RCC_FMC_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
UNUSED(tmpreg); \
} while(0)

Enables or disables the AHB3 peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 895 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_GPIOA_CLK_DISABLE

#define __HAL_RCC_GPIOA_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))

Definition at line 734 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_GPIOA_CLK_ENABLE

#define __HAL_RCC_GPIOA_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 629 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_GPIOB_CLK_DISABLE

#define __HAL_RCC_GPIOB_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))

Definition at line 735 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_GPIOB_CLK_ENABLE

#define __HAL_RCC_GPIOB_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 637 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_GPIOC_CLK_DISABLE

#define __HAL_RCC_GPIOC_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))

Definition at line 736 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_GPIOC_CLK_ENABLE

#define __HAL_RCC_GPIOC_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 645 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_GPIOD_CLK_DISABLE

#define __HAL_RCC_GPIOD_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))

Definition at line 737 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_GPIOD_CLK_ENABLE

#define __HAL_RCC_GPIOD_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 653 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_GPIOE_CLK_DISABLE

#define __HAL_RCC_GPIOE_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))

Definition at line 738 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_GPIOE_CLK_ENABLE

#define __HAL_RCC_GPIOE_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 661 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_GPIOF_CLK_DISABLE

#define __HAL_RCC_GPIOF_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))

Definition at line 739 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_GPIOF_CLK_ENABLE

#define __HAL_RCC_GPIOF_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 669 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_GPIOG_CLK_DISABLE

#define __HAL_RCC_GPIOG_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))

Definition at line 740 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_GPIOG_CLK_ENABLE

#define __HAL_RCC_GPIOG_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 677 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_GPIOH_CLK_DISABLE

#define __HAL_RCC_GPIOH_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))

Definition at line 741 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_GPIOH_CLK_ENABLE

#define __HAL_RCC_GPIOH_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 685 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_GPIOI_CLK_DISABLE

#define __HAL_RCC_GPIOI_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))

Definition at line 742 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_GPIOI_CLK_ENABLE

#define __HAL_RCC_GPIOI_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 693 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_I2C1_CLK_DISABLE

#define __HAL_RCC_I2C1_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))

Definition at line 1187 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_I2C1_CLK_ENABLE

#define __HAL_RCC_I2C1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1070 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_I2C2_CLK_DISABLE

#define __HAL_RCC_I2C2_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))

Definition at line 1188 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_I2C2_CLK_ENABLE

#define __HAL_RCC_I2C2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1078 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_I2C3_CLK_DISABLE

#define __HAL_RCC_I2C3_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))

Definition at line 1189 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_I2C3_CLK_ENABLE

#define __HAL_RCC_I2C3_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1086 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_LPTIM1_CLK_DISABLE

#define __HAL_RCC_LPTIM1_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))

Definition at line 1171 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_LPTIM1_CLK_ENABLE

#define __HAL_RCC_LPTIM1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 991 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_QSPI_CLK_DISABLE

#define __HAL_RCC_QSPI_CLK_DISABLE ( )    (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))

Definition at line 912 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_QSPI_CLK_ENABLE

#define __HAL_RCC_QSPI_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 903 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_RNG_CLK_DISABLE

#define __HAL_RCC_RNG_CLK_DISABLE ( )    (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))

Definition at line 854 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_RNG_CLK_ENABLE

#define __HAL_RCC_RNG_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
UNUSED(tmpreg); \
} while(0)

Enable or disable the AHB2 peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 837 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_SAI1_CLK_DISABLE

#define __HAL_RCC_SAI1_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))

Definition at line 1421 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_SAI1_CLK_ENABLE

#define __HAL_RCC_SAI1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1339 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_SAI2_CLK_DISABLE

#define __HAL_RCC_SAI2_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))

Definition at line 1422 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_SAI2_CLK_ENABLE

#define __HAL_RCC_SAI2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1347 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_SDMMC1_CLK_DISABLE

#define __HAL_RCC_SDMMC1_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))

Definition at line 1413 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_SDMMC1_CLK_ENABLE

#define __HAL_RCC_SDMMC1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1275 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_SPI1_CLK_DISABLE

#define __HAL_RCC_SPI1_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))

Definition at line 1414 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_SPI1_CLK_ENABLE

#define __HAL_RCC_SPI1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1283 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_SPI2_CLK_DISABLE

#define __HAL_RCC_SPI2_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))

Definition at line 1181 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_SPI2_CLK_ENABLE

#define __HAL_RCC_SPI2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1022 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_SPI3_CLK_DISABLE

#define __HAL_RCC_SPI3_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))

Definition at line 1182 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_SPI3_CLK_ENABLE

#define __HAL_RCC_SPI3_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1030 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_SPI4_CLK_DISABLE

#define __HAL_RCC_SPI4_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))

Definition at line 1415 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_SPI4_CLK_ENABLE

#define __HAL_RCC_SPI4_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1291 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_SPI5_CLK_DISABLE

#define __HAL_RCC_SPI5_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))

Definition at line 1419 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_SPI5_CLK_ENABLE

#define __HAL_RCC_SPI5_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1323 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_SPI6_CLK_DISABLE

#define __HAL_RCC_SPI6_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))

Definition at line 1420 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_SPI6_CLK_ENABLE

#define __HAL_RCC_SPI6_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1331 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM10_CLK_DISABLE

#define __HAL_RCC_TIM10_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))

Definition at line 1417 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM10_CLK_ENABLE

#define __HAL_RCC_TIM10_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1307 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM11_CLK_DISABLE

#define __HAL_RCC_TIM11_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))

Definition at line 1418 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM11_CLK_ENABLE

#define __HAL_RCC_TIM11_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1315 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM12_CLK_DISABLE

#define __HAL_RCC_TIM12_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))

Definition at line 1168 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM12_CLK_ENABLE

#define __HAL_RCC_TIM12_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 967 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM13_CLK_DISABLE

#define __HAL_RCC_TIM13_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))

Definition at line 1169 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM13_CLK_ENABLE

#define __HAL_RCC_TIM13_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 975 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM14_CLK_DISABLE

#define __HAL_RCC_TIM14_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))

Definition at line 1170 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM14_CLK_ENABLE

#define __HAL_RCC_TIM14_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 983 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM1_CLK_DISABLE

#define __HAL_RCC_TIM1_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))

Definition at line 1402 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM1_CLK_ENABLE

#define __HAL_RCC_TIM1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
UNUSED(tmpreg); \
} while(0)

Enable or disable the High Speed APB (APB2) peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1208 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM2_CLK_DISABLE

#define __HAL_RCC_TIM2_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))

Definition at line 1162 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM2_CLK_ENABLE

#define __HAL_RCC_TIM2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
UNUSED(tmpreg); \
} while(0)

Enable or disable the Low Speed APB (APB1) peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 919 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM3_CLK_DISABLE

#define __HAL_RCC_TIM3_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))

Definition at line 1163 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM3_CLK_ENABLE

#define __HAL_RCC_TIM3_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 927 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM4_CLK_DISABLE

#define __HAL_RCC_TIM4_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))

Definition at line 1164 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM4_CLK_ENABLE

#define __HAL_RCC_TIM4_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 935 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM5_CLK_DISABLE

#define __HAL_RCC_TIM5_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))

Definition at line 1165 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM5_CLK_ENABLE

#define __HAL_RCC_TIM5_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 943 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM6_CLK_DISABLE

#define __HAL_RCC_TIM6_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))

Definition at line 1166 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM6_CLK_ENABLE

#define __HAL_RCC_TIM6_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 951 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM7_CLK_DISABLE

#define __HAL_RCC_TIM7_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))

Definition at line 1167 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM7_CLK_ENABLE

#define __HAL_RCC_TIM7_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 959 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM8_CLK_DISABLE

#define __HAL_RCC_TIM8_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))

Definition at line 1403 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM8_CLK_ENABLE

#define __HAL_RCC_TIM8_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1216 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM9_CLK_DISABLE

#define __HAL_RCC_TIM9_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))

Definition at line 1416 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM9_CLK_ENABLE

#define __HAL_RCC_TIM9_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1299 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_UART4_CLK_DISABLE

#define __HAL_RCC_UART4_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))

Definition at line 1185 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_UART4_CLK_ENABLE

#define __HAL_RCC_UART4_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1054 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_UART5_CLK_DISABLE

#define __HAL_RCC_UART5_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))

Definition at line 1186 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_UART5_CLK_ENABLE

#define __HAL_RCC_UART5_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1062 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_UART7_CLK_DISABLE

#define __HAL_RCC_UART7_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))

Definition at line 1192 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_UART7_CLK_ENABLE

#define __HAL_RCC_UART7_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1110 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_UART8_CLK_DISABLE

#define __HAL_RCC_UART8_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))

Definition at line 1193 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_UART8_CLK_ENABLE

#define __HAL_RCC_UART8_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1118 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_USART1_CLK_DISABLE

#define __HAL_RCC_USART1_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))

Definition at line 1404 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_USART1_CLK_ENABLE

#define __HAL_RCC_USART1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1224 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_USART2_CLK_DISABLE

#define __HAL_RCC_USART2_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))

Definition at line 1183 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_USART2_CLK_ENABLE

#define __HAL_RCC_USART2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1038 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_USART3_CLK_DISABLE

#define __HAL_RCC_USART3_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))

Definition at line 1184 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_USART3_CLK_ENABLE

#define __HAL_RCC_USART3_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1046 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_USART6_CLK_DISABLE

#define __HAL_RCC_USART6_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))

Definition at line 1405 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_USART6_CLK_ENABLE

#define __HAL_RCC_USART6_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 1232 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_USB_OTG_FS_CLK_DISABLE

#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE ( )    (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))

Definition at line 856 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_USB_OTG_FS_CLK_ENABLE

#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
UNUSED(tmpreg); \
__HAL_RCC_SYSCFG_CLK_ENABLE();\
} while(0)

Definition at line 845 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_USB_OTG_HS_CLK_DISABLE

#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))

Definition at line 732 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_USB_OTG_HS_CLK_ENABLE

#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 613 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE

#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))

Definition at line 733 of file stm32f7xx_hal_rcc_ex.h.

◆ __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE

#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 621 of file stm32f7xx_hal_rcc_ex.h.

RCC_AHB1ENR_OTGHSULPIEN
#define RCC_AHB1ENR_OTGHSULPIEN
Definition: stm32f407xx.h:9936
RCC_APB1ENR_USART2EN
#define RCC_APB1ENR_USART2EN
Definition: stm32f407xx.h:10002
RCC_APB2ENR_SPI1EN
#define RCC_APB2ENR_SPI1EN
Definition: stm32f407xx.h:10061
RCC_APB1ENR_CAN1EN
#define RCC_APB1ENR_CAN1EN
Definition: stm32f407xx.h:10023
RCC_AHB1ENR_GPIOBEN
#define RCC_AHB1ENR_GPIOBEN
Definition: stm32f407xx.h:9882
RCC_AHB1ENR_GPIOIEN
#define RCC_AHB1ENR_GPIOIEN
Definition: stm32f407xx.h:9903
RCC_APB2ENR_TIM8EN
#define RCC_APB2ENR_TIM8EN
Definition: stm32f407xx.h:10040
RCC_APB1ENR_SPI2EN
#define RCC_APB1ENR_SPI2EN
Definition: stm32f407xx.h:9996
RCC_APB1ENR_TIM14EN
#define RCC_APB1ENR_TIM14EN
Definition: stm32f407xx.h:9990
RCC_APB1ENR_I2C3EN
#define RCC_APB1ENR_I2C3EN
Definition: stm32f407xx.h:10020
RCC_AHB1ENR_DMA2EN
#define RCC_AHB1ENR_DMA2EN
Definition: stm32f407xx.h:9918
RCC_APB1ENR_TIM3EN
#define RCC_APB1ENR_TIM3EN
Definition: stm32f407xx.h:9969
RCC_APB2ENR_ADC1EN
#define RCC_APB2ENR_ADC1EN
Definition: stm32f407xx.h:10049
RCC_APB1ENR_TIM7EN
#define RCC_APB1ENR_TIM7EN
Definition: stm32f407xx.h:9981
RCC_APB2ENR_TIM11EN
#define RCC_APB2ENR_TIM11EN
Definition: stm32f407xx.h:10073
RCC_AHB2ENR_OTGFSEN
#define RCC_AHB2ENR_OTGFSEN
Definition: stm32f407xx.h:9951
RCC_APB1ENR_TIM4EN
#define RCC_APB1ENR_TIM4EN
Definition: stm32f407xx.h:9972
RCC_APB2ENR_USART6EN
#define RCC_APB2ENR_USART6EN
Definition: stm32f407xx.h:10046
RCC_AHB1ENR_GPIOEEN
#define RCC_AHB1ENR_GPIOEEN
Definition: stm32f407xx.h:9891
RCC_APB1ENR_USART3EN
#define RCC_APB1ENR_USART3EN
Definition: stm32f407xx.h:10005
RCC_APB1ENR_I2C2EN
#define RCC_APB1ENR_I2C2EN
Definition: stm32f407xx.h:10017
RCC_APB2ENR_USART1EN
#define RCC_APB2ENR_USART1EN
Definition: stm32f407xx.h:10043
RCC_APB2ENR_SPI6EN
#define RCC_APB2ENR_SPI6EN
Definition: stm32f469xx.h:14212
RCC_AHB1ENR_GPIODEN
#define RCC_AHB1ENR_GPIODEN
Definition: stm32f407xx.h:9888
RCC_AHB1ENR_GPIOCEN
#define RCC_AHB1ENR_GPIOCEN
Definition: stm32f407xx.h:9885
RCC_APB1ENR_LPTIM1EN
#define RCC_APB1ENR_LPTIM1EN
Definition: stm32f769xx.h:11493
RCC_APB1ENR_TIM6EN
#define RCC_APB1ENR_TIM6EN
Definition: stm32f407xx.h:9978
RCC_APB1ENR_TIM2EN
#define RCC_APB1ENR_TIM2EN
Definition: stm32f407xx.h:9966
RCC_APB1ENR_UART7EN
#define RCC_APB1ENR_UART7EN
Definition: stm32f469xx.h:14159
RCC_APB1ENR_DACEN
#define RCC_APB1ENR_DACEN
Definition: stm32f407xx.h:10032
RCC_APB1ENR_I2C1EN
#define RCC_APB1ENR_I2C1EN
Definition: stm32f407xx.h:10014
RCC_APB2ENR_TIM9EN
#define RCC_APB2ENR_TIM9EN
Definition: stm32f407xx.h:10067
RCC_APB2ENR_SAI2EN
#define RCC_APB2ENR_SAI2EN
Definition: stm32f769xx.h:11615
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:216
RCC_APB2ENR_TIM1EN
#define RCC_APB2ENR_TIM1EN
Definition: stm32f407xx.h:10037
RCC_APB1ENR_TIM12EN
#define RCC_APB1ENR_TIM12EN
Definition: stm32f407xx.h:9984
RCC_APB1ENR_TIM5EN
#define RCC_APB1ENR_TIM5EN
Definition: stm32f407xx.h:9975
RCC_APB2ENR_ADC3EN
#define RCC_APB2ENR_ADC3EN
Definition: stm32f407xx.h:10055
RCC_AHB1ENR_GPIOHEN
#define RCC_AHB1ENR_GPIOHEN
Definition: stm32f407xx.h:9900
RCC
#define RCC
Definition: stm32f407xx.h:1113
RCC_AHB1ENR_GPIOFEN
#define RCC_AHB1ENR_GPIOFEN
Definition: stm32f407xx.h:9894
RCC_AHB3ENR_FMCEN
#define RCC_AHB3ENR_FMCEN
Definition: stm32f469xx.h:14082
RCC_APB1ENR_TIM13EN
#define RCC_APB1ENR_TIM13EN
Definition: stm32f407xx.h:9987
RCC_APB1ENR_UART4EN
#define RCC_APB1ENR_UART4EN
Definition: stm32f407xx.h:10008
RCC_APB2ENR_SDMMC1EN
#define RCC_APB2ENR_SDMMC1EN
Definition: stm32f769xx.h:11585
RCC_APB2ENR_SPI4EN
#define RCC_APB2ENR_SPI4EN
Definition: stm32f411xe.h:4362
RCC_AHB3ENR_QSPIEN
#define RCC_AHB3ENR_QSPIEN
Definition: stm32f469xx.h:14085
RCC_APB2ENR_ADC2EN
#define RCC_APB2ENR_ADC2EN
Definition: stm32f407xx.h:10052
RCC_APB1ENR_UART8EN
#define RCC_APB1ENR_UART8EN
Definition: stm32f469xx.h:14162
RCC_AHB1ENR_BKPSRAMEN
#define RCC_AHB1ENR_BKPSRAMEN
Definition: stm32f407xx.h:9909
RCC_APB2ENR_TIM10EN
#define RCC_APB2ENR_TIM10EN
Definition: stm32f407xx.h:10070
RCC_APB1ENR_UART5EN
#define RCC_APB1ENR_UART5EN
Definition: stm32f407xx.h:10011
RCC_APB2ENR_SAI1EN
#define RCC_APB2ENR_SAI1EN
Definition: stm32f469xx.h:14215
RCC_AHB1ENR_GPIOAEN
#define RCC_AHB1ENR_GPIOAEN
Definition: stm32f407xx.h:9879
RCC_AHB2ENR_RNGEN
#define RCC_AHB2ENR_RNGEN
Definition: stm32f407xx.h:9948
RCC_AHB1ENR_OTGHSEN
#define RCC_AHB1ENR_OTGHSEN
Definition: stm32f407xx.h:9933
RCC_APB1ENR_SPI3EN
#define RCC_APB1ENR_SPI3EN
Definition: stm32f407xx.h:9999
RCC_AHB1ENR_DTCMRAMEN
#define RCC_AHB1ENR_DTCMRAMEN
Definition: stm32f769xx.h:11412
RCC_APB2ENR_SPI5EN
#define RCC_APB2ENR_SPI5EN
Definition: stm32f411xe.h:4377
RCC_AHB1ENR_GPIOGEN
#define RCC_AHB1ENR_GPIOGEN
Definition: stm32f407xx.h:9897

picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:15:08