Collaboration diagram for DFSDM channel SPI clock selection:
Macros | |
| #define | DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL 0x00000000U |
| #define | DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 |
| #define | DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 |
| #define | DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL |
Detailed Description
Macro Definition Documentation
◆ DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL
| #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL 0x00000000U |
External SPI clock
Definition at line 354 of file stm32h7xx_hal_dfsdm.h.
◆ DFSDM_CHANNEL_SPI_CLOCK_INTERNAL
| #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 |
Internal SPI clock
Definition at line 355 of file stm32h7xx_hal_dfsdm.h.
◆ DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING
| #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 |
Internal SPI clock divided by 2, falling edge
Definition at line 356 of file stm32h7xx_hal_dfsdm.h.
◆ DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING
| #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL |
Internal SPI clock divided by 2, rising edge
Definition at line 357 of file stm32h7xx_hal_dfsdm.h.