10 #if WM8904_DEBUG_REGISTER
17 #define WM8904_MAP_DAC_ADC_VOLUME(volume) (volume * (255 / 100U))
18 #define WM8904_MAP_PGA_VOLUME(volume) (volume > 0x1FU ? 0x1FU : volume)
19 #define WM8904_MAP_HEADPHONE_LINEOUT_VOLUME(volume) (volume > 0x3FU ? 0x3FU : volume)
20 #define WM8904_SWAP_UINT16_BYTE_SEQUENCE(x) (__REV16(x))
21 #define WM8904_MAP_SAMPLERATE(x) \
22 (x == kWM8904_SampleRate8kHz ? \
24 x == kWM8904_SampleRate12kHz ? \
26 x == kWM8904_SampleRate16kHz ? \
28 x == kWM8904_SampleRate24kHz ? 24000U : x == kWM8904_SampleRate32kHz ? 32000U : 48000U)
29 #define WM8904_MAP_BITWIDTH(x) \
30 (x == kWM8904_BitWidth16 ? 16 : x == kWM8904_BitWidth20 ? 20 : x == kWM8904_BitWidth24 ? 24 : 32)
53 #if WM8904_DEBUG_REGISTER
55 static const uint8_t allRegisters[] = {
56 0x00, 0x04, 0x05, 0x06, 0x07, 0x0A, 0x0C, 0x0E, 0x0F, 0x12, 0x14, 0x15, 0x16, 0x18, 0x19, 0x1A, 0x1B,
57 0x1E, 0x1F, 0x20, 0x21, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x39,
58 0x3A, 0x3B, 0x3C, 0x3D, 0x43, 0x44, 0x45, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x5A, 0x5E, 0x62,
59 0x68, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7E, 0x7F,
60 0x80, 0x81, 0x82, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93,
61 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0xC6, 0xF7, 0xF8};
153 uint16_t readValue = 0U;
182 regValue &= (uint16_t)~mask;
196 assert(handle !=
NULL);
197 assert(wm8904Config !=
NULL);
200 uint32_t sysclk = 0U;
379 sysclk =
config->fll->outputClock_HZ;
487 uint32_t bclk = sampleRate * bitWidth * 2U;
488 uint32_t bclkDiv = 0U;
489 uint16_t audioInterface = 0U;
492 if ((sysclk / bclk > 48U) || (bclk / sampleRate > 2047U) || (bclk / sampleRate < 8U))
503 audioInterface &= ~0x1FU;
504 bclkDiv = (sysclk * 10U) / bclk;
509 audioInterface |= 0U;
512 audioInterface |= 1U;
518 audioInterface |= bclkDiv / 10U;
521 audioInterface |= 6U;
524 audioInterface |= 7U;
527 audioInterface |= 8U;
532 audioInterface |= bclkDiv / 10U - 1U;
535 audioInterface |= 12U;
538 audioInterface |= 13U;
541 audioInterface |= 14U;
544 audioInterface |= 15U;
547 audioInterface |= 16U;
550 audioInterface |= 17U;
553 audioInterface |= 18U;
556 audioInterface |= 19U;
559 audioInterface |= 20U;
581 audioInterface = (1 << 11U) | (bclk / sampleRate);
594 assert(handle !=
NULL);
596 uint32_t referenceClock =
config->refClock_HZ;
597 uint32_t inputDivider = 0U;
598 uint32_t fvco = 0U, outputDiv = 0U, ratio = 0U;
599 uint32_t n = 0U, k = 0U;
602 if (referenceClock < 13500000U)
606 else if (referenceClock / 2 < 13500000U)
610 else if (referenceClock / 4 < 13500000U)
619 if (referenceClock / (1U << inputDivider) > 13500000U)
624 referenceClock = referenceClock / (1U << inputDivider);
626 for (outputDiv = 4U; outputDiv <= 64; outputDiv++)
628 fvco = outputDiv *
config->outputClock_HZ;
629 if ((fvco >= 90000000) && (fvco <= 100000000))
635 if (referenceClock <= 64000)
639 else if (referenceClock <= 128000)
643 else if (referenceClock <= 256000)
647 else if (referenceClock <= 1000000)
656 n = fvco / ((ratio + 1) * referenceClock);
657 k = (((uint64_t)fvco) * 1000000U) / ((ratio + 1) * referenceClock);
660 k = k - n * 1000000U;
662 k = ((uint64_t)k * 65536) / 1000000U;
771 assert(handle && format);
774 uint16_t mclkDiv = 0U;
775 uint32_t sampleRate = 0U;
776 uint32_t fsRatio = 0U;
808 fsRatio = (mclkFreq >> (mclkDiv & 0x1U)) / sampleRate;
911 ratio = sysclk / sampleRate;
997 uint16_t left = muteLeft ? 0x0100 : 0x0000;
998 uint16_t right = muteRight ? 0x0100 : 0x0000;
1015 #if WM8904_DEBUG_REGISTER
1029 for (i = 0; i <
sizeof(allRegisters); i++)
1037 PRINTF(
"%s", ((i % 8) == 0) ?
"\r\n" :
"\t");
1038 PRINTF(
"%02X:%04X", allRegisters[i], value);
1068 volume == 0U ? 0x100U : (volume));
1074 volume == 0U ? 0x100U : (volume | 0x80U));
1080 volume == 0U ? 0x100U : (volume));
1086 volume == 0U ? 0x100U : (volume | 0x80U));
1104 uint16_t regValue = 0U, regMask = 0U;
1106 regValue = isMute ? 0x180U : 0x80U;
1147 uint8_t regAddr = 0, regBitMask = 0U, regValue = 0U;
1154 regValue = isEnabled ? 3U : 0U;
1159 regValue = isEnabled ? 0xCU : 0U;
1165 regValue = isEnabled ? 3U : 0U;
1171 regValue = isEnabled ? 3U : 0U;
1176 regValue = isEnabled ? 3U : 0U;
1198 uint16_t regLeftValue = 0U, regRightValue = 0U, regBitMask;
1201 switch (recordSource)
1219 regLeftValue = (1U << 12U);
1222 regBitMask = 1U << 12U;
1253 uint16_t regLeftValue = 0U, regRightValue = 0U, regBitMask;
1255 uint8_t leftPositiveChannel = 0U, leftNegativeChannel = 0U, rightPositiveChannel = 0U, rightNegativeChannel = 0U;
1259 leftPositiveChannel = 0U;
1263 leftPositiveChannel = 1U;
1267 leftPositiveChannel = 2U;
1272 leftNegativeChannel = 0U;
1276 leftNegativeChannel = 1U;
1280 leftNegativeChannel = 2U;
1284 leftNegativeChannel = leftPositiveChannel;
1289 rightPositiveChannel = 0U;
1293 rightPositiveChannel = 1U;
1297 rightPositiveChannel = 2U;
1302 rightNegativeChannel = 0U;
1306 rightNegativeChannel = 1U;
1310 rightNegativeChannel = 2U;
1314 rightNegativeChannel = rightPositiveChannel;
1317 regLeftValue = ((leftNegativeChannel & 3U) << 4U) | ((leftPositiveChannel & 3U) << 2U);
1318 regRightValue = ((rightNegativeChannel & 3U) << 4U) | ((rightPositiveChannel & 3U) << 2U);
1341 uint16_t regValue = 0U, regBitMask = 0xFU;
1346 regValue |= (3U << 2U) | 3U;
1351 regValue &= ~((3U << 2U) | 3U);