usart.c

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/*
 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
 */

#include "usart.h"


#ifdef __cplusplus
extern "C" {
#endif


/* The write protect key value. */
#ifndef US_WPMR_WPKEY_PASSWD
#define US_WPMR_WPKEY_PASSWD    US_WPMR_WPKEY(0x555341U)
#endif

#ifndef US_WPMR_WPKEY_PASSWD
#  define US_WPMR_WPKEY_PASSWD US_WPMR_WPKEY(US_WPKEY_VALUE)
#endif

/* The CD value scope programmed in MR register. */
#define MIN_CD_VALUE                  0x01
#define MIN_CD_VALUE_SPI              0x04
#define MAX_CD_VALUE                  US_BRGR_CD_Msk

/* The receiver sampling divide of baudrate clock. */
#define HIGH_FRQ_SAMPLE_DIV           16
#define LOW_FRQ_SAMPLE_DIV            8

/* Max transmitter timeguard. */
#define MAX_TRAN_GUARD_TIME           US_TTGR_TG_Msk

/* The non-existent parity error number. */
#define USART_PARITY_ERROR            5

/* ISO7816 protocol type. */
#define ISO7816_T_0                   0
#define ISO7816_T_1                   1

uint32_t usart_set_async_baudrate(Usart *p_usart,
                uint32_t baudrate, uint32_t ul_mck)
{
        uint32_t over;
        uint32_t cd_fp;
        uint32_t cd;
        uint32_t fp;

        /* Calculate the receiver sampling divide of baudrate clock. */
        if (ul_mck >= HIGH_FRQ_SAMPLE_DIV * baudrate) {
                over = HIGH_FRQ_SAMPLE_DIV;
        } else {
                over = LOW_FRQ_SAMPLE_DIV;
        }

        /* Calculate clock divider according to the fraction calculated formula. */
        cd_fp = (8 * ul_mck + (over * baudrate) / 2) / (over * baudrate);
        cd = cd_fp >> 3;
        fp = cd_fp & 0x07;
        if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) {
                return 1;
        }

        /* Configure the OVER bit in MR register. */
        if (over == 8) {
                p_usart->US_MR |= US_MR_OVER;
        }

        /* Configure the baudrate generate register. */
        p_usart->US_BRGR = (cd << US_BRGR_CD_Pos) | (fp << US_BRGR_FP_Pos);

        return 0;
}

static uint32_t usart_set_sync_master_baudrate(Usart *p_usart,
                uint32_t baudrate, uint32_t ul_mck)
{
        uint32_t cd;

        /* Calculate clock divider according to the formula in synchronous mode. */
        cd = (ul_mck + baudrate / 2) / baudrate;

        if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) {
                return 1;
        }

        /* Configure the baudrate generate register. */
        p_usart->US_BRGR = cd << US_BRGR_CD_Pos;

        p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) |
                        US_MR_USCLKS_MCK | US_MR_SYNC;
        return 0;
}

static void usart_set_sync_slave_baudrate(Usart *p_usart)
{
        p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) |
                        US_MR_USCLKS_SCK | US_MR_SYNC;
}

static uint32_t usart_set_spi_master_baudrate(Usart *p_usart,
                uint32_t baudrate, uint32_t ul_mck)
{
        uint32_t cd;

        /* Calculate the clock divider according to the formula in SPI mode. */
        cd = (ul_mck + baudrate / 2) / baudrate;

        if (cd < MIN_CD_VALUE_SPI || cd > MAX_CD_VALUE) {
                return 1;
        }

        p_usart->US_BRGR = cd << US_BRGR_CD_Pos;

        return 0;
}

static void usart_set_spi_slave_baudrate(Usart *p_usart)
{
        p_usart->US_MR &= ~US_MR_USCLKS_Msk;
        p_usart->US_MR |= US_MR_USCLKS_SCK;
}

void usart_reset(Usart *p_usart)
{
        /* Disable the Write Protect. */
        usart_disable_writeprotect(p_usart);

        /* Reset registers that could cause unpredictable behavior after reset. */
        p_usart->US_MR = 0;
        p_usart->US_RTOR = 0;
        p_usart->US_TTGR = 0;

        /* Disable TX and RX. */
        usart_reset_tx(p_usart);
        usart_reset_rx(p_usart);
        /* Reset status bits. */
        usart_reset_status(p_usart);
        /* Turn off RTS and DTR if exist. */
        usart_drive_RTS_pin_high(p_usart);
#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E)
        usart_drive_DTR_pin_high(p_usart);
#endif
}

uint32_t usart_init_rs232(Usart *p_usart,
                const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
{
        static uint32_t ul_reg_val;

        /* Reset the USART and shut down TX and RX. */
        usart_reset(p_usart);

        ul_reg_val = 0;
        /* Check whether the input values are legal. */
        if (!p_usart_opt || usart_set_async_baudrate(p_usart,
                        p_usart_opt->baudrate, ul_mck)) {
                return 1;
        }

        /* Configure the USART option. */
        ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type |
                        p_usart_opt->channel_mode | p_usart_opt->stop_bits;

        /* Configure the USART mode as normal mode. */
        ul_reg_val |= US_MR_USART_MODE_NORMAL;

        p_usart->US_MR |= ul_reg_val;

        return 0;
}

uint32_t usart_init_hw_handshaking(Usart *p_usart,
                const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
{
        /* Initialize the USART as standard RS232. */
        if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {
                return 1;
        }

        /* Set hardware handshaking mode. */
        p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |
                        US_MR_USART_MODE_HW_HANDSHAKING;

        return 0;
}

#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E)

uint32_t usart_init_modem(Usart *p_usart,
                const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
{
        /*
         * SAM3S, SAM4S and SAM4E series support MODEM mode only on USART1,
         * SAM3U and SAM4L series support MODEM mode only on USART0.
         */
#if (SAM3S || SAM4S || SAM4E)
#ifdef USART1
        if (p_usart != USART1) {
                return 1;
        }
#endif
#elif (SAM3U || SAM4L)
        if (p_usart != USART0) {
                return 1;
        }
#endif

        /* Initialize the USART as standard RS232. */
        if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {
                return 1;
        }

        /* Set MODEM mode. */
        p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |
                        US_MR_USART_MODE_MODEM;

        return 0;
}
#endif

uint32_t usart_init_sync_master(Usart *p_usart,
                const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
{
        static uint32_t ul_reg_val;

        /* Reset the USART and shut down TX and RX. */
        usart_reset(p_usart);

        ul_reg_val = 0;
        /* Check whether the input values are legal. */
        if (!p_usart_opt || usart_set_sync_master_baudrate(p_usart,
                        p_usart_opt->baudrate, ul_mck)) {
                return 1;
        }

        /* Configure the USART option. */
        ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type |
                        p_usart_opt->channel_mode | p_usart_opt->stop_bits;

        /* Set normal mode and output clock as synchronous master. */
        ul_reg_val |= US_MR_USART_MODE_NORMAL | US_MR_CLKO;
        p_usart->US_MR |= ul_reg_val;

        return 0;
}

uint32_t usart_init_sync_slave(Usart *p_usart,
                const sam_usart_opt_t *p_usart_opt)
{
        static uint32_t ul_reg_val;

        /* Reset the USART and shut down TX and RX. */
        usart_reset(p_usart);

        ul_reg_val = 0;
        usart_set_sync_slave_baudrate(p_usart);

        /* Check whether the input values are legal. */
        if (!p_usart_opt) {
                return 1;
        }

        /* Configure the USART option. */
        ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type |
                        p_usart_opt->channel_mode | p_usart_opt->stop_bits;

        /* Set normal mode. */
        ul_reg_val |= US_MR_USART_MODE_NORMAL;
        p_usart->US_MR |= ul_reg_val;

        return 0;
}

uint32_t usart_init_rs485(Usart *p_usart,
                const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
{
        /* Initialize the USART as standard RS232. */
        if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {
                return 1;
        }

        /* Set RS485 mode. */
        p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |
                        US_MR_USART_MODE_RS485;

        return 0;
}

#if (!SAMG55 && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70)

uint32_t usart_init_irda(Usart *p_usart,
                const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
{
        /* Initialize the USART as standard RS232. */
        if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {
                return 1;
        }

        /* Set IrDA filter. */
        p_usart->US_IF = p_usart_opt->irda_filter;

        /* Set IrDA mode. */
        p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |
                        US_MR_USART_MODE_IRDA;

        return 0;
}
#endif

#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70)

static uint32_t usart_set_iso7816_clock(Usart *p_usart,
                uint32_t clock, uint32_t ul_mck)
{
        uint32_t cd;

        /* Calculate clock divider according to the formula in ISO7816 mode. */
        cd = (ul_mck + clock / 2) / clock;

        if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) {
                return 1;
        }

        p_usart->US_MR = (p_usart->US_MR & ~(US_MR_USCLKS_Msk | US_MR_SYNC |
                        US_MR_OVER)) | US_MR_USCLKS_MCK | US_MR_CLKO;

        /* Configure the baudrate generate register. */
        p_usart->US_BRGR = cd << US_BRGR_CD_Pos;

        return 0;
}

uint32_t usart_init_iso7816(Usart *p_usart,
                const usart_iso7816_opt_t *p_usart_opt, uint32_t ul_mck)
{
        static uint32_t ul_reg_val;

        /* Reset the USART and shut down TX and RX. */
        usart_reset(p_usart);

        ul_reg_val = 0;

        /* Check whether the input values are legal. */
        if (!p_usart_opt || ((p_usart_opt->parity_type != US_MR_PAR_EVEN) &&
                        (p_usart_opt->parity_type != US_MR_PAR_ODD))) {
                return 1;
        }

        if (p_usart_opt->protocol_type == ISO7816_T_0) {
                ul_reg_val |= US_MR_USART_MODE_IS07816_T_0 | US_MR_NBSTOP_2_BIT |
                                (p_usart_opt->max_iterations << US_MR_MAX_ITERATION_Pos);

                if (p_usart_opt->bit_order) {
                        ul_reg_val |= US_MR_MSBF;
                }
        } else if (p_usart_opt->protocol_type == ISO7816_T_1) {
                /*
                 * Only LSBF is used in the T=1 protocol, and max_iterations field
                 * is only used in T=0 mode.
                 */
                if (p_usart_opt->bit_order || p_usart_opt->max_iterations) {
                        return 1;
                }

                /* Set USART mode to ISO7816, T=1, and always uses 1 stop bit. */
                ul_reg_val |= US_MR_USART_MODE_IS07816_T_1 | US_MR_NBSTOP_1_BIT;
        } else {
                return 1;
        }

        /* Set up the baudrate. */
        if (usart_set_iso7816_clock(p_usart, p_usart_opt->iso7816_hz, ul_mck)) {
                return 1;
        }

        /* Set FIDI register: bit rate = iso7816_hz / fidi_ratio. */
        p_usart->US_FIDI = p_usart_opt->fidi_ratio;

        /* Set ISO7816 parity type in the MODE register. */
        ul_reg_val |= p_usart_opt->parity_type;

        if (p_usart_opt->inhibit_nack) {
                ul_reg_val |= US_MR_INACK;
        }
        if (p_usart_opt->dis_suc_nack) {
                ul_reg_val |= US_MR_DSNACK;
        }

        p_usart->US_MR |= ul_reg_val;

        return 0;
}

void usart_reset_iterations(Usart *p_usart)
{
        p_usart->US_CR = US_CR_RSTIT;
}

void usart_reset_nack(Usart *p_usart)
{
        p_usart->US_CR = US_CR_RSTNACK;
}

uint32_t usart_is_rx_buf_full(Usart *p_usart)
{
        return (p_usart->US_CSR & US_CSR_RXBUFF) > 0;
}

#if (!SAM4L)

uint32_t usart_is_rx_buf_end(Usart *p_usart)
{
        return (p_usart->US_CSR & US_CSR_ENDRX) > 0;
}

uint32_t usart_is_tx_buf_end(Usart *p_usart)
{
        return (p_usart->US_CSR & US_CSR_ENDTX) > 0;
}

uint32_t usart_is_tx_buf_empty(Usart *p_usart)
{
        return (p_usart->US_CSR & US_CSR_TXBUFE) > 0;
}
#endif

uint8_t usart_get_error_number(Usart *p_usart)
{
        return (p_usart->US_NER & US_NER_NB_ERRORS_Msk);
}

#endif

uint32_t usart_init_spi_master(Usart *p_usart,
                const usart_spi_opt_t *p_usart_opt, uint32_t ul_mck)
{
        static uint32_t ul_reg_val;

        /* Reset the USART and shut down TX and RX. */
        usart_reset(p_usart);

        ul_reg_val = 0;
        /* Check whether the input values are legal. */
        if (!p_usart_opt || (p_usart_opt->spi_mode > SPI_MODE_3) ||
                        usart_set_spi_master_baudrate(p_usart, p_usart_opt->baudrate,
                        ul_mck)) {
                return 1;
        }

        /* Configure the character length bit in MR register. */
        ul_reg_val |= p_usart_opt->char_length;

        /* Set SPI master mode and channel mode. */
        ul_reg_val |= US_MR_USART_MODE_SPI_MASTER | US_MR_CLKO |
                        p_usart_opt->channel_mode;

        switch (p_usart_opt->spi_mode) {
        case SPI_MODE_0:
                ul_reg_val |= US_MR_CPHA;
                ul_reg_val &= ~US_MR_CPOL;
                break;

        case SPI_MODE_1:
                ul_reg_val &= ~US_MR_CPHA;
                ul_reg_val &= ~US_MR_CPOL;
                break;

        case SPI_MODE_2:
                ul_reg_val |= US_MR_CPHA;
                ul_reg_val |= US_MR_CPOL;
                break;

        case SPI_MODE_3:
                ul_reg_val &= ~US_MR_CPHA;
                ul_reg_val |= US_MR_CPOL;
                break;

        default:
                break;
        }

        p_usart->US_MR |= ul_reg_val;

        return 0;
}

uint32_t usart_init_spi_slave(Usart *p_usart,
                const usart_spi_opt_t *p_usart_opt)
{
        static uint32_t ul_reg_val;

        /* Reset the USART and shut down TX and RX. */
        usart_reset(p_usart);

        ul_reg_val = 0;
        usart_set_spi_slave_baudrate(p_usart);

        /* Check whether the input values are legal. */
        if (!p_usart_opt || p_usart_opt->spi_mode > SPI_MODE_3) {
                return 1;
        }

        /* Configure the character length bit in MR register. */
        ul_reg_val |= p_usart_opt->char_length;

        /* Set SPI slave mode and channel mode. */
        ul_reg_val |= US_MR_USART_MODE_SPI_SLAVE | p_usart_opt->channel_mode;

        switch (p_usart_opt->spi_mode) {
        case SPI_MODE_0:
                ul_reg_val |= US_MR_CPHA;
                ul_reg_val &= ~US_MR_CPOL;
                break;

        case SPI_MODE_1:
                ul_reg_val &= ~US_MR_CPHA;
                ul_reg_val &= ~US_MR_CPOL;
                break;

        case SPI_MODE_2:
                ul_reg_val |= US_MR_CPHA;
                ul_reg_val |= US_MR_CPOL;
                break;

        case SPI_MODE_3:
                ul_reg_val |= US_MR_CPOL;
                ul_reg_val &= ~US_MR_CPHA;
                break;

        default:
                break;
        }

        p_usart->US_MR |= ul_reg_val;

        return 0;
}

#if (SAM3XA || SAM4L || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)

uint32_t usart_init_lin_master(Usart *p_usart,uint32_t ul_baudrate,
                uint32_t ul_mck)
{
        /* Reset the USART and shut down TX and RX. */
        usart_reset(p_usart);

        /* Set up the baudrate. */
        if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) {
                return 1;
        }

        /* Set LIN master mode. */
        p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |
                        US_MR_USART_MODE_LIN_MASTER;

        usart_enable_rx(p_usart);
        usart_enable_tx(p_usart);

        return 0;
}

uint32_t usart_init_lin_slave(Usart *p_usart, uint32_t ul_baudrate,
                uint32_t ul_mck)
{
        /* Reset the USART and shut down TX and RX. */
        usart_reset(p_usart);

        usart_enable_rx(p_usart);
        usart_enable_tx(p_usart);

        /* Set LIN slave mode. */
        p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |
                        US_MR_USART_MODE_LIN_SLAVE;

        /* Set up the baudrate. */
        if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) {
                return 1;
        }

        return 0;
}

void usart_lin_abort_tx(Usart *p_usart)
{
        p_usart->US_CR = US_CR_LINABT;
}

void usart_lin_send_wakeup_signal(Usart *p_usart)
{
        p_usart->US_CR = US_CR_LINWKUP;
}

void usart_lin_set_node_action(Usart *p_usart, uint8_t uc_action)
{
        p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_NACT_Msk) |
                        (uc_action << US_LINMR_NACT_Pos);
}

void usart_lin_disable_parity(Usart *p_usart)
{
        p_usart->US_LINMR |= US_LINMR_PARDIS;
}

void usart_lin_enable_parity(Usart *p_usart)
{
        p_usart->US_LINMR &= ~US_LINMR_PARDIS;
}

void usart_lin_disable_checksum(Usart *p_usart)
{
        p_usart->US_LINMR |= US_LINMR_CHKDIS;
}

void usart_lin_enable_checksum(Usart *p_usart)
{
        p_usart->US_LINMR &= ~US_LINMR_CHKDIS;
}

void usart_lin_set_checksum_type(Usart *p_usart, uint8_t uc_type)
{
        p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_CHKTYP) |
                        (uc_type << 4);
}

void usart_lin_set_data_len_mode(Usart *p_usart, uint8_t uc_mode)
{
        p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLM) |
                        (uc_mode << 5);
}

void usart_lin_disable_frame_slot(Usart *p_usart)
{
        p_usart->US_LINMR |= US_LINMR_FSDIS;
}

void usart_lin_enable_frame_slot(Usart *p_usart)
{
        p_usart->US_LINMR &= ~US_LINMR_FSDIS;
}

void usart_lin_set_wakeup_signal_type(Usart *p_usart, uint8_t uc_type)
{
        p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_WKUPTYP) |
                        (uc_type << 7);
}

void usart_lin_set_response_data_len(Usart *p_usart, uint8_t uc_len)
{
        p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLC_Msk) |
                        ((uc_len - 1) << US_LINMR_DLC_Pos);
}

void usart_lin_disable_pdc_mode(Usart *p_usart)
{
        p_usart->US_LINMR &= ~US_LINMR_PDCM;
}

void usart_lin_enable_pdc_mode(Usart *p_usart)
{
        p_usart->US_LINMR |= US_LINMR_PDCM;
}

void usart_lin_set_tx_identifier(Usart *p_usart, uint8_t uc_id)
{
        p_usart->US_LINIR = (p_usart->US_LINIR & ~US_LINIR_IDCHR_Msk) |
                        US_LINIR_IDCHR(uc_id);
}

uint8_t usart_lin_read_identifier(Usart *p_usart)
{
        return (p_usart->US_LINIR & US_LINIR_IDCHR_Msk);
}

uint8_t usart_lin_get_data_length(Usart *usart)
{
        if (usart->US_LINMR & US_LINMR_DLM) {
                uint8_t data_length = 1 << ((usart->US_LINIR >>
                                (US_LINIR_IDCHR_Pos + 4)) & 0x03);
                return data_length;
        } else {
                return ((usart->US_LINMR & US_LINMR_DLC_Msk) >> US_LINMR_DLC_Pos) + 1;
        }
}

#endif

#if (SAMV71 || SAMV70 || SAME70 || SAMS70)

uint8_t usart_lin_identifier_send_complete(Usart *usart)
{
        return (usart->US_CSR & US_CSR_LINID) > 0;
}

uint8_t usart_lin_identifier_reception_complete(Usart *usart)
{
        return (usart->US_CSR & US_CSR_LINID) > 0;
}

uint8_t usart_lin_tx_complete(Usart *usart)
{
        return (usart->US_CSR & US_CSR_LINTC) > 0;
}

uint32_t usart_init_lon(Usart *p_usart,uint32_t ul_baudrate,
                uint32_t ul_mck)
{
        /* Reset the USART and shut down TX and RX. */
        usart_reset(p_usart);

        /* Set up the baudrate. */
        if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) {
                return 1;
        }

        /* Set LIN master mode. */
        p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |
                        US_MR_USART_MODE_LON;

        usart_enable_rx(p_usart);
        usart_enable_tx(p_usart);

        return 0;
}

void  usart_lon_set_comm_type(Usart *p_usart, uint8_t uc_type)
{
        p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_COMMT) |
                         (uc_type << 0);
}

void usart_lon_disable_coll_detection(Usart *p_usart)
{
        p_usart->US_LONMR |= US_LONMR_COLDET;
}

void usart_lon_enable_coll_detection(Usart *p_usart)
{
        p_usart->US_LONMR &= ~US_LONMR_COLDET;
}

void  usart_lon_set_tcol(Usart *p_usart, uint8_t uc_type)
{
        p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_TCOL) |
                         (uc_type << 2);
}

void  usart_lon_set_cdtail(Usart *p_usart, uint8_t uc_type)
{
        p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_CDTAIL) |
                         (uc_type << 3);
}

void  usart_lon_set_dmam(Usart *p_usart, uint8_t uc_type)
{
        p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_DMAM) |
                         (uc_type << 4);
}

void  usart_lon_set_beta1_tx_len(Usart *p_usart, uint32_t ul_len)
{
        p_usart->US_LONB1TX = US_LONB1TX_BETA1TX(ul_len);
}

void  usart_lon_set_beta1_rx_len(Usart *p_usart, uint32_t ul_len)
{
        p_usart->US_LONB1RX = US_LONB1RX_BETA1RX(ul_len);
}

void  usart_lon_set_priority(Usart *p_usart, uint8_t uc_psnb, uint8_t uc_nps)
{
        p_usart->US_LONPRIO = US_LONPRIO_PSNB(uc_psnb) | US_LONPRIO_NPS(uc_nps);
}

void  usart_lon_set_tx_idt(Usart *p_usart, uint32_t ul_time)
{
        p_usart->US_IDTTX = US_IDTTX_IDTTX(ul_time);
}

void  usart_lon_set_rx_idt(Usart *p_usart, uint32_t ul_time)
{
        p_usart->US_IDTRX = US_IDTRX_IDTRX(ul_time);
}

void  usart_lon_set_pre_len(Usart *p_usart, uint32_t ul_len)
{
        p_usart->US_LONPR = US_LONPR_LONPL(ul_len);
}

void  usart_lon_set_data_len(Usart *p_usart, uint8_t uc_len)
{
        p_usart->US_LONDL = US_LONDL_LONDL(uc_len);
}

void  usart_lon_set_l2hdr(Usart *p_usart, uint8_t uc_bli, uint8_t uc_altp, uint8_t uc_pb)
{
        p_usart->US_LONL2HDR = US_LONL2HDR_BLI(uc_bli) | (uc_altp << 6) | (uc_pb << 7);
}

uint32_t usart_lon_is_tx_end(Usart *p_usart)
{
        return (p_usart->US_CSR & US_CSR_LTXD) > 0;
}

uint32_t usart_lon_is_rx_end(Usart *p_usart)
{
        return (p_usart->US_CSR & US_CSR_LRXD) > 0;
}
#endif

void usart_enable_tx(Usart *p_usart)
{
        p_usart->US_CR = US_CR_TXEN;
}

void usart_disable_tx(Usart *p_usart)
{
        p_usart->US_CR = US_CR_TXDIS;
}

void usart_reset_tx(Usart *p_usart)
{
        /* Reset transmitter */
        p_usart->US_CR = US_CR_RSTTX | US_CR_TXDIS;
}

void usart_set_tx_timeguard(Usart *p_usart, uint32_t timeguard)
{
        p_usart->US_TTGR = timeguard;
}

void usart_enable_rx(Usart *p_usart)
{
        p_usart->US_CR = US_CR_RXEN;
}

void usart_disable_rx(Usart *p_usart)
{
        p_usart->US_CR = US_CR_RXDIS;
}

void usart_reset_rx(Usart *p_usart)
{
        /* Reset Receiver */
        p_usart->US_CR = US_CR_RSTRX | US_CR_RXDIS;
}

void usart_set_rx_timeout(Usart *p_usart, uint32_t timeout)
{
        p_usart->US_RTOR = timeout;
}

void usart_enable_interrupt(Usart *p_usart, uint32_t ul_sources)
{
        p_usart->US_IER = ul_sources;
}

void usart_disable_interrupt(Usart *p_usart, uint32_t ul_sources)
{
        p_usart->US_IDR = ul_sources;
}

uint32_t usart_get_interrupt_mask(Usart *p_usart)
{
        return p_usart->US_IMR;
}

uint32_t usart_get_status(Usart *p_usart)
{
        return p_usart->US_CSR;
}

void usart_reset_status(Usart *p_usart)
{
        p_usart->US_CR = US_CR_RSTSTA;
}

void usart_start_tx_break(Usart *p_usart)
{
        p_usart->US_CR = US_CR_STTBRK;
}

void usart_stop_tx_break(Usart *p_usart)
{
        p_usart->US_CR = US_CR_STPBRK;
}

void usart_start_rx_timeout(Usart *p_usart)
{
        p_usart->US_CR = US_CR_STTTO;
}

uint32_t usart_send_address(Usart *p_usart, uint32_t ul_addr)
{
        if ((p_usart->US_MR & US_MR_PAR_MULTIDROP) != US_MR_PAR_MULTIDROP) {
                return 1;
        }

        p_usart->US_CR = US_CR_SENDA;

        if (usart_write(p_usart, ul_addr)) {
                return 1;
        } else {
                return 0;
        }
}

void usart_restart_rx_timeout(Usart *p_usart)
{
        p_usart->US_CR = US_CR_RETTO;
}

#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E)

void usart_drive_DTR_pin_low(Usart *p_usart)
{
        p_usart->US_CR = US_CR_DTREN;
}

void usart_drive_DTR_pin_high(Usart *p_usart)
{
        p_usart->US_CR = US_CR_DTRDIS;
}

#endif

void usart_drive_RTS_pin_low(Usart *p_usart)
{
        p_usart->US_CR = US_CR_RTSEN;
}

void usart_drive_RTS_pin_high(Usart *p_usart)
{
        p_usart->US_CR = US_CR_RTSDIS;
}

void usart_spi_force_chip_select(Usart *p_usart)
{
        p_usart->US_CR = US_CR_FCS;
}

void usart_spi_release_chip_select(Usart *p_usart)
{
        p_usart->US_CR = US_CR_RCS;
}

uint32_t usart_is_tx_ready(Usart *p_usart)
{
        return (p_usart->US_CSR & US_CSR_TXRDY) > 0;
}

uint32_t usart_is_tx_empty(Usart *p_usart)
{
        return (p_usart->US_CSR & US_CSR_TXEMPTY) > 0;
}

uint32_t usart_is_rx_ready(Usart *p_usart)
{
        return (p_usart->US_CSR & US_CSR_RXRDY) > 0;
}

uint32_t usart_write(Usart *p_usart, uint32_t c)
{
        if (!(p_usart->US_CSR & US_CSR_TXRDY)) {
                return 1;
        }

        p_usart->US_THR = US_THR_TXCHR(c);
        return 0;
}

uint32_t usart_putchar(Usart *p_usart, uint32_t c)
{
        while (!(p_usart->US_CSR & US_CSR_TXRDY)) {
        }

        p_usart->US_THR = US_THR_TXCHR(c);

        return 0;
}

void usart_write_line(Usart *p_usart, const char *string)
{
        while (*string != '\0') {
                usart_putchar(p_usart, *string++);
        }
}

uint32_t usart_read(Usart *p_usart, uint32_t *c)
{
        if (!(p_usart->US_CSR & US_CSR_RXRDY)) {
                return 1;
        }

        /* Read character */
        *c = p_usart->US_RHR & US_RHR_RXCHR_Msk;

        return 0;
}

uint32_t usart_getchar(Usart *p_usart, uint32_t *c)
{
        /* Wait until it's not empty or timeout has reached. */
        while (!(p_usart->US_CSR & US_CSR_RXRDY)) {
        }

        /* Read character */
        *c = p_usart->US_RHR & US_RHR_RXCHR_Msk;

        return 0;
}

#if (SAM3XA || SAM3U)

uint32_t *usart_get_tx_access(Usart *p_usart)
{
        return (uint32_t *)&(p_usart->US_THR);
}

uint32_t *usart_get_rx_access(Usart *p_usart)
{
        return (uint32_t *)&(p_usart->US_RHR);
}
#endif

#if (!SAM4L && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70)

Pdc *usart_get_pdc_base(Usart *p_usart)
{
        Pdc *p_pdc_base;

        p_pdc_base = (Pdc *)NULL;

#ifdef PDC_USART
        if (p_usart == USART) {
                p_pdc_base = PDC_USART;
                return p_pdc_base;
        }
#endif
#ifdef PDC_USART0
        if (p_usart == USART0) {
                p_pdc_base = PDC_USART0;
                return p_pdc_base;
        }
#endif
#ifdef PDC_USART1
        else if (p_usart == USART1) {
                p_pdc_base = PDC_USART1;
                return p_pdc_base;
        }
#endif
#ifdef PDC_USART2
        else if (p_usart == USART2) {
                p_pdc_base = PDC_USART2;
                return p_pdc_base;
        }
#endif
#ifdef PDC_USART3
        else if (p_usart == USART3) {
                p_pdc_base = PDC_USART3;
                return p_pdc_base;
        }
#endif
#ifdef PDC_USART4
        else if (p_usart == USART4) {
                p_pdc_base = PDC_USART4;
                return p_pdc_base;
        }
#endif
#ifdef PDC_USART5
        else if (p_usart == USART5) {
                p_pdc_base = PDC_USART5;
                return p_pdc_base;
        }
#endif
#ifdef PDC_USART6
        else if (p_usart == USART6) {
                p_pdc_base = PDC_USART6;
                return p_pdc_base;
        }
#endif
#ifdef PDC_USART7
        else if (p_usart == USART7) {
                p_pdc_base = PDC_USART7;
                return p_pdc_base;
        }
#endif

        return p_pdc_base;
}
#endif

void usart_enable_writeprotect(Usart *p_usart)
{
        p_usart->US_WPMR = US_WPMR_WPEN | US_WPMR_WPKEY_PASSWD;
}

void usart_disable_writeprotect(Usart *p_usart)
{
        p_usart->US_WPMR = US_WPMR_WPKEY_PASSWD;
}

uint32_t usart_get_writeprotect_status(Usart *p_usart)
{
        uint32_t reg_value;

        reg_value = p_usart->US_WPSR;
        if (reg_value & US_WPSR_WPVS) {
                return (reg_value & US_WPSR_WPVSRC_Msk) >> US_WPSR_WPVSRC_Pos;
        } else {
                return 0;
        }
}

#if (SAM3S || SAM4S || SAM3U || SAM3XA || SAM4L || SAM4E || SAM4C || SAM4CP || SAM4CM)

void usart_man_set_tx_pre_len(Usart *p_usart, uint8_t uc_len)
{
        p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PL_Msk) |
                        US_MAN_TX_PL(uc_len);
}

void usart_man_set_tx_pre_pattern(Usart *p_usart, uint8_t uc_pattern)
{
        p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PP_Msk) |
                        (uc_pattern << US_MAN_TX_PP_Pos);
}

void usart_man_set_tx_polarity(Usart *p_usart, uint8_t uc_polarity)
{
        p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_MPOL) |
                        (uc_polarity << 12);
}

void usart_man_set_rx_pre_len(Usart *p_usart, uint8_t uc_len)
{
        p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PL_Msk) |
                        US_MAN_RX_PL(uc_len);
}

void usart_man_set_rx_pre_pattern(Usart *p_usart, uint8_t uc_pattern)
{
        p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PP_Msk) |
                        (uc_pattern << US_MAN_RX_PP_Pos);
}

void usart_man_set_rx_polarity(Usart *p_usart, uint8_t uc_polarity)
{
        p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_MPOL) |
                        (uc_polarity << 28);
}

void usart_man_enable_drift_compensation(Usart *p_usart)
{
        p_usart->US_MAN |= US_MAN_DRIFT;
}

void usart_man_disable_drift_compensation(Usart *p_usart)
{
        p_usart->US_MAN &= ~US_MAN_DRIFT;
}

#endif

#if SAM4L

uint32_t usart_get_version(Usart *p_usart)
{
        return p_usart->US_VERSION;
}

#endif

#if SAMG55

void usart_set_sleepwalking(Usart *p_uart, uint8_t ul_low_value,
                bool cmpmode, bool cmppar, uint8_t ul_high_value)
{
        Assert(ul_low_value <= ul_high_value);

        uint32_t temp = 0;

        if (cmpmode) {
                temp |= US_CMPR_CMPMODE_START_CONDITION;
        }

        if (cmppar) {
                temp |= US_CMPR_CMPPAR;
        }

        temp |= US_CMPR_VAL1(ul_low_value);

        temp |= US_CMPR_VAL2(ul_high_value);

        p_uart->US_CMPR= temp;
}
#endif



#ifdef __cplusplus
}
#endif

---

inertial_sense_ros
Author(s):
autogenerated on Sun Feb 28 2021 03:17:58