Classes | Macros
High Speed MultiMedia Card Interface

Classes

struct  Hsmci
 Hsmci hardware registers. More...
 

Macros

#define HSMCI_ARGR_ARG(value)   ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))
 
#define HSMCI_ARGR_ARG_Msk   (0xffffffffu << HSMCI_ARGR_ARG_Pos)
 (HSMCI_ARGR) Command Argument More...
 
#define HSMCI_ARGR_ARG_Pos   0
 
#define HSMCI_BLKR_BCNT(value)   ((HSMCI_BLKR_BCNT_Msk & ((value) << HSMCI_BLKR_BCNT_Pos)))
 
#define HSMCI_BLKR_BCNT_Msk   (0xffffu << HSMCI_BLKR_BCNT_Pos)
 (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count More...
 
#define HSMCI_BLKR_BCNT_Pos   0
 
#define HSMCI_BLKR_BLKLEN(value)   ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))
 
#define HSMCI_BLKR_BLKLEN_Msk   (0xffffu << HSMCI_BLKR_BLKLEN_Pos)
 (HSMCI_BLKR) Data Block Length More...
 
#define HSMCI_BLKR_BLKLEN_Pos   16
 
#define HSMCI_CFG_FERRCTRL   (0x1u << 4)
 (HSMCI_CFG) Flow Error flag reset control mode More...
 
#define HSMCI_CFG_FIFOMODE   (0x1u << 0)
 (HSMCI_CFG) HSMCI Internal FIFO control mode More...
 
#define HSMCI_CFG_HSMODE   (0x1u << 8)
 (HSMCI_CFG) High Speed Mode More...
 
#define HSMCI_CFG_LSYNC   (0x1u << 12)
 (HSMCI_CFG) Synchronize on the last block More...
 
#define HSMCI_CMDR_ATACS   (0x1u << 26)
 (HSMCI_CMDR) ATA with Command Completion Signal More...
 
#define HSMCI_CMDR_ATACS_COMPLETION   (0x1u << 26)
 (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). More...
 
#define HSMCI_CMDR_ATACS_NORMAL   (0x0u << 26)
 (HSMCI_CMDR) Normal operation mode. More...
 
#define HSMCI_CMDR_BOOT_ACK   (0x1u << 27)
 (HSMCI_CMDR) Boot Operation Acknowledge More...
 
#define HSMCI_CMDR_CMDNB(value)   ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))
 
#define HSMCI_CMDR_CMDNB_Msk   (0x3fu << HSMCI_CMDR_CMDNB_Pos)
 (HSMCI_CMDR) Command Number More...
 
#define HSMCI_CMDR_CMDNB_Pos   0
 
#define HSMCI_CMDR_IOSPCMD(value)   ((HSMCI_CMDR_IOSPCMD_Msk & ((value) << HSMCI_CMDR_IOSPCMD_Pos)))
 
#define HSMCI_CMDR_IOSPCMD_Msk   (0x3u << HSMCI_CMDR_IOSPCMD_Pos)
 (HSMCI_CMDR) SDIO Special Command More...
 
#define HSMCI_CMDR_IOSPCMD_Pos   24
 
#define HSMCI_CMDR_IOSPCMD_RESUME   (0x2u << 24)
 (HSMCI_CMDR) SDIO Resume Command More...
 
#define HSMCI_CMDR_IOSPCMD_STD   (0x0u << 24)
 (HSMCI_CMDR) Not an SDIO Special Command More...
 
#define HSMCI_CMDR_IOSPCMD_SUSPEND   (0x1u << 24)
 (HSMCI_CMDR) SDIO Suspend Command More...
 
#define HSMCI_CMDR_MAXLAT   (0x1u << 12)
 (HSMCI_CMDR) Max Latency for Command to Response More...
 
#define HSMCI_CMDR_MAXLAT_5   (0x0u << 12)
 (HSMCI_CMDR) 5-cycle max latency. More...
 
#define HSMCI_CMDR_MAXLAT_64   (0x1u << 12)
 (HSMCI_CMDR) 64-cycle max latency. More...
 
#define HSMCI_CMDR_OPDCMD   (0x1u << 11)
 (HSMCI_CMDR) Open Drain Command More...
 
#define HSMCI_CMDR_OPDCMD_OPENDRAIN   (0x1u << 11)
 (HSMCI_CMDR) Open drain command. More...
 
#define HSMCI_CMDR_OPDCMD_PUSHPULL   (0x0u << 11)
 (HSMCI_CMDR) Push pull command. More...
 
#define HSMCI_CMDR_RSPTYP(value)   ((HSMCI_CMDR_RSPTYP_Msk & ((value) << HSMCI_CMDR_RSPTYP_Pos)))
 
#define HSMCI_CMDR_RSPTYP_136_BIT   (0x2u << 6)
 (HSMCI_CMDR) 136-bit response More...
 
#define HSMCI_CMDR_RSPTYP_48_BIT   (0x1u << 6)
 (HSMCI_CMDR) 48-bit response More...
 
#define HSMCI_CMDR_RSPTYP_Msk   (0x3u << HSMCI_CMDR_RSPTYP_Pos)
 (HSMCI_CMDR) Response Type More...
 
#define HSMCI_CMDR_RSPTYP_NORESP   (0x0u << 6)
 (HSMCI_CMDR) No response More...
 
#define HSMCI_CMDR_RSPTYP_Pos   6
 
#define HSMCI_CMDR_RSPTYP_R1B   (0x3u << 6)
 (HSMCI_CMDR) R1b response type More...
 
#define HSMCI_CMDR_SPCMD(value)   ((HSMCI_CMDR_SPCMD_Msk & ((value) << HSMCI_CMDR_SPCMD_Pos)))
 
#define HSMCI_CMDR_SPCMD_BOR   (0x6u << 8)
 (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. More...
 
#define HSMCI_CMDR_SPCMD_CE_ATA   (0x3u << 8)
 (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. More...
 
#define HSMCI_CMDR_SPCMD_EBO   (0x7u << 8)
 (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. More...
 
#define HSMCI_CMDR_SPCMD_INIT   (0x1u << 8)
 (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. More...
 
#define HSMCI_CMDR_SPCMD_IT_CMD   (0x4u << 8)
 (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). More...
 
#define HSMCI_CMDR_SPCMD_IT_RESP   (0x5u << 8)
 (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). More...
 
#define HSMCI_CMDR_SPCMD_Msk   (0x7u << HSMCI_CMDR_SPCMD_Pos)
 (HSMCI_CMDR) Special Command More...
 
#define HSMCI_CMDR_SPCMD_Pos   8
 
#define HSMCI_CMDR_SPCMD_STD   (0x0u << 8)
 (HSMCI_CMDR) Not a special CMD. More...
 
#define HSMCI_CMDR_SPCMD_SYNC   (0x2u << 8)
 (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. More...
 
#define HSMCI_CMDR_TRCMD(value)   ((HSMCI_CMDR_TRCMD_Msk & ((value) << HSMCI_CMDR_TRCMD_Pos)))
 
#define HSMCI_CMDR_TRCMD_Msk   (0x3u << HSMCI_CMDR_TRCMD_Pos)
 (HSMCI_CMDR) Transfer Command More...
 
#define HSMCI_CMDR_TRCMD_NO_DATA   (0x0u << 16)
 (HSMCI_CMDR) No data transfer More...
 
#define HSMCI_CMDR_TRCMD_Pos   16
 
#define HSMCI_CMDR_TRCMD_START_DATA   (0x1u << 16)
 (HSMCI_CMDR) Start data transfer More...
 
#define HSMCI_CMDR_TRCMD_STOP_DATA   (0x2u << 16)
 (HSMCI_CMDR) Stop data transfer More...
 
#define HSMCI_CMDR_TRDIR   (0x1u << 18)
 (HSMCI_CMDR) Transfer Direction More...
 
#define HSMCI_CMDR_TRDIR_READ   (0x1u << 18)
 (HSMCI_CMDR) Read. More...
 
#define HSMCI_CMDR_TRDIR_WRITE   (0x0u << 18)
 (HSMCI_CMDR) Write. More...
 
#define HSMCI_CMDR_TRTYP(value)   ((HSMCI_CMDR_TRTYP_Msk & ((value) << HSMCI_CMDR_TRTYP_Pos)))
 
#define HSMCI_CMDR_TRTYP_BLOCK   (0x5u << 19)
 (HSMCI_CMDR) SDIO Block More...
 
#define HSMCI_CMDR_TRTYP_BYTE   (0x4u << 19)
 (HSMCI_CMDR) SDIO Byte More...
 
#define HSMCI_CMDR_TRTYP_Msk   (0x7u << HSMCI_CMDR_TRTYP_Pos)
 (HSMCI_CMDR) Transfer Type More...
 
#define HSMCI_CMDR_TRTYP_MULTIPLE   (0x1u << 19)
 (HSMCI_CMDR) MMC/SD Card Multiple Block More...
 
#define HSMCI_CMDR_TRTYP_Pos   19
 
#define HSMCI_CMDR_TRTYP_SINGLE   (0x0u << 19)
 (HSMCI_CMDR) MMC/SD Card Single Block More...
 
#define HSMCI_CMDR_TRTYP_STREAM   (0x2u << 19)
 (HSMCI_CMDR) MMC Stream More...
 
#define HSMCI_CR_MCIDIS   (0x1u << 1)
 (HSMCI_CR) Multi-Media Interface Disable More...
 
#define HSMCI_CR_MCIEN   (0x1u << 0)
 (HSMCI_CR) Multi-Media Interface Enable More...
 
#define HSMCI_CR_PWSDIS   (0x1u << 3)
 (HSMCI_CR) Power Save Mode Disable More...
 
#define HSMCI_CR_PWSEN   (0x1u << 2)
 (HSMCI_CR) Power Save Mode Enable More...
 
#define HSMCI_CR_SWRST   (0x1u << 7)
 (HSMCI_CR) Software Reset More...
 
#define HSMCI_CSTOR_CSTOCYC(value)   ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))
 
#define HSMCI_CSTOR_CSTOCYC_Msk   (0xfu << HSMCI_CSTOR_CSTOCYC_Pos)
 (HSMCI_CSTOR) Completion Signal Timeout Cycle Number More...
 
#define HSMCI_CSTOR_CSTOCYC_Pos   0
 
#define HSMCI_CSTOR_CSTOMUL(value)   ((HSMCI_CSTOR_CSTOMUL_Msk & ((value) << HSMCI_CSTOR_CSTOMUL_Pos)))
 
#define HSMCI_CSTOR_CSTOMUL_1   (0x0u << 4)
 (HSMCI_CSTOR) CSTOCYC x 1 More...
 
#define HSMCI_CSTOR_CSTOMUL_1024   (0x4u << 4)
 (HSMCI_CSTOR) CSTOCYC x 1024 More...
 
#define HSMCI_CSTOR_CSTOMUL_1048576   (0x7u << 4)
 (HSMCI_CSTOR) CSTOCYC x 1048576 More...
 
#define HSMCI_CSTOR_CSTOMUL_128   (0x2u << 4)
 (HSMCI_CSTOR) CSTOCYC x 128 More...
 
#define HSMCI_CSTOR_CSTOMUL_16   (0x1u << 4)
 (HSMCI_CSTOR) CSTOCYC x 16 More...
 
#define HSMCI_CSTOR_CSTOMUL_256   (0x3u << 4)
 (HSMCI_CSTOR) CSTOCYC x 256 More...
 
#define HSMCI_CSTOR_CSTOMUL_4096   (0x5u << 4)
 (HSMCI_CSTOR) CSTOCYC x 4096 More...
 
#define HSMCI_CSTOR_CSTOMUL_65536   (0x6u << 4)
 (HSMCI_CSTOR) CSTOCYC x 65536 More...
 
#define HSMCI_CSTOR_CSTOMUL_Msk   (0x7u << HSMCI_CSTOR_CSTOMUL_Pos)
 (HSMCI_CSTOR) Completion Signal Timeout Multiplier More...
 
#define HSMCI_CSTOR_CSTOMUL_Pos   4
 
#define HSMCI_DMA_CHKSIZE(value)   ((HSMCI_DMA_CHKSIZE_Msk & ((value) << HSMCI_DMA_CHKSIZE_Pos)))
 
#define HSMCI_DMA_CHKSIZE_1   (0x0u << 4)
 (HSMCI_DMA) 1 data available More...
 
#define HSMCI_DMA_CHKSIZE_16   (0x4u << 4)
 (HSMCI_DMA) 16 data available More...
 
#define HSMCI_DMA_CHKSIZE_2   (0x1u << 4)
 (HSMCI_DMA) 2 data available More...
 
#define HSMCI_DMA_CHKSIZE_4   (0x2u << 4)
 (HSMCI_DMA) 4 data available More...
 
#define HSMCI_DMA_CHKSIZE_8   (0x3u << 4)
 (HSMCI_DMA) 8 data available More...
 
#define HSMCI_DMA_CHKSIZE_Msk   (0x7u << HSMCI_DMA_CHKSIZE_Pos)
 (HSMCI_DMA) DMA Channel Read and Write Chunk Size More...
 
#define HSMCI_DMA_CHKSIZE_Pos   4
 
#define HSMCI_DMA_DMAEN   (0x1u << 8)
 (HSMCI_DMA) DMA Hardware Handshaking Enable More...
 
#define HSMCI_DTOR_DTOCYC(value)   ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))
 
#define HSMCI_DTOR_DTOCYC_Msk   (0xfu << HSMCI_DTOR_DTOCYC_Pos)
 (HSMCI_DTOR) Data Timeout Cycle Number More...
 
#define HSMCI_DTOR_DTOCYC_Pos   0
 
#define HSMCI_DTOR_DTOMUL(value)   ((HSMCI_DTOR_DTOMUL_Msk & ((value) << HSMCI_DTOR_DTOMUL_Pos)))
 
#define HSMCI_DTOR_DTOMUL_1   (0x0u << 4)
 (HSMCI_DTOR) DTOCYC More...
 
#define HSMCI_DTOR_DTOMUL_1024   (0x4u << 4)
 (HSMCI_DTOR) DTOCYC x 1024 More...
 
#define HSMCI_DTOR_DTOMUL_1048576   (0x7u << 4)
 (HSMCI_DTOR) DTOCYC x 1048576 More...
 
#define HSMCI_DTOR_DTOMUL_128   (0x2u << 4)
 (HSMCI_DTOR) DTOCYC x 128 More...
 
#define HSMCI_DTOR_DTOMUL_16   (0x1u << 4)
 (HSMCI_DTOR) DTOCYC x 16 More...
 
#define HSMCI_DTOR_DTOMUL_256   (0x3u << 4)
 (HSMCI_DTOR) DTOCYC x 256 More...
 
#define HSMCI_DTOR_DTOMUL_4096   (0x5u << 4)
 (HSMCI_DTOR) DTOCYC x 4096 More...
 
#define HSMCI_DTOR_DTOMUL_65536   (0x6u << 4)
 (HSMCI_DTOR) DTOCYC x 65536 More...
 
#define HSMCI_DTOR_DTOMUL_Msk   (0x7u << HSMCI_DTOR_DTOMUL_Pos)
 (HSMCI_DTOR) Data Timeout Multiplier More...
 
#define HSMCI_DTOR_DTOMUL_Pos   4
 
#define HSMCI_FIFO_DATA(value)   ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos)))
 
#define HSMCI_FIFO_DATA_Msk   (0xffffffffu << HSMCI_FIFO_DATA_Pos)
 (HSMCI_FIFO[256]) Data to Read or Data to Write More...
 
#define HSMCI_FIFO_DATA_Pos   0
 
#define HSMCI_IDR_ACKRCV   (0x1u << 28)
 (HSMCI_IDR) Boot Acknowledge Interrupt Disable More...
 
#define HSMCI_IDR_ACKRCVE   (0x1u << 29)
 (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable More...
 
#define HSMCI_IDR_BLKE   (0x1u << 3)
 (HSMCI_IDR) Data Block Ended Interrupt Disable More...
 
#define HSMCI_IDR_BLKOVRE   (0x1u << 24)
 (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable More...
 
#define HSMCI_IDR_CMDRDY   (0x1u << 0)
 (HSMCI_IDR) Command Ready Interrupt Disable More...
 
#define HSMCI_IDR_CSRCV   (0x1u << 13)
 (HSMCI_IDR) Completion Signal received interrupt Disable More...
 
#define HSMCI_IDR_CSTOE   (0x1u << 23)
 (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable More...
 
#define HSMCI_IDR_DCRCE   (0x1u << 21)
 (HSMCI_IDR) Data CRC Error Interrupt Disable More...
 
#define HSMCI_IDR_DTIP   (0x1u << 4)
 (HSMCI_IDR) Data Transfer in Progress Interrupt Disable More...
 
#define HSMCI_IDR_DTOE   (0x1u << 22)
 (HSMCI_IDR) Data Time-out Error Interrupt Disable More...
 
#define HSMCI_IDR_FIFOEMPTY   (0x1u << 26)
 (HSMCI_IDR) FIFO empty Interrupt Disable More...
 
#define HSMCI_IDR_NOTBUSY   (0x1u << 5)
 (HSMCI_IDR) Data Not Busy Interrupt Disable More...
 
#define HSMCI_IDR_OVRE   (0x1u << 30)
 (HSMCI_IDR) Overrun Interrupt Disable More...
 
#define HSMCI_IDR_RCRCE   (0x1u << 18)
 (HSMCI_IDR) Response CRC Error Interrupt Disable More...
 
#define HSMCI_IDR_RDIRE   (0x1u << 17)
 (HSMCI_IDR) Response Direction Error Interrupt Disable More...
 
#define HSMCI_IDR_RENDE   (0x1u << 19)
 (HSMCI_IDR) Response End Bit Error Interrupt Disable More...
 
#define HSMCI_IDR_RINDE   (0x1u << 16)
 (HSMCI_IDR) Response Index Error Interrupt Disable More...
 
#define HSMCI_IDR_RTOE   (0x1u << 20)
 (HSMCI_IDR) Response Time-out Error Interrupt Disable More...
 
#define HSMCI_IDR_RXRDY   (0x1u << 1)
 (HSMCI_IDR) Receiver Ready Interrupt Disable More...
 
#define HSMCI_IDR_SDIOIRQA   (0x1u << 8)
 (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable More...
 
#define HSMCI_IDR_SDIOWAIT   (0x1u << 12)
 (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable More...
 
#define HSMCI_IDR_TXRDY   (0x1u << 2)
 (HSMCI_IDR) Transmit Ready Interrupt Disable More...
 
#define HSMCI_IDR_UNRE   (0x1u << 31)
 (HSMCI_IDR) Underrun Interrupt Disable More...
 
#define HSMCI_IDR_XFRDONE   (0x1u << 27)
 (HSMCI_IDR) Transfer Done Interrupt Disable More...
 
#define HSMCI_IER_ACKRCV   (0x1u << 28)
 (HSMCI_IER) Boot Acknowledge Interrupt Enable More...
 
#define HSMCI_IER_ACKRCVE   (0x1u << 29)
 (HSMCI_IER) Boot Acknowledge Error Interrupt Enable More...
 
#define HSMCI_IER_BLKE   (0x1u << 3)
 (HSMCI_IER) Data Block Ended Interrupt Enable More...
 
#define HSMCI_IER_BLKOVRE   (0x1u << 24)
 (HSMCI_IER) DMA Block Overrun Error Interrupt Enable More...
 
#define HSMCI_IER_CMDRDY   (0x1u << 0)
 (HSMCI_IER) Command Ready Interrupt Enable More...
 
#define HSMCI_IER_CSRCV   (0x1u << 13)
 (HSMCI_IER) Completion Signal Received Interrupt Enable More...
 
#define HSMCI_IER_CSTOE   (0x1u << 23)
 (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable More...
 
#define HSMCI_IER_DCRCE   (0x1u << 21)
 (HSMCI_IER) Data CRC Error Interrupt Enable More...
 
#define HSMCI_IER_DTIP   (0x1u << 4)
 (HSMCI_IER) Data Transfer in Progress Interrupt Enable More...
 
#define HSMCI_IER_DTOE   (0x1u << 22)
 (HSMCI_IER) Data Time-out Error Interrupt Enable More...
 
#define HSMCI_IER_FIFOEMPTY   (0x1u << 26)
 (HSMCI_IER) FIFO empty Interrupt enable More...
 
#define HSMCI_IER_NOTBUSY   (0x1u << 5)
 (HSMCI_IER) Data Not Busy Interrupt Enable More...
 
#define HSMCI_IER_OVRE   (0x1u << 30)
 (HSMCI_IER) Overrun Interrupt Enable More...
 
#define HSMCI_IER_RCRCE   (0x1u << 18)
 (HSMCI_IER) Response CRC Error Interrupt Enable More...
 
#define HSMCI_IER_RDIRE   (0x1u << 17)
 (HSMCI_IER) Response Direction Error Interrupt Enable More...
 
#define HSMCI_IER_RENDE   (0x1u << 19)
 (HSMCI_IER) Response End Bit Error Interrupt Enable More...
 
#define HSMCI_IER_RINDE   (0x1u << 16)
 (HSMCI_IER) Response Index Error Interrupt Enable More...
 
#define HSMCI_IER_RTOE   (0x1u << 20)
 (HSMCI_IER) Response Time-out Error Interrupt Enable More...
 
#define HSMCI_IER_RXRDY   (0x1u << 1)
 (HSMCI_IER) Receiver Ready Interrupt Enable More...
 
#define HSMCI_IER_SDIOIRQA   (0x1u << 8)
 (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable More...
 
#define HSMCI_IER_SDIOWAIT   (0x1u << 12)
 (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable More...
 
#define HSMCI_IER_TXRDY   (0x1u << 2)
 (HSMCI_IER) Transmit Ready Interrupt Enable More...
 
#define HSMCI_IER_UNRE   (0x1u << 31)
 (HSMCI_IER) Underrun Interrupt Enable More...
 
#define HSMCI_IER_XFRDONE   (0x1u << 27)
 (HSMCI_IER) Transfer Done Interrupt enable More...
 
#define HSMCI_IMR_ACKRCV   (0x1u << 28)
 (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask More...
 
#define HSMCI_IMR_ACKRCVE   (0x1u << 29)
 (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask More...
 
#define HSMCI_IMR_BLKE   (0x1u << 3)
 (HSMCI_IMR) Data Block Ended Interrupt Mask More...
 
#define HSMCI_IMR_BLKOVRE   (0x1u << 24)
 (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask More...
 
#define HSMCI_IMR_CMDRDY   (0x1u << 0)
 (HSMCI_IMR) Command Ready Interrupt Mask More...
 
#define HSMCI_IMR_CSRCV   (0x1u << 13)
 (HSMCI_IMR) Completion Signal Received Interrupt Mask More...
 
#define HSMCI_IMR_CSTOE   (0x1u << 23)
 (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask More...
 
#define HSMCI_IMR_DCRCE   (0x1u << 21)
 (HSMCI_IMR) Data CRC Error Interrupt Mask More...
 
#define HSMCI_IMR_DTIP   (0x1u << 4)
 (HSMCI_IMR) Data Transfer in Progress Interrupt Mask More...
 
#define HSMCI_IMR_DTOE   (0x1u << 22)
 (HSMCI_IMR) Data Time-out Error Interrupt Mask More...
 
#define HSMCI_IMR_FIFOEMPTY   (0x1u << 26)
 (HSMCI_IMR) FIFO Empty Interrupt Mask More...
 
#define HSMCI_IMR_NOTBUSY   (0x1u << 5)
 (HSMCI_IMR) Data Not Busy Interrupt Mask More...
 
#define HSMCI_IMR_OVRE   (0x1u << 30)
 (HSMCI_IMR) Overrun Interrupt Mask More...
 
#define HSMCI_IMR_RCRCE   (0x1u << 18)
 (HSMCI_IMR) Response CRC Error Interrupt Mask More...
 
#define HSMCI_IMR_RDIRE   (0x1u << 17)
 (HSMCI_IMR) Response Direction Error Interrupt Mask More...
 
#define HSMCI_IMR_RENDE   (0x1u << 19)
 (HSMCI_IMR) Response End Bit Error Interrupt Mask More...
 
#define HSMCI_IMR_RINDE   (0x1u << 16)
 (HSMCI_IMR) Response Index Error Interrupt Mask More...
 
#define HSMCI_IMR_RTOE   (0x1u << 20)
 (HSMCI_IMR) Response Time-out Error Interrupt Mask More...
 
#define HSMCI_IMR_RXRDY   (0x1u << 1)
 (HSMCI_IMR) Receiver Ready Interrupt Mask More...
 
#define HSMCI_IMR_SDIOIRQA   (0x1u << 8)
 (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask More...
 
#define HSMCI_IMR_SDIOWAIT   (0x1u << 12)
 (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask More...
 
#define HSMCI_IMR_TXRDY   (0x1u << 2)
 (HSMCI_IMR) Transmit Ready Interrupt Mask More...
 
#define HSMCI_IMR_UNRE   (0x1u << 31)
 (HSMCI_IMR) Underrun Interrupt Mask More...
 
#define HSMCI_IMR_XFRDONE   (0x1u << 27)
 (HSMCI_IMR) Transfer Done Interrupt Mask More...
 
#define HSMCI_MR_CLKDIV(value)   ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))
 
#define HSMCI_MR_CLKDIV_Msk   (0xffu << HSMCI_MR_CLKDIV_Pos)
 (HSMCI_MR) Clock Divider More...
 
#define HSMCI_MR_CLKDIV_Pos   0
 
#define HSMCI_MR_CLKODD   (0x1u << 16)
 (HSMCI_MR) Clock divider is odd More...
 
#define HSMCI_MR_FBYTE   (0x1u << 13)
 (HSMCI_MR) Force Byte Transfer More...
 
#define HSMCI_MR_PADV   (0x1u << 14)
 (HSMCI_MR) Padding Value More...
 
#define HSMCI_MR_PWSDIV(value)   ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))
 
#define HSMCI_MR_PWSDIV_Msk   (0x7u << HSMCI_MR_PWSDIV_Pos)
 (HSMCI_MR) Power Saving Divider More...
 
#define HSMCI_MR_PWSDIV_Pos   8
 
#define HSMCI_MR_RDPROOF   (0x1u << 11)
 (HSMCI_MR) Read Proof Enable More...
 
#define HSMCI_MR_WRPROOF   (0x1u << 12)
 (HSMCI_MR) Write Proof Enable More...
 
#define HSMCI_RDR_DATA_Msk   (0xffffffffu << HSMCI_RDR_DATA_Pos)
 (HSMCI_RDR) Data to Read More...
 
#define HSMCI_RDR_DATA_Pos   0
 
#define HSMCI_RSPR_RSP_Msk   (0xffffffffu << HSMCI_RSPR_RSP_Pos)
 (HSMCI_RSPR[4]) Response More...
 
#define HSMCI_RSPR_RSP_Pos   0
 
#define HSMCI_SDCR_SDCBUS(value)   ((HSMCI_SDCR_SDCBUS_Msk & ((value) << HSMCI_SDCR_SDCBUS_Pos)))
 
#define HSMCI_SDCR_SDCBUS_1   (0x0u << 6)
 (HSMCI_SDCR) 1 bit More...
 
#define HSMCI_SDCR_SDCBUS_4   (0x2u << 6)
 (HSMCI_SDCR) 4 bits More...
 
#define HSMCI_SDCR_SDCBUS_8   (0x3u << 6)
 (HSMCI_SDCR) 8 bits More...
 
#define HSMCI_SDCR_SDCBUS_Msk   (0x3u << HSMCI_SDCR_SDCBUS_Pos)
 (HSMCI_SDCR) SDCard/SDIO Bus Width More...
 
#define HSMCI_SDCR_SDCBUS_Pos   6
 
#define HSMCI_SDCR_SDCSEL(value)   ((HSMCI_SDCR_SDCSEL_Msk & ((value) << HSMCI_SDCR_SDCSEL_Pos)))
 
#define HSMCI_SDCR_SDCSEL_Msk   (0x3u << HSMCI_SDCR_SDCSEL_Pos)
 (HSMCI_SDCR) SDCard/SDIO Slot More...
 
#define HSMCI_SDCR_SDCSEL_Pos   0
 
#define HSMCI_SDCR_SDCSEL_SLOTA   (0x0u << 0)
 (HSMCI_SDCR) Slot A is selected. More...
 
#define HSMCI_SR_ACKRCV   (0x1u << 28)
 (HSMCI_SR) Boot Operation Acknowledge Received (cleared on read) More...
 
#define HSMCI_SR_ACKRCVE   (0x1u << 29)
 (HSMCI_SR) Boot Operation Acknowledge Error (cleared on read) More...
 
#define HSMCI_SR_BLKE   (0x1u << 3)
 (HSMCI_SR) Data Block Ended (cleared on read) More...
 
#define HSMCI_SR_BLKOVRE   (0x1u << 24)
 (HSMCI_SR) DMA Block Overrun Error (cleared on read) More...
 
#define HSMCI_SR_CMDRDY   (0x1u << 0)
 (HSMCI_SR) Command Ready (cleared by writing in HSMCI_CMDR) More...
 
#define HSMCI_SR_CSRCV   (0x1u << 13)
 (HSMCI_SR) CE-ATA Completion Signal Received (cleared on read) More...
 
#define HSMCI_SR_CSTOE   (0x1u << 23)
 (HSMCI_SR) Completion Signal Time-out Error (cleared on read) More...
 
#define HSMCI_SR_DCRCE   (0x1u << 21)
 (HSMCI_SR) Data CRC Error (cleared on read) More...
 
#define HSMCI_SR_DTIP   (0x1u << 4)
 (HSMCI_SR) Data Transfer in Progress (cleared at the end of CRC16 calculation) More...
 
#define HSMCI_SR_DTOE   (0x1u << 22)
 (HSMCI_SR) Data Time-out Error (cleared on read) More...
 
#define HSMCI_SR_FIFOEMPTY   (0x1u << 26)
 (HSMCI_SR) FIFO empty flag More...
 
#define HSMCI_SR_NOTBUSY   (0x1u << 5)
 (HSMCI_SR) HSMCI Not Busy More...
 
#define HSMCI_SR_OVRE   (0x1u << 30)
 (HSMCI_SR) Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) More...
 
#define HSMCI_SR_RCRCE   (0x1u << 18)
 (HSMCI_SR) Response CRC Error (cleared by writing in HSMCI_CMDR) More...
 
#define HSMCI_SR_RDIRE   (0x1u << 17)
 (HSMCI_SR) Response Direction Error (cleared by writing in HSMCI_CMDR) More...
 
#define HSMCI_SR_RENDE   (0x1u << 19)
 (HSMCI_SR) Response End Bit Error (cleared by writing in HSMCI_CMDR) More...
 
#define HSMCI_SR_RINDE   (0x1u << 16)
 (HSMCI_SR) Response Index Error (cleared by writing in HSMCI_CMDR) More...
 
#define HSMCI_SR_RTOE   (0x1u << 20)
 (HSMCI_SR) Response Time-out Error (cleared by writing in HSMCI_CMDR) More...
 
#define HSMCI_SR_RXRDY   (0x1u << 1)
 (HSMCI_SR) Receiver Ready (cleared by reading HSMCI_RDR) More...
 
#define HSMCI_SR_SDIOIRQA   (0x1u << 8)
 (HSMCI_SR) SDIO Interrupt for Slot A (cleared on read) More...
 
#define HSMCI_SR_SDIOWAIT   (0x1u << 12)
 (HSMCI_SR) SDIO Read Wait Operation Status More...
 
#define HSMCI_SR_TXRDY   (0x1u << 2)
 (HSMCI_SR) Transmit Ready (cleared by writing in HSMCI_TDR) More...
 
#define HSMCI_SR_UNRE   (0x1u << 31)
 (HSMCI_SR) Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) More...
 
#define HSMCI_SR_XFRDONE   (0x1u << 27)
 (HSMCI_SR) Transfer Done flag More...
 
#define HSMCI_TDR_DATA(value)   ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))
 
#define HSMCI_TDR_DATA_Msk   (0xffffffffu << HSMCI_TDR_DATA_Pos)
 (HSMCI_TDR) Data to Write More...
 
#define HSMCI_TDR_DATA_Pos   0
 
#define HSMCI_VERSION_MFN_Msk   (0x7u << HSMCI_VERSION_MFN_Pos)
 (HSMCI_VERSION) Metal Fix Number More...
 
#define HSMCI_VERSION_MFN_Pos   16
 
#define HSMCI_VERSION_VERSION_Msk   (0xfffu << HSMCI_VERSION_VERSION_Pos)
 (HSMCI_VERSION) Hardware Module Version More...
 
#define HSMCI_VERSION_VERSION_Pos   0
 
#define HSMCI_WPMR_WPEN   (0x1u << 0)
 (HSMCI_WPMR) Write Protect Enable More...
 
#define HSMCI_WPMR_WPKEY(value)   ((HSMCI_WPMR_WPKEY_Msk & ((value) << HSMCI_WPMR_WPKEY_Pos)))
 
#define HSMCI_WPMR_WPKEY_Msk   (0xffffffu << HSMCI_WPMR_WPKEY_Pos)
 (HSMCI_WPMR) Write Protect Key More...
 
#define HSMCI_WPMR_WPKEY_PASSWD   (0x4D4349u << 8)
 (HSMCI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. More...
 
#define HSMCI_WPMR_WPKEY_Pos   8
 
#define HSMCI_WPSR_WPVS   (0x1u << 0)
 (HSMCI_WPSR) Write Protection Violation Status More...
 
#define HSMCI_WPSR_WPVSRC_Msk   (0xffffu << HSMCI_WPSR_WPVSRC_Pos)
 (HSMCI_WPSR) Write Protection Violation Source More...
 
#define HSMCI_WPSR_WPVSRC_Pos   8
 

Detailed Description

SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface

Macro Definition Documentation

◆ HSMCI_ARGR_ARG

#define HSMCI_ARGR_ARG (   value)    ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))

◆ HSMCI_ARGR_ARG_Msk

#define HSMCI_ARGR_ARG_Msk   (0xffffffffu << HSMCI_ARGR_ARG_Pos)

(HSMCI_ARGR) Command Argument

Definition at line 120 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_ARGR_ARG_Pos

#define HSMCI_ARGR_ARG_Pos   0

◆ HSMCI_BLKR_BCNT

#define HSMCI_BLKR_BCNT (   value)    ((HSMCI_BLKR_BCNT_Msk & ((value) << HSMCI_BLKR_BCNT_Pos)))

◆ HSMCI_BLKR_BCNT_Msk

#define HSMCI_BLKR_BCNT_Msk   (0xffffu << HSMCI_BLKR_BCNT_Pos)

(HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count

Definition at line 179 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_BLKR_BCNT_Pos

#define HSMCI_BLKR_BCNT_Pos   0

◆ HSMCI_BLKR_BLKLEN

#define HSMCI_BLKR_BLKLEN (   value)    ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))

◆ HSMCI_BLKR_BLKLEN_Msk

#define HSMCI_BLKR_BLKLEN_Msk   (0xffffu << HSMCI_BLKR_BLKLEN_Pos)

(HSMCI_BLKR) Data Block Length

Definition at line 182 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_BLKR_BLKLEN_Pos

#define HSMCI_BLKR_BLKLEN_Pos   16

◆ HSMCI_CFG_FERRCTRL

#define HSMCI_CFG_FERRCTRL   (0x1u << 4)

(HSMCI_CFG) Flow Error flag reset control mode

Definition at line 321 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CFG_FIFOMODE

#define HSMCI_CFG_FIFOMODE   (0x1u << 0)

(HSMCI_CFG) HSMCI Internal FIFO control mode

Definition at line 320 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CFG_HSMODE

#define HSMCI_CFG_HSMODE   (0x1u << 8)

(HSMCI_CFG) High Speed Mode

Definition at line 322 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CFG_LSYNC

#define HSMCI_CFG_LSYNC   (0x1u << 12)

(HSMCI_CFG) Synchronize on the last block

Definition at line 323 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_ATACS

#define HSMCI_CMDR_ATACS   (0x1u << 26)

(HSMCI_CMDR) ATA with Command Completion Signal

Definition at line 173 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_ATACS_COMPLETION

#define HSMCI_CMDR_ATACS_COMPLETION   (0x1u << 26)

(HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR).

Definition at line 175 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_ATACS_NORMAL

#define HSMCI_CMDR_ATACS_NORMAL   (0x0u << 26)

(HSMCI_CMDR) Normal operation mode.

Definition at line 174 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_BOOT_ACK

#define HSMCI_CMDR_BOOT_ACK   (0x1u << 27)

(HSMCI_CMDR) Boot Operation Acknowledge

Definition at line 176 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_CMDNB

#define HSMCI_CMDR_CMDNB (   value)    ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))

◆ HSMCI_CMDR_CMDNB_Msk

#define HSMCI_CMDR_CMDNB_Msk   (0x3fu << HSMCI_CMDR_CMDNB_Pos)

(HSMCI_CMDR) Command Number

Definition at line 124 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_CMDNB_Pos

#define HSMCI_CMDR_CMDNB_Pos   0

◆ HSMCI_CMDR_IOSPCMD

#define HSMCI_CMDR_IOSPCMD (   value)    ((HSMCI_CMDR_IOSPCMD_Msk & ((value) << HSMCI_CMDR_IOSPCMD_Pos)))

◆ HSMCI_CMDR_IOSPCMD_Msk

#define HSMCI_CMDR_IOSPCMD_Msk   (0x3u << HSMCI_CMDR_IOSPCMD_Pos)

(HSMCI_CMDR) SDIO Special Command

Definition at line 168 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_IOSPCMD_Pos

#define HSMCI_CMDR_IOSPCMD_Pos   24

◆ HSMCI_CMDR_IOSPCMD_RESUME

#define HSMCI_CMDR_IOSPCMD_RESUME   (0x2u << 24)

(HSMCI_CMDR) SDIO Resume Command

Definition at line 172 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_IOSPCMD_STD

#define HSMCI_CMDR_IOSPCMD_STD   (0x0u << 24)

(HSMCI_CMDR) Not an SDIO Special Command

Definition at line 170 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_IOSPCMD_SUSPEND

#define HSMCI_CMDR_IOSPCMD_SUSPEND   (0x1u << 24)

(HSMCI_CMDR) SDIO Suspend Command

Definition at line 171 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_MAXLAT

#define HSMCI_CMDR_MAXLAT   (0x1u << 12)

(HSMCI_CMDR) Max Latency for Command to Response

Definition at line 147 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_MAXLAT_5

#define HSMCI_CMDR_MAXLAT_5   (0x0u << 12)

(HSMCI_CMDR) 5-cycle max latency.

Definition at line 148 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_MAXLAT_64

#define HSMCI_CMDR_MAXLAT_64   (0x1u << 12)

(HSMCI_CMDR) 64-cycle max latency.

Definition at line 149 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_OPDCMD

#define HSMCI_CMDR_OPDCMD   (0x1u << 11)

(HSMCI_CMDR) Open Drain Command

Definition at line 144 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_OPDCMD_OPENDRAIN

#define HSMCI_CMDR_OPDCMD_OPENDRAIN   (0x1u << 11)

(HSMCI_CMDR) Open drain command.

Definition at line 146 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_OPDCMD_PUSHPULL

#define HSMCI_CMDR_OPDCMD_PUSHPULL   (0x0u << 11)

(HSMCI_CMDR) Push pull command.

Definition at line 145 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_RSPTYP

#define HSMCI_CMDR_RSPTYP (   value)    ((HSMCI_CMDR_RSPTYP_Msk & ((value) << HSMCI_CMDR_RSPTYP_Pos)))

◆ HSMCI_CMDR_RSPTYP_136_BIT

#define HSMCI_CMDR_RSPTYP_136_BIT   (0x2u << 6)

(HSMCI_CMDR) 136-bit response

Definition at line 131 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_RSPTYP_48_BIT

#define HSMCI_CMDR_RSPTYP_48_BIT   (0x1u << 6)

(HSMCI_CMDR) 48-bit response

Definition at line 130 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_RSPTYP_Msk

#define HSMCI_CMDR_RSPTYP_Msk   (0x3u << HSMCI_CMDR_RSPTYP_Pos)

(HSMCI_CMDR) Response Type

Definition at line 127 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_RSPTYP_NORESP

#define HSMCI_CMDR_RSPTYP_NORESP   (0x0u << 6)

(HSMCI_CMDR) No response

Definition at line 129 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_RSPTYP_Pos

#define HSMCI_CMDR_RSPTYP_Pos   6

◆ HSMCI_CMDR_RSPTYP_R1B

#define HSMCI_CMDR_RSPTYP_R1B   (0x3u << 6)

(HSMCI_CMDR) R1b response type

Definition at line 132 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_SPCMD

#define HSMCI_CMDR_SPCMD (   value)    ((HSMCI_CMDR_SPCMD_Msk & ((value) << HSMCI_CMDR_SPCMD_Pos)))

◆ HSMCI_CMDR_SPCMD_BOR

#define HSMCI_CMDR_SPCMD_BOR   (0x6u << 8)

(HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly.

Definition at line 142 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_SPCMD_CE_ATA

#define HSMCI_CMDR_SPCMD_CE_ATA   (0x3u << 8)

(HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line.

Definition at line 139 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_SPCMD_EBO

#define HSMCI_CMDR_SPCMD_EBO   (0x7u << 8)

(HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode.

Definition at line 143 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_SPCMD_INIT

#define HSMCI_CMDR_SPCMD_INIT   (0x1u << 8)

(HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence.

Definition at line 137 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_SPCMD_IT_CMD

#define HSMCI_CMDR_SPCMD_IT_CMD   (0x4u << 8)

(HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40).

Definition at line 140 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_SPCMD_IT_RESP

#define HSMCI_CMDR_SPCMD_IT_RESP   (0x5u << 8)

(HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40).

Definition at line 141 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_SPCMD_Msk

#define HSMCI_CMDR_SPCMD_Msk   (0x7u << HSMCI_CMDR_SPCMD_Pos)

(HSMCI_CMDR) Special Command

Definition at line 134 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_SPCMD_Pos

#define HSMCI_CMDR_SPCMD_Pos   8

◆ HSMCI_CMDR_SPCMD_STD

#define HSMCI_CMDR_SPCMD_STD   (0x0u << 8)

(HSMCI_CMDR) Not a special CMD.

Definition at line 136 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_SPCMD_SYNC

#define HSMCI_CMDR_SPCMD_SYNC   (0x2u << 8)

(HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command.

Definition at line 138 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_TRCMD

#define HSMCI_CMDR_TRCMD (   value)    ((HSMCI_CMDR_TRCMD_Msk & ((value) << HSMCI_CMDR_TRCMD_Pos)))

◆ HSMCI_CMDR_TRCMD_Msk

#define HSMCI_CMDR_TRCMD_Msk   (0x3u << HSMCI_CMDR_TRCMD_Pos)

(HSMCI_CMDR) Transfer Command

Definition at line 151 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_TRCMD_NO_DATA

#define HSMCI_CMDR_TRCMD_NO_DATA   (0x0u << 16)

(HSMCI_CMDR) No data transfer

Definition at line 153 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_TRCMD_Pos

#define HSMCI_CMDR_TRCMD_Pos   16

◆ HSMCI_CMDR_TRCMD_START_DATA

#define HSMCI_CMDR_TRCMD_START_DATA   (0x1u << 16)

(HSMCI_CMDR) Start data transfer

Definition at line 154 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_TRCMD_STOP_DATA

#define HSMCI_CMDR_TRCMD_STOP_DATA   (0x2u << 16)

(HSMCI_CMDR) Stop data transfer

Definition at line 155 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_TRDIR

#define HSMCI_CMDR_TRDIR   (0x1u << 18)

(HSMCI_CMDR) Transfer Direction

Definition at line 156 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_TRDIR_READ

#define HSMCI_CMDR_TRDIR_READ   (0x1u << 18)

(HSMCI_CMDR) Read.

Definition at line 158 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_TRDIR_WRITE

#define HSMCI_CMDR_TRDIR_WRITE   (0x0u << 18)

(HSMCI_CMDR) Write.

Definition at line 157 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_TRTYP

#define HSMCI_CMDR_TRTYP (   value)    ((HSMCI_CMDR_TRTYP_Msk & ((value) << HSMCI_CMDR_TRTYP_Pos)))

◆ HSMCI_CMDR_TRTYP_BLOCK

#define HSMCI_CMDR_TRTYP_BLOCK   (0x5u << 19)

(HSMCI_CMDR) SDIO Block

Definition at line 166 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_TRTYP_BYTE

#define HSMCI_CMDR_TRTYP_BYTE   (0x4u << 19)

(HSMCI_CMDR) SDIO Byte

Definition at line 165 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_TRTYP_Msk

#define HSMCI_CMDR_TRTYP_Msk   (0x7u << HSMCI_CMDR_TRTYP_Pos)

(HSMCI_CMDR) Transfer Type

Definition at line 160 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_TRTYP_MULTIPLE

#define HSMCI_CMDR_TRTYP_MULTIPLE   (0x1u << 19)

(HSMCI_CMDR) MMC/SD Card Multiple Block

Definition at line 163 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_TRTYP_Pos

#define HSMCI_CMDR_TRTYP_Pos   19

◆ HSMCI_CMDR_TRTYP_SINGLE

#define HSMCI_CMDR_TRTYP_SINGLE   (0x0u << 19)

(HSMCI_CMDR) MMC/SD Card Single Block

Definition at line 162 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CMDR_TRTYP_STREAM

#define HSMCI_CMDR_TRTYP_STREAM   (0x2u << 19)

(HSMCI_CMDR) MMC Stream

Definition at line 164 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CR_MCIDIS

#define HSMCI_CR_MCIDIS   (0x1u << 1)

(HSMCI_CR) Multi-Media Interface Disable

Definition at line 76 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CR_MCIEN

#define HSMCI_CR_MCIEN   (0x1u << 0)

(HSMCI_CR) Multi-Media Interface Enable

Definition at line 75 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CR_PWSDIS

#define HSMCI_CR_PWSDIS   (0x1u << 3)

(HSMCI_CR) Power Save Mode Disable

Definition at line 78 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CR_PWSEN

#define HSMCI_CR_PWSEN   (0x1u << 2)

(HSMCI_CR) Power Save Mode Enable

Definition at line 77 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CR_SWRST

#define HSMCI_CR_SWRST   (0x1u << 7)

(HSMCI_CR) Software Reset

Definition at line 79 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CSTOR_CSTOCYC

#define HSMCI_CSTOR_CSTOCYC (   value)    ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))

◆ HSMCI_CSTOR_CSTOCYC_Msk

#define HSMCI_CSTOR_CSTOCYC_Msk   (0xfu << HSMCI_CSTOR_CSTOCYC_Pos)

(HSMCI_CSTOR) Completion Signal Timeout Cycle Number

Definition at line 186 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CSTOR_CSTOCYC_Pos

#define HSMCI_CSTOR_CSTOCYC_Pos   0

◆ HSMCI_CSTOR_CSTOMUL

#define HSMCI_CSTOR_CSTOMUL (   value)    ((HSMCI_CSTOR_CSTOMUL_Msk & ((value) << HSMCI_CSTOR_CSTOMUL_Pos)))

◆ HSMCI_CSTOR_CSTOMUL_1

#define HSMCI_CSTOR_CSTOMUL_1   (0x0u << 4)

(HSMCI_CSTOR) CSTOCYC x 1

Definition at line 191 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CSTOR_CSTOMUL_1024

#define HSMCI_CSTOR_CSTOMUL_1024   (0x4u << 4)

(HSMCI_CSTOR) CSTOCYC x 1024

Definition at line 195 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CSTOR_CSTOMUL_1048576

#define HSMCI_CSTOR_CSTOMUL_1048576   (0x7u << 4)

(HSMCI_CSTOR) CSTOCYC x 1048576

Definition at line 198 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CSTOR_CSTOMUL_128

#define HSMCI_CSTOR_CSTOMUL_128   (0x2u << 4)

(HSMCI_CSTOR) CSTOCYC x 128

Definition at line 193 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CSTOR_CSTOMUL_16

#define HSMCI_CSTOR_CSTOMUL_16   (0x1u << 4)

(HSMCI_CSTOR) CSTOCYC x 16

Definition at line 192 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CSTOR_CSTOMUL_256

#define HSMCI_CSTOR_CSTOMUL_256   (0x3u << 4)

(HSMCI_CSTOR) CSTOCYC x 256

Definition at line 194 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CSTOR_CSTOMUL_4096

#define HSMCI_CSTOR_CSTOMUL_4096   (0x5u << 4)

(HSMCI_CSTOR) CSTOCYC x 4096

Definition at line 196 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CSTOR_CSTOMUL_65536

#define HSMCI_CSTOR_CSTOMUL_65536   (0x6u << 4)

(HSMCI_CSTOR) CSTOCYC x 65536

Definition at line 197 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CSTOR_CSTOMUL_Msk

#define HSMCI_CSTOR_CSTOMUL_Msk   (0x7u << HSMCI_CSTOR_CSTOMUL_Pos)

(HSMCI_CSTOR) Completion Signal Timeout Multiplier

Definition at line 189 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_CSTOR_CSTOMUL_Pos

#define HSMCI_CSTOR_CSTOMUL_Pos   4

◆ HSMCI_DMA_CHKSIZE

#define HSMCI_DMA_CHKSIZE (   value)    ((HSMCI_DMA_CHKSIZE_Msk & ((value) << HSMCI_DMA_CHKSIZE_Pos)))

◆ HSMCI_DMA_CHKSIZE_1

#define HSMCI_DMA_CHKSIZE_1   (0x0u << 4)

(HSMCI_DMA) 1 data available

Definition at line 313 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_DMA_CHKSIZE_16

#define HSMCI_DMA_CHKSIZE_16   (0x4u << 4)

(HSMCI_DMA) 16 data available

Definition at line 317 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_DMA_CHKSIZE_2

#define HSMCI_DMA_CHKSIZE_2   (0x1u << 4)

(HSMCI_DMA) 2 data available

Definition at line 314 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_DMA_CHKSIZE_4

#define HSMCI_DMA_CHKSIZE_4   (0x2u << 4)

(HSMCI_DMA) 4 data available

Definition at line 315 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_DMA_CHKSIZE_8

#define HSMCI_DMA_CHKSIZE_8   (0x3u << 4)

(HSMCI_DMA) 8 data available

Definition at line 316 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_DMA_CHKSIZE_Msk

#define HSMCI_DMA_CHKSIZE_Msk   (0x7u << HSMCI_DMA_CHKSIZE_Pos)

(HSMCI_DMA) DMA Channel Read and Write Chunk Size

Definition at line 311 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_DMA_CHKSIZE_Pos

#define HSMCI_DMA_CHKSIZE_Pos   4

◆ HSMCI_DMA_DMAEN

#define HSMCI_DMA_DMAEN   (0x1u << 8)

(HSMCI_DMA) DMA Hardware Handshaking Enable

Definition at line 318 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_DTOR_DTOCYC

#define HSMCI_DTOR_DTOCYC (   value)    ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))

Definition at line 95 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_DTOR_DTOCYC_Msk

#define HSMCI_DTOR_DTOCYC_Msk   (0xfu << HSMCI_DTOR_DTOCYC_Pos)

(HSMCI_DTOR) Data Timeout Cycle Number

Definition at line 94 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_DTOR_DTOCYC_Pos

#define HSMCI_DTOR_DTOCYC_Pos   0

Definition at line 93 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_DTOR_DTOMUL

#define HSMCI_DTOR_DTOMUL (   value)    ((HSMCI_DTOR_DTOMUL_Msk & ((value) << HSMCI_DTOR_DTOMUL_Pos)))

Definition at line 98 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_DTOR_DTOMUL_1

#define HSMCI_DTOR_DTOMUL_1   (0x0u << 4)

(HSMCI_DTOR) DTOCYC

Definition at line 99 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_DTOR_DTOMUL_1024

#define HSMCI_DTOR_DTOMUL_1024   (0x4u << 4)

(HSMCI_DTOR) DTOCYC x 1024

Definition at line 103 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_DTOR_DTOMUL_1048576

#define HSMCI_DTOR_DTOMUL_1048576   (0x7u << 4)

(HSMCI_DTOR) DTOCYC x 1048576

Definition at line 106 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_DTOR_DTOMUL_128

#define HSMCI_DTOR_DTOMUL_128   (0x2u << 4)

(HSMCI_DTOR) DTOCYC x 128

Definition at line 101 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_DTOR_DTOMUL_16

#define HSMCI_DTOR_DTOMUL_16   (0x1u << 4)

(HSMCI_DTOR) DTOCYC x 16

Definition at line 100 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_DTOR_DTOMUL_256

#define HSMCI_DTOR_DTOMUL_256   (0x3u << 4)

(HSMCI_DTOR) DTOCYC x 256

Definition at line 102 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_DTOR_DTOMUL_4096

#define HSMCI_DTOR_DTOMUL_4096   (0x5u << 4)

(HSMCI_DTOR) DTOCYC x 4096

Definition at line 104 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_DTOR_DTOMUL_65536

#define HSMCI_DTOR_DTOMUL_65536   (0x6u << 4)

(HSMCI_DTOR) DTOCYC x 65536

Definition at line 105 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_DTOR_DTOMUL_Msk

#define HSMCI_DTOR_DTOMUL_Msk   (0x7u << HSMCI_DTOR_DTOMUL_Pos)

(HSMCI_DTOR) Data Timeout Multiplier

Definition at line 97 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_DTOR_DTOMUL_Pos

#define HSMCI_DTOR_DTOMUL_Pos   4

Definition at line 96 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_FIFO_DATA

#define HSMCI_FIFO_DATA (   value)    ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos)))

◆ HSMCI_FIFO_DATA_Msk

#define HSMCI_FIFO_DATA_Msk   (0xffffffffu << HSMCI_FIFO_DATA_Pos)

(HSMCI_FIFO[256]) Data to Read or Data to Write

Definition at line 341 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_FIFO_DATA_Pos

#define HSMCI_FIFO_DATA_Pos   0

◆ HSMCI_IDR_ACKRCV

#define HSMCI_IDR_ACKRCV   (0x1u << 28)

(HSMCI_IDR) Boot Acknowledge Interrupt Disable

Definition at line 280 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IDR_ACKRCVE

#define HSMCI_IDR_ACKRCVE   (0x1u << 29)

(HSMCI_IDR) Boot Acknowledge Error Interrupt Disable

Definition at line 281 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IDR_BLKE

#define HSMCI_IDR_BLKE   (0x1u << 3)

(HSMCI_IDR) Data Block Ended Interrupt Disable

Definition at line 263 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IDR_BLKOVRE

#define HSMCI_IDR_BLKOVRE   (0x1u << 24)

(HSMCI_IDR) DMA Block Overrun Error Interrupt Disable

Definition at line 277 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IDR_CMDRDY

#define HSMCI_IDR_CMDRDY   (0x1u << 0)

(HSMCI_IDR) Command Ready Interrupt Disable

Definition at line 260 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IDR_CSRCV

#define HSMCI_IDR_CSRCV   (0x1u << 13)

(HSMCI_IDR) Completion Signal received interrupt Disable

Definition at line 268 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IDR_CSTOE

#define HSMCI_IDR_CSTOE   (0x1u << 23)

(HSMCI_IDR) Completion Signal Time out Error Interrupt Disable

Definition at line 276 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IDR_DCRCE

#define HSMCI_IDR_DCRCE   (0x1u << 21)

(HSMCI_IDR) Data CRC Error Interrupt Disable

Definition at line 274 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IDR_DTIP

#define HSMCI_IDR_DTIP   (0x1u << 4)

(HSMCI_IDR) Data Transfer in Progress Interrupt Disable

Definition at line 264 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IDR_DTOE

#define HSMCI_IDR_DTOE   (0x1u << 22)

(HSMCI_IDR) Data Time-out Error Interrupt Disable

Definition at line 275 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IDR_FIFOEMPTY

#define HSMCI_IDR_FIFOEMPTY   (0x1u << 26)

(HSMCI_IDR) FIFO empty Interrupt Disable

Definition at line 278 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IDR_NOTBUSY

#define HSMCI_IDR_NOTBUSY   (0x1u << 5)

(HSMCI_IDR) Data Not Busy Interrupt Disable

Definition at line 265 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IDR_OVRE

#define HSMCI_IDR_OVRE   (0x1u << 30)

(HSMCI_IDR) Overrun Interrupt Disable

Definition at line 282 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IDR_RCRCE

#define HSMCI_IDR_RCRCE   (0x1u << 18)

(HSMCI_IDR) Response CRC Error Interrupt Disable

Definition at line 271 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IDR_RDIRE

#define HSMCI_IDR_RDIRE   (0x1u << 17)

(HSMCI_IDR) Response Direction Error Interrupt Disable

Definition at line 270 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IDR_RENDE

#define HSMCI_IDR_RENDE   (0x1u << 19)

(HSMCI_IDR) Response End Bit Error Interrupt Disable

Definition at line 272 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IDR_RINDE

#define HSMCI_IDR_RINDE   (0x1u << 16)

(HSMCI_IDR) Response Index Error Interrupt Disable

Definition at line 269 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IDR_RTOE

#define HSMCI_IDR_RTOE   (0x1u << 20)

(HSMCI_IDR) Response Time-out Error Interrupt Disable

Definition at line 273 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IDR_RXRDY

#define HSMCI_IDR_RXRDY   (0x1u << 1)

(HSMCI_IDR) Receiver Ready Interrupt Disable

Definition at line 261 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IDR_SDIOIRQA

#define HSMCI_IDR_SDIOIRQA   (0x1u << 8)

(HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable

Definition at line 266 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IDR_SDIOWAIT

#define HSMCI_IDR_SDIOWAIT   (0x1u << 12)

(HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable

Definition at line 267 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IDR_TXRDY

#define HSMCI_IDR_TXRDY   (0x1u << 2)

(HSMCI_IDR) Transmit Ready Interrupt Disable

Definition at line 262 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IDR_UNRE

#define HSMCI_IDR_UNRE   (0x1u << 31)

(HSMCI_IDR) Underrun Interrupt Disable

Definition at line 283 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IDR_XFRDONE

#define HSMCI_IDR_XFRDONE   (0x1u << 27)

(HSMCI_IDR) Transfer Done Interrupt Disable

Definition at line 279 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IER_ACKRCV

#define HSMCI_IER_ACKRCV   (0x1u << 28)

(HSMCI_IER) Boot Acknowledge Interrupt Enable

Definition at line 255 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IER_ACKRCVE

#define HSMCI_IER_ACKRCVE   (0x1u << 29)

(HSMCI_IER) Boot Acknowledge Error Interrupt Enable

Definition at line 256 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IER_BLKE

#define HSMCI_IER_BLKE   (0x1u << 3)

(HSMCI_IER) Data Block Ended Interrupt Enable

Definition at line 238 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IER_BLKOVRE

#define HSMCI_IER_BLKOVRE   (0x1u << 24)

(HSMCI_IER) DMA Block Overrun Error Interrupt Enable

Definition at line 252 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IER_CMDRDY

#define HSMCI_IER_CMDRDY   (0x1u << 0)

(HSMCI_IER) Command Ready Interrupt Enable

Definition at line 235 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IER_CSRCV

#define HSMCI_IER_CSRCV   (0x1u << 13)

(HSMCI_IER) Completion Signal Received Interrupt Enable

Definition at line 243 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IER_CSTOE

#define HSMCI_IER_CSTOE   (0x1u << 23)

(HSMCI_IER) Completion Signal Timeout Error Interrupt Enable

Definition at line 251 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IER_DCRCE

#define HSMCI_IER_DCRCE   (0x1u << 21)

(HSMCI_IER) Data CRC Error Interrupt Enable

Definition at line 249 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IER_DTIP

#define HSMCI_IER_DTIP   (0x1u << 4)

(HSMCI_IER) Data Transfer in Progress Interrupt Enable

Definition at line 239 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IER_DTOE

#define HSMCI_IER_DTOE   (0x1u << 22)

(HSMCI_IER) Data Time-out Error Interrupt Enable

Definition at line 250 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IER_FIFOEMPTY

#define HSMCI_IER_FIFOEMPTY   (0x1u << 26)

(HSMCI_IER) FIFO empty Interrupt enable

Definition at line 253 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IER_NOTBUSY

#define HSMCI_IER_NOTBUSY   (0x1u << 5)

(HSMCI_IER) Data Not Busy Interrupt Enable

Definition at line 240 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IER_OVRE

#define HSMCI_IER_OVRE   (0x1u << 30)

(HSMCI_IER) Overrun Interrupt Enable

Definition at line 257 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IER_RCRCE

#define HSMCI_IER_RCRCE   (0x1u << 18)

(HSMCI_IER) Response CRC Error Interrupt Enable

Definition at line 246 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IER_RDIRE

#define HSMCI_IER_RDIRE   (0x1u << 17)

(HSMCI_IER) Response Direction Error Interrupt Enable

Definition at line 245 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IER_RENDE

#define HSMCI_IER_RENDE   (0x1u << 19)

(HSMCI_IER) Response End Bit Error Interrupt Enable

Definition at line 247 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IER_RINDE

#define HSMCI_IER_RINDE   (0x1u << 16)

(HSMCI_IER) Response Index Error Interrupt Enable

Definition at line 244 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IER_RTOE

#define HSMCI_IER_RTOE   (0x1u << 20)

(HSMCI_IER) Response Time-out Error Interrupt Enable

Definition at line 248 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IER_RXRDY

#define HSMCI_IER_RXRDY   (0x1u << 1)

(HSMCI_IER) Receiver Ready Interrupt Enable

Definition at line 236 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IER_SDIOIRQA

#define HSMCI_IER_SDIOIRQA   (0x1u << 8)

(HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable

Definition at line 241 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IER_SDIOWAIT

#define HSMCI_IER_SDIOWAIT   (0x1u << 12)

(HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable

Definition at line 242 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IER_TXRDY

#define HSMCI_IER_TXRDY   (0x1u << 2)

(HSMCI_IER) Transmit Ready Interrupt Enable

Definition at line 237 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IER_UNRE

#define HSMCI_IER_UNRE   (0x1u << 31)

(HSMCI_IER) Underrun Interrupt Enable

Definition at line 258 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IER_XFRDONE

#define HSMCI_IER_XFRDONE   (0x1u << 27)

(HSMCI_IER) Transfer Done Interrupt enable

Definition at line 254 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IMR_ACKRCV

#define HSMCI_IMR_ACKRCV   (0x1u << 28)

(HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask

Definition at line 305 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IMR_ACKRCVE

#define HSMCI_IMR_ACKRCVE   (0x1u << 29)

(HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask

Definition at line 306 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IMR_BLKE

#define HSMCI_IMR_BLKE   (0x1u << 3)

(HSMCI_IMR) Data Block Ended Interrupt Mask

Definition at line 288 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IMR_BLKOVRE

#define HSMCI_IMR_BLKOVRE   (0x1u << 24)

(HSMCI_IMR) DMA Block Overrun Error Interrupt Mask

Definition at line 302 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IMR_CMDRDY

#define HSMCI_IMR_CMDRDY   (0x1u << 0)

(HSMCI_IMR) Command Ready Interrupt Mask

Definition at line 285 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IMR_CSRCV

#define HSMCI_IMR_CSRCV   (0x1u << 13)

(HSMCI_IMR) Completion Signal Received Interrupt Mask

Definition at line 293 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IMR_CSTOE

#define HSMCI_IMR_CSTOE   (0x1u << 23)

(HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask

Definition at line 301 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IMR_DCRCE

#define HSMCI_IMR_DCRCE   (0x1u << 21)

(HSMCI_IMR) Data CRC Error Interrupt Mask

Definition at line 299 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IMR_DTIP

#define HSMCI_IMR_DTIP   (0x1u << 4)

(HSMCI_IMR) Data Transfer in Progress Interrupt Mask

Definition at line 289 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IMR_DTOE

#define HSMCI_IMR_DTOE   (0x1u << 22)

(HSMCI_IMR) Data Time-out Error Interrupt Mask

Definition at line 300 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IMR_FIFOEMPTY

#define HSMCI_IMR_FIFOEMPTY   (0x1u << 26)

(HSMCI_IMR) FIFO Empty Interrupt Mask

Definition at line 303 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IMR_NOTBUSY

#define HSMCI_IMR_NOTBUSY   (0x1u << 5)

(HSMCI_IMR) Data Not Busy Interrupt Mask

Definition at line 290 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IMR_OVRE

#define HSMCI_IMR_OVRE   (0x1u << 30)

(HSMCI_IMR) Overrun Interrupt Mask

Definition at line 307 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IMR_RCRCE

#define HSMCI_IMR_RCRCE   (0x1u << 18)

(HSMCI_IMR) Response CRC Error Interrupt Mask

Definition at line 296 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IMR_RDIRE

#define HSMCI_IMR_RDIRE   (0x1u << 17)

(HSMCI_IMR) Response Direction Error Interrupt Mask

Definition at line 295 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IMR_RENDE

#define HSMCI_IMR_RENDE   (0x1u << 19)

(HSMCI_IMR) Response End Bit Error Interrupt Mask

Definition at line 297 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IMR_RINDE

#define HSMCI_IMR_RINDE   (0x1u << 16)

(HSMCI_IMR) Response Index Error Interrupt Mask

Definition at line 294 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IMR_RTOE

#define HSMCI_IMR_RTOE   (0x1u << 20)

(HSMCI_IMR) Response Time-out Error Interrupt Mask

Definition at line 298 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IMR_RXRDY

#define HSMCI_IMR_RXRDY   (0x1u << 1)

(HSMCI_IMR) Receiver Ready Interrupt Mask

Definition at line 286 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IMR_SDIOIRQA

#define HSMCI_IMR_SDIOIRQA   (0x1u << 8)

(HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask

Definition at line 291 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IMR_SDIOWAIT

#define HSMCI_IMR_SDIOWAIT   (0x1u << 12)

(HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask

Definition at line 292 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IMR_TXRDY

#define HSMCI_IMR_TXRDY   (0x1u << 2)

(HSMCI_IMR) Transmit Ready Interrupt Mask

Definition at line 287 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IMR_UNRE

#define HSMCI_IMR_UNRE   (0x1u << 31)

(HSMCI_IMR) Underrun Interrupt Mask

Definition at line 308 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_IMR_XFRDONE

#define HSMCI_IMR_XFRDONE   (0x1u << 27)

(HSMCI_IMR) Transfer Done Interrupt Mask

Definition at line 304 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_MR_CLKDIV

#define HSMCI_MR_CLKDIV (   value)    ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))

Definition at line 83 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_MR_CLKDIV_Msk

#define HSMCI_MR_CLKDIV_Msk   (0xffu << HSMCI_MR_CLKDIV_Pos)

(HSMCI_MR) Clock Divider

Definition at line 82 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_MR_CLKDIV_Pos

#define HSMCI_MR_CLKDIV_Pos   0

Definition at line 81 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_MR_CLKODD

#define HSMCI_MR_CLKODD   (0x1u << 16)

(HSMCI_MR) Clock divider is odd

Definition at line 91 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_MR_FBYTE

#define HSMCI_MR_FBYTE   (0x1u << 13)

(HSMCI_MR) Force Byte Transfer

Definition at line 89 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_MR_PADV

#define HSMCI_MR_PADV   (0x1u << 14)

(HSMCI_MR) Padding Value

Definition at line 90 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_MR_PWSDIV

#define HSMCI_MR_PWSDIV (   value)    ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))

Definition at line 86 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_MR_PWSDIV_Msk

#define HSMCI_MR_PWSDIV_Msk   (0x7u << HSMCI_MR_PWSDIV_Pos)

(HSMCI_MR) Power Saving Divider

Definition at line 85 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_MR_PWSDIV_Pos

#define HSMCI_MR_PWSDIV_Pos   8

Definition at line 84 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_MR_RDPROOF

#define HSMCI_MR_RDPROOF   (0x1u << 11)

(HSMCI_MR) Read Proof Enable

Definition at line 87 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_MR_WRPROOF

#define HSMCI_MR_WRPROOF   (0x1u << 12)

(HSMCI_MR) Write Proof Enable

Definition at line 88 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_RDR_DATA_Msk

#define HSMCI_RDR_DATA_Msk   (0xffffffffu << HSMCI_RDR_DATA_Pos)

(HSMCI_RDR) Data to Read

Definition at line 204 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_RDR_DATA_Pos

#define HSMCI_RDR_DATA_Pos   0

◆ HSMCI_RSPR_RSP_Msk

#define HSMCI_RSPR_RSP_Msk   (0xffffffffu << HSMCI_RSPR_RSP_Pos)

(HSMCI_RSPR[4]) Response

Definition at line 201 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_RSPR_RSP_Pos

#define HSMCI_RSPR_RSP_Pos   0

◆ HSMCI_SDCR_SDCBUS

#define HSMCI_SDCR_SDCBUS (   value)    ((HSMCI_SDCR_SDCBUS_Msk & ((value) << HSMCI_SDCR_SDCBUS_Pos)))

◆ HSMCI_SDCR_SDCBUS_1

#define HSMCI_SDCR_SDCBUS_1   (0x0u << 6)

(HSMCI_SDCR) 1 bit

Definition at line 115 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SDCR_SDCBUS_4

#define HSMCI_SDCR_SDCBUS_4   (0x2u << 6)

(HSMCI_SDCR) 4 bits

Definition at line 116 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SDCR_SDCBUS_8

#define HSMCI_SDCR_SDCBUS_8   (0x3u << 6)

(HSMCI_SDCR) 8 bits

Definition at line 117 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SDCR_SDCBUS_Msk

#define HSMCI_SDCR_SDCBUS_Msk   (0x3u << HSMCI_SDCR_SDCBUS_Pos)

(HSMCI_SDCR) SDCard/SDIO Bus Width

Definition at line 113 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SDCR_SDCBUS_Pos

#define HSMCI_SDCR_SDCBUS_Pos   6

◆ HSMCI_SDCR_SDCSEL

#define HSMCI_SDCR_SDCSEL (   value)    ((HSMCI_SDCR_SDCSEL_Msk & ((value) << HSMCI_SDCR_SDCSEL_Pos)))

◆ HSMCI_SDCR_SDCSEL_Msk

#define HSMCI_SDCR_SDCSEL_Msk   (0x3u << HSMCI_SDCR_SDCSEL_Pos)

(HSMCI_SDCR) SDCard/SDIO Slot

Definition at line 109 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SDCR_SDCSEL_Pos

#define HSMCI_SDCR_SDCSEL_Pos   0

◆ HSMCI_SDCR_SDCSEL_SLOTA

#define HSMCI_SDCR_SDCSEL_SLOTA   (0x0u << 0)

(HSMCI_SDCR) Slot A is selected.

Definition at line 111 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SR_ACKRCV

#define HSMCI_SR_ACKRCV   (0x1u << 28)

(HSMCI_SR) Boot Operation Acknowledge Received (cleared on read)

Definition at line 230 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SR_ACKRCVE

#define HSMCI_SR_ACKRCVE   (0x1u << 29)

(HSMCI_SR) Boot Operation Acknowledge Error (cleared on read)

Definition at line 231 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SR_BLKE

#define HSMCI_SR_BLKE   (0x1u << 3)

(HSMCI_SR) Data Block Ended (cleared on read)

Definition at line 213 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SR_BLKOVRE

#define HSMCI_SR_BLKOVRE   (0x1u << 24)

(HSMCI_SR) DMA Block Overrun Error (cleared on read)

Definition at line 227 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SR_CMDRDY

#define HSMCI_SR_CMDRDY   (0x1u << 0)

(HSMCI_SR) Command Ready (cleared by writing in HSMCI_CMDR)

Definition at line 210 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SR_CSRCV

#define HSMCI_SR_CSRCV   (0x1u << 13)

(HSMCI_SR) CE-ATA Completion Signal Received (cleared on read)

Definition at line 218 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SR_CSTOE

#define HSMCI_SR_CSTOE   (0x1u << 23)

(HSMCI_SR) Completion Signal Time-out Error (cleared on read)

Definition at line 226 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SR_DCRCE

#define HSMCI_SR_DCRCE   (0x1u << 21)

(HSMCI_SR) Data CRC Error (cleared on read)

Definition at line 224 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SR_DTIP

#define HSMCI_SR_DTIP   (0x1u << 4)

(HSMCI_SR) Data Transfer in Progress (cleared at the end of CRC16 calculation)

Definition at line 214 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SR_DTOE

#define HSMCI_SR_DTOE   (0x1u << 22)

(HSMCI_SR) Data Time-out Error (cleared on read)

Definition at line 225 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SR_FIFOEMPTY

#define HSMCI_SR_FIFOEMPTY   (0x1u << 26)

(HSMCI_SR) FIFO empty flag

Definition at line 228 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SR_NOTBUSY

#define HSMCI_SR_NOTBUSY   (0x1u << 5)

(HSMCI_SR) HSMCI Not Busy

Definition at line 215 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SR_OVRE

#define HSMCI_SR_OVRE   (0x1u << 30)

(HSMCI_SR) Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0)

Definition at line 232 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SR_RCRCE

#define HSMCI_SR_RCRCE   (0x1u << 18)

(HSMCI_SR) Response CRC Error (cleared by writing in HSMCI_CMDR)

Definition at line 221 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SR_RDIRE

#define HSMCI_SR_RDIRE   (0x1u << 17)

(HSMCI_SR) Response Direction Error (cleared by writing in HSMCI_CMDR)

Definition at line 220 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SR_RENDE

#define HSMCI_SR_RENDE   (0x1u << 19)

(HSMCI_SR) Response End Bit Error (cleared by writing in HSMCI_CMDR)

Definition at line 222 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SR_RINDE

#define HSMCI_SR_RINDE   (0x1u << 16)

(HSMCI_SR) Response Index Error (cleared by writing in HSMCI_CMDR)

Definition at line 219 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SR_RTOE

#define HSMCI_SR_RTOE   (0x1u << 20)

(HSMCI_SR) Response Time-out Error (cleared by writing in HSMCI_CMDR)

Definition at line 223 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SR_RXRDY

#define HSMCI_SR_RXRDY   (0x1u << 1)

(HSMCI_SR) Receiver Ready (cleared by reading HSMCI_RDR)

Definition at line 211 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SR_SDIOIRQA

#define HSMCI_SR_SDIOIRQA   (0x1u << 8)

(HSMCI_SR) SDIO Interrupt for Slot A (cleared on read)

Definition at line 216 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SR_SDIOWAIT

#define HSMCI_SR_SDIOWAIT   (0x1u << 12)

(HSMCI_SR) SDIO Read Wait Operation Status

Definition at line 217 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SR_TXRDY

#define HSMCI_SR_TXRDY   (0x1u << 2)

(HSMCI_SR) Transmit Ready (cleared by writing in HSMCI_TDR)

Definition at line 212 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SR_UNRE

#define HSMCI_SR_UNRE   (0x1u << 31)

(HSMCI_SR) Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0)

Definition at line 233 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_SR_XFRDONE

#define HSMCI_SR_XFRDONE   (0x1u << 27)

(HSMCI_SR) Transfer Done flag

Definition at line 229 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_TDR_DATA

#define HSMCI_TDR_DATA (   value)    ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))

◆ HSMCI_TDR_DATA_Msk

#define HSMCI_TDR_DATA_Msk   (0xffffffffu << HSMCI_TDR_DATA_Pos)

(HSMCI_TDR) Data to Write

Definition at line 207 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_TDR_DATA_Pos

#define HSMCI_TDR_DATA_Pos   0

◆ HSMCI_VERSION_MFN_Msk

#define HSMCI_VERSION_MFN_Msk   (0x7u << HSMCI_VERSION_MFN_Pos)

(HSMCI_VERSION) Metal Fix Number

Definition at line 338 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_VERSION_MFN_Pos

#define HSMCI_VERSION_MFN_Pos   16

◆ HSMCI_VERSION_VERSION_Msk

#define HSMCI_VERSION_VERSION_Msk   (0xfffu << HSMCI_VERSION_VERSION_Pos)

(HSMCI_VERSION) Hardware Module Version

Definition at line 336 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_VERSION_VERSION_Pos

#define HSMCI_VERSION_VERSION_Pos   0

◆ HSMCI_WPMR_WPEN

#define HSMCI_WPMR_WPEN   (0x1u << 0)

(HSMCI_WPMR) Write Protect Enable

Definition at line 325 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_WPMR_WPKEY

#define HSMCI_WPMR_WPKEY (   value)    ((HSMCI_WPMR_WPKEY_Msk & ((value) << HSMCI_WPMR_WPKEY_Pos)))

◆ HSMCI_WPMR_WPKEY_Msk

#define HSMCI_WPMR_WPKEY_Msk   (0xffffffu << HSMCI_WPMR_WPKEY_Pos)

(HSMCI_WPMR) Write Protect Key

Definition at line 327 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_WPMR_WPKEY_PASSWD

#define HSMCI_WPMR_WPKEY_PASSWD   (0x4D4349u << 8)

(HSMCI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

Definition at line 329 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_WPMR_WPKEY_Pos

#define HSMCI_WPMR_WPKEY_Pos   8

◆ HSMCI_WPSR_WPVS

#define HSMCI_WPSR_WPVS   (0x1u << 0)

(HSMCI_WPSR) Write Protection Violation Status

Definition at line 331 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_WPSR_WPVSRC_Msk

#define HSMCI_WPSR_WPVSRC_Msk   (0xffffu << HSMCI_WPSR_WPVSRC_Pos)

(HSMCI_WPSR) Write Protection Violation Source

Definition at line 333 of file utils/cmsis/same70/include/component/hsmci.h.

◆ HSMCI_WPSR_WPVSRC_Pos

#define HSMCI_WPSR_WPVSRC_Pos   8


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autogenerated on Sun Feb 28 2021 03:18:01