Classes | Macros
Digital-to-Analog Converter Controller

Classes

struct  Dacc
 Dacc hardware registers. More...
 

Macros

#define DACC_ACR_IBCTLCH0(value)   ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)))
 
#define DACC_ACR_IBCTLCH0_Msk   (0x3u << DACC_ACR_IBCTLCH0_Pos)
 (DACC_ACR) Analog Output Current Control More...
 
#define DACC_ACR_IBCTLCH0_Pos   0
 
#define DACC_ACR_IBCTLCH1(value)   ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)))
 
#define DACC_ACR_IBCTLCH1_Msk   (0x3u << DACC_ACR_IBCTLCH1_Pos)
 (DACC_ACR) Analog Output Current Control More...
 
#define DACC_ACR_IBCTLCH1_Pos   2
 
#define DACC_CDR_DATA0(value)   ((DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos)))
 
#define DACC_CDR_DATA0_Msk   (0xffffu << DACC_CDR_DATA0_Pos)
 (DACC_CDR[2]) Data to Convert for channel 0 More...
 
#define DACC_CDR_DATA0_Pos   0
 
#define DACC_CDR_DATA1(value)   ((DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos)))
 
#define DACC_CDR_DATA1_Msk   (0xffffu << DACC_CDR_DATA1_Pos)
 (DACC_CDR[2]) Data to Convert for channel 1 More...
 
#define DACC_CDR_DATA1_Pos   16
 
#define DACC_CHDR_CH0   (0x1u << 0)
 (DACC_CHDR) Channel 0 Disable More...
 
#define DACC_CHDR_CH1   (0x1u << 1)
 (DACC_CHDR) Channel 1 Disable More...
 
#define DACC_CHER_CH0   (0x1u << 0)
 (DACC_CHER) Channel 0 Enable More...
 
#define DACC_CHER_CH1   (0x1u << 1)
 (DACC_CHER) Channel 1 Enable More...
 
#define DACC_CHSR_CH0   (0x1u << 0)
 (DACC_CHSR) Channel 0 Status More...
 
#define DACC_CHSR_CH1   (0x1u << 1)
 (DACC_CHSR) Channel 1 Status More...
 
#define DACC_CHSR_DACRDY0   (0x1u << 8)
 (DACC_CHSR) DAC ready flag More...
 
#define DACC_CHSR_DACRDY1   (0x1u << 9)
 (DACC_CHSR) DAC ready flag More...
 
#define DACC_CR_SWRST   (0x1u << 0)
 (DACC_CR) Software Reset More...
 
#define DACC_IDR_ENDTX0   (0x1u << 8)
 (DACC_IDR) End of Transmit Buffer Interrupt Disable of channel 0 More...
 
#define DACC_IDR_ENDTX1   (0x1u << 9)
 (DACC_IDR) End of Transmit Buffer Interrupt Disable of channel 1 More...
 
#define DACC_IDR_EOC0   (0x1u << 4)
 (DACC_IDR) End of Conversion Interrupt Disable of channel 0 More...
 
#define DACC_IDR_EOC1   (0x1u << 5)
 (DACC_IDR) End of Conversion Interrupt Disable of channel 1 More...
 
#define DACC_IDR_TXBUFE0   (0x1u << 12)
 (DACC_IDR) Transmit Buffer Empty Interrupt Disable of channel 0 More...
 
#define DACC_IDR_TXBUFE1   (0x1u << 13)
 (DACC_IDR) Transmit Buffer Empty Interrupt Disable of channel 1 More...
 
#define DACC_IDR_TXRDY0   (0x1u << 0)
 (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 More...
 
#define DACC_IDR_TXRDY1   (0x1u << 1)
 (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 More...
 
#define DACC_IER_ENDTX0   (0x1u << 8)
 (DACC_IER) End of Transmit Buffer Interrupt Enable of channel 0 More...
 
#define DACC_IER_ENDTX1   (0x1u << 9)
 (DACC_IER) End of Transmit Buffer Interrupt Enable of channel 1 More...
 
#define DACC_IER_EOC0   (0x1u << 4)
 (DACC_IER) End of Conversion Interrupt Enable of channel 0 More...
 
#define DACC_IER_EOC1   (0x1u << 5)
 (DACC_IER) End of Conversion Interrupt Enable of channel 1 More...
 
#define DACC_IER_TXBUFE0   (0x1u << 12)
 (DACC_IER) Transmit Buffer Empty Interrupt Enable of channel 0 More...
 
#define DACC_IER_TXBUFE1   (0x1u << 13)
 (DACC_IER) Transmit Buffer Empty Interrupt Enable of channel 1 More...
 
#define DACC_IER_TXRDY0   (0x1u << 0)
 (DACC_IER) Transmit Ready Interrupt Enable of channel 0 More...
 
#define DACC_IER_TXRDY1   (0x1u << 1)
 (DACC_IER) Transmit Ready Interrupt Enable of channel 1 More...
 
#define DACC_IMR_ENDTX0   (0x1u << 8)
 (DACC_IMR) End of Transmit Buffer Interrupt Mask of channel 0 More...
 
#define DACC_IMR_ENDTX1   (0x1u << 9)
 (DACC_IMR) End of Transmit Buffer Interrupt Mask of channel 1 More...
 
#define DACC_IMR_EOC0   (0x1u << 4)
 (DACC_IMR) End of Conversion Interrupt Mask of channel 0 More...
 
#define DACC_IMR_EOC1   (0x1u << 5)
 (DACC_IMR) End of Conversion Interrupt Mask of channel 1 More...
 
#define DACC_IMR_TXBUFE0   (0x1u << 12)
 (DACC_IMR) Transmit Buffer Empty Interrupt Mask of channel 0 More...
 
#define DACC_IMR_TXBUFE1   (0x1u << 13)
 (DACC_IMR) Transmit Buffer Empty Interrupt Mask of channel 1 More...
 
#define DACC_IMR_TXRDY0   (0x1u << 0)
 (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 More...
 
#define DACC_IMR_TXRDY1   (0x1u << 1)
 (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 More...
 
#define DACC_ISR_ENDTX0   (0x1u << 8)
 (DACC_ISR) End of DMA Interrupt Flag of channel 0 More...
 
#define DACC_ISR_ENDTX1   (0x1u << 9)
 (DACC_ISR) End of DMA Interrupt Flag of channel 1 More...
 
#define DACC_ISR_EOC0   (0x1u << 4)
 (DACC_ISR) End of Conversion Interrupt Flag of channel 0 More...
 
#define DACC_ISR_EOC1   (0x1u << 5)
 (DACC_ISR) End of Conversion Interrupt Flag of channel 1 More...
 
#define DACC_ISR_TXBUFE0   (0x1u << 12)
 (DACC_ISR) Transmit Buffer Empty of channel 0 More...
 
#define DACC_ISR_TXBUFE1   (0x1u << 13)
 (DACC_ISR) Transmit Buffer Empty of channel 1 More...
 
#define DACC_ISR_TXRDY0   (0x1u << 0)
 (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 More...
 
#define DACC_ISR_TXRDY1   (0x1u << 1)
 (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 More...
 
#define DACC_MR_DIFF   (0x1u << 23)
 (DACC_MR) Differential Mode More...
 
#define DACC_MR_DIFF_DISABLED   (0x0u << 23)
 (DACC_MR) DAC0 and DAC1 outputs can be separately configured More...
 
#define DACC_MR_DIFF_ENABLED   (0x1u << 23)
 (DACC_MR) DACP and DACN outputs are configured by the channel 0 value. More...
 
#define DACC_MR_MAXS0   (0x1u << 0)
 (DACC_MR) Max Speed Mode for Channel 0 More...
 
#define DACC_MR_MAXS0_MAXIMUM   (0x1u << 0)
 (DACC_MR) Max Speed Mode enabled More...
 
#define DACC_MR_MAXS0_TRIG_EVENT   (0x0u << 0)
 (DACC_MR) Triggered by selected event More...
 
#define DACC_MR_MAXS1   (0x1u << 1)
 (DACC_MR) Max Speed Mode for Channel 1 More...
 
#define DACC_MR_MAXS1_MAXIMUM   (0x1u << 1)
 (DACC_MR) Max Speed Mode enabled More...
 
#define DACC_MR_MAXS1_TRIG_EVENT   (0x0u << 1)
 (DACC_MR) Triggered by selected event More...
 
#define DACC_MR_PRESCALER(value)   ((DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos)))
 
#define DACC_MR_PRESCALER_Msk   (0xfu << DACC_MR_PRESCALER_Pos)
 (DACC_MR) Peripheral Clock to DAC Clock Ratio More...
 
#define DACC_MR_PRESCALER_Pos   24
 
#define DACC_MR_REFRESH(value)   ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos)))
 
#define DACC_MR_REFRESH_Msk   (0xffu << DACC_MR_REFRESH_Pos)
 (DACC_MR) Refresh Period More...
 
#define DACC_MR_REFRESH_Pos   8
 
#define DACC_MR_WORD   (0x1u << 4)
 (DACC_MR) Word Transfer Mode More...
 
#define DACC_MR_WORD_DISABLED   (0x0u << 4)
 (DACC_MR) One data to convert is written to the FIFO per access to DACC More...
 
#define DACC_MR_WORD_ENABLED   (0x1u << 4)
 (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces number of requests to DMA and the number of system bus accesses) More...
 
#define DACC_MR_ZERO   (0x1u << 5)
 (DACC_MR) Must always be written to 0. More...
 
#define DACC_TRIGR_OSR0(value)   ((DACC_TRIGR_OSR0_Msk & ((value) << DACC_TRIGR_OSR0_Pos)))
 
#define DACC_TRIGR_OSR0_Msk   (0x7u << DACC_TRIGR_OSR0_Pos)
 (DACC_TRIGR) Over Sampling Ratio of Channel 0 More...
 
#define DACC_TRIGR_OSR0_OSR_1   (0x0u << 16)
 (DACC_TRIGR) OSR = 1 More...
 
#define DACC_TRIGR_OSR0_OSR_16   (0x4u << 16)
 (DACC_TRIGR) OSR = 16 More...
 
#define DACC_TRIGR_OSR0_OSR_2   (0x1u << 16)
 (DACC_TRIGR) OSR = 2 More...
 
#define DACC_TRIGR_OSR0_OSR_32   (0x5u << 16)
 (DACC_TRIGR) OSR = 32 More...
 
#define DACC_TRIGR_OSR0_OSR_4   (0x2u << 16)
 (DACC_TRIGR) OSR = 4 More...
 
#define DACC_TRIGR_OSR0_OSR_8   (0x3u << 16)
 (DACC_TRIGR) OSR = 8 More...
 
#define DACC_TRIGR_OSR0_Pos   16
 
#define DACC_TRIGR_OSR1(value)   ((DACC_TRIGR_OSR1_Msk & ((value) << DACC_TRIGR_OSR1_Pos)))
 
#define DACC_TRIGR_OSR1_Msk   (0x7u << DACC_TRIGR_OSR1_Pos)
 (DACC_TRIGR) Over Sampling Ratio of Channel 1 More...
 
#define DACC_TRIGR_OSR1_OSR_1   (0x0u << 20)
 (DACC_TRIGR) OSR = 1 More...
 
#define DACC_TRIGR_OSR1_OSR_16   (0x4u << 20)
 (DACC_TRIGR) OSR = 16 More...
 
#define DACC_TRIGR_OSR1_OSR_2   (0x1u << 20)
 (DACC_TRIGR) OSR = 2 More...
 
#define DACC_TRIGR_OSR1_OSR_32   (0x5u << 20)
 (DACC_TRIGR) OSR = 32 More...
 
#define DACC_TRIGR_OSR1_OSR_4   (0x2u << 20)
 (DACC_TRIGR) OSR = 4 More...
 
#define DACC_TRIGR_OSR1_OSR_8   (0x3u << 20)
 (DACC_TRIGR) OSR = 8 More...
 
#define DACC_TRIGR_OSR1_Pos   20
 
#define DACC_TRIGR_TRGEN0   (0x1u << 0)
 (DACC_TRIGR) Trigger Enable of Channel 0 More...
 
#define DACC_TRIGR_TRGEN0_DIS   (0x0u << 0)
 (DACC_TRIGR) External trigger mode disabled. DAC is in free running mode. More...
 
#define DACC_TRIGR_TRGEN0_EN   (0x1u << 0)
 (DACC_TRIGR) External trigger mode enabled. More...
 
#define DACC_TRIGR_TRGEN1   (0x1u << 1)
 (DACC_TRIGR) Trigger Enable of Channel 1 More...
 
#define DACC_TRIGR_TRGEN1_DIS   (0x0u << 1)
 (DACC_TRIGR) External trigger mode disabled. DAC is in free running mode. More...
 
#define DACC_TRIGR_TRGEN1_EN   (0x1u << 1)
 (DACC_TRIGR) External trigger mode enabled. More...
 
#define DACC_TRIGR_TRGSEL0(value)   ((DACC_TRIGR_TRGSEL0_Msk & ((value) << DACC_TRIGR_TRGSEL0_Pos)))
 
#define DACC_TRIGR_TRGSEL0_Msk   (0x7u << DACC_TRIGR_TRGSEL0_Pos)
 (DACC_TRIGR) Trigger Selection of Channel 0 More...
 
#define DACC_TRIGR_TRGSEL0_Pos   4
 
#define DACC_TRIGR_TRGSEL0_TRGSEL0   (0x0u << 4)
 (DACC_TRIGR) DATRG More...
 
#define DACC_TRIGR_TRGSEL0_TRGSEL1   (0x1u << 4)
 (DACC_TRIGR) TC0 output More...
 
#define DACC_TRIGR_TRGSEL0_TRGSEL2   (0x2u << 4)
 (DACC_TRIGR) TC1 output More...
 
#define DACC_TRIGR_TRGSEL0_TRGSEL3   (0x3u << 4)
 (DACC_TRIGR) TC2 output More...
 
#define DACC_TRIGR_TRGSEL0_TRGSEL4   (0x4u << 4)
 (DACC_TRIGR) PWM0 event 0 More...
 
#define DACC_TRIGR_TRGSEL0_TRGSEL5   (0x5u << 4)
 (DACC_TRIGR) PWM0 event 1 More...
 
#define DACC_TRIGR_TRGSEL0_TRGSEL6   (0x6u << 4)
 (DACC_TRIGR) PWM1 event 0 More...
 
#define DACC_TRIGR_TRGSEL0_TRGSEL7   (0x7u << 4)
 (DACC_TRIGR) PWM1 event 1 More...
 
#define DACC_TRIGR_TRGSEL1(value)   ((DACC_TRIGR_TRGSEL1_Msk & ((value) << DACC_TRIGR_TRGSEL1_Pos)))
 
#define DACC_TRIGR_TRGSEL1_Msk   (0x7u << DACC_TRIGR_TRGSEL1_Pos)
 (DACC_TRIGR) Trigger Selection of Channel 1 More...
 
#define DACC_TRIGR_TRGSEL1_Pos   8
 
#define DACC_TRIGR_TRGSEL1_TRGSEL0   (0x0u << 8)
 (DACC_TRIGR) DATRG More...
 
#define DACC_TRIGR_TRGSEL1_TRGSEL1   (0x1u << 8)
 (DACC_TRIGR) TC0 output More...
 
#define DACC_TRIGR_TRGSEL1_TRGSEL2   (0x2u << 8)
 (DACC_TRIGR) TC1 output More...
 
#define DACC_TRIGR_TRGSEL1_TRGSEL3   (0x3u << 8)
 (DACC_TRIGR) TC2 output More...
 
#define DACC_TRIGR_TRGSEL1_TRGSEL4   (0x4u << 8)
 (DACC_TRIGR) PWM0 event 0 More...
 
#define DACC_TRIGR_TRGSEL1_TRGSEL5   (0x5u << 8)
 (DACC_TRIGR) PWM0 event 1 More...
 
#define DACC_TRIGR_TRGSEL1_TRGSEL6   (0x6u << 8)
 (DACC_TRIGR) PWM1 event 0 More...
 
#define DACC_TRIGR_TRGSEL1_TRGSEL7   (0x7u << 8)
 (DACC_TRIGR) PWM1 event 1 More...
 
#define DACC_VERSION_MFN_Msk   (0x7u << DACC_VERSION_MFN_Pos)
 (DACC_VERSION) Metal Fix Number More...
 
#define DACC_VERSION_MFN_Pos   16
 
#define DACC_VERSION_VERSION_Msk   (0xfffu << DACC_VERSION_VERSION_Pos)
 (DACC_VERSION) Version More...
 
#define DACC_VERSION_VERSION_Pos   0
 
#define DACC_WPMR_WPEN   (0x1u << 0)
 (DACC_WPMR) Write Protection Enable More...
 
#define DACC_WPMR_WPKEY(value)   ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))
 
#define DACC_WPMR_WPKEY_Msk   (0xffffffu << DACC_WPMR_WPKEY_Pos)
 (DACC_WPMR) Write Protect Key More...
 
#define DACC_WPMR_WPKEY_PASSWD   (0x444143u << 8)
 (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. More...
 
#define DACC_WPMR_WPKEY_Pos   8
 
#define DACC_WPSR_WPVS   (0x1u << 0)
 (DACC_WPSR) Write Protection Violation Status More...
 
#define DACC_WPSR_WPVSRC_Msk   (0xffu << DACC_WPSR_WPVSRC_Pos)
 (DACC_WPSR) Write Protection Violation Source More...
 
#define DACC_WPSR_WPVSRC_Pos   8
 

Detailed Description

SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller

Macro Definition Documentation

◆ DACC_ACR_IBCTLCH0

#define DACC_ACR_IBCTLCH0 (   value)    ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)))

Definition at line 194 of file component/dacc.h.

◆ DACC_ACR_IBCTLCH0_Msk

#define DACC_ACR_IBCTLCH0_Msk   (0x3u << DACC_ACR_IBCTLCH0_Pos)

(DACC_ACR) Analog Output Current Control

Definition at line 193 of file component/dacc.h.

◆ DACC_ACR_IBCTLCH0_Pos

#define DACC_ACR_IBCTLCH0_Pos   0

Definition at line 192 of file component/dacc.h.

◆ DACC_ACR_IBCTLCH1

#define DACC_ACR_IBCTLCH1 (   value)    ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)))

Definition at line 197 of file component/dacc.h.

◆ DACC_ACR_IBCTLCH1_Msk

#define DACC_ACR_IBCTLCH1_Msk   (0x3u << DACC_ACR_IBCTLCH1_Pos)

(DACC_ACR) Analog Output Current Control

Definition at line 196 of file component/dacc.h.

◆ DACC_ACR_IBCTLCH1_Pos

#define DACC_ACR_IBCTLCH1_Pos   2

Definition at line 195 of file component/dacc.h.

◆ DACC_CDR_DATA0

#define DACC_CDR_DATA0 (   value)    ((DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos)))

Definition at line 151 of file component/dacc.h.

◆ DACC_CDR_DATA0_Msk

#define DACC_CDR_DATA0_Msk   (0xffffu << DACC_CDR_DATA0_Pos)

(DACC_CDR[2]) Data to Convert for channel 0

Definition at line 150 of file component/dacc.h.

◆ DACC_CDR_DATA0_Pos

#define DACC_CDR_DATA0_Pos   0

Definition at line 149 of file component/dacc.h.

◆ DACC_CDR_DATA1

#define DACC_CDR_DATA1 (   value)    ((DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos)))

Definition at line 154 of file component/dacc.h.

◆ DACC_CDR_DATA1_Msk

#define DACC_CDR_DATA1_Msk   (0xffffu << DACC_CDR_DATA1_Pos)

(DACC_CDR[2]) Data to Convert for channel 1

Definition at line 153 of file component/dacc.h.

◆ DACC_CDR_DATA1_Pos

#define DACC_CDR_DATA1_Pos   16

Definition at line 152 of file component/dacc.h.

◆ DACC_CHDR_CH0

#define DACC_CHDR_CH0   (0x1u << 0)

(DACC_CHDR) Channel 0 Disable

Definition at line 141 of file component/dacc.h.

◆ DACC_CHDR_CH1

#define DACC_CHDR_CH1   (0x1u << 1)

(DACC_CHDR) Channel 1 Disable

Definition at line 142 of file component/dacc.h.

◆ DACC_CHER_CH0

#define DACC_CHER_CH0   (0x1u << 0)

(DACC_CHER) Channel 0 Enable

Definition at line 138 of file component/dacc.h.

◆ DACC_CHER_CH1

#define DACC_CHER_CH1   (0x1u << 1)

(DACC_CHER) Channel 1 Enable

Definition at line 139 of file component/dacc.h.

◆ DACC_CHSR_CH0

#define DACC_CHSR_CH0   (0x1u << 0)

(DACC_CHSR) Channel 0 Status

Definition at line 144 of file component/dacc.h.

◆ DACC_CHSR_CH1

#define DACC_CHSR_CH1   (0x1u << 1)

(DACC_CHSR) Channel 1 Status

Definition at line 145 of file component/dacc.h.

◆ DACC_CHSR_DACRDY0

#define DACC_CHSR_DACRDY0   (0x1u << 8)

(DACC_CHSR) DAC ready flag

Definition at line 146 of file component/dacc.h.

◆ DACC_CHSR_DACRDY1

#define DACC_CHSR_DACRDY1   (0x1u << 9)

(DACC_CHSR) DAC ready flag

Definition at line 147 of file component/dacc.h.

◆ DACC_CR_SWRST

#define DACC_CR_SWRST   (0x1u << 0)

(DACC_CR) Software Reset

Definition at line 69 of file component/dacc.h.

◆ DACC_IDR_ENDTX0

#define DACC_IDR_ENDTX0   (0x1u << 8)

(DACC_IDR) End of Transmit Buffer Interrupt Disable of channel 0

Definition at line 169 of file component/dacc.h.

◆ DACC_IDR_ENDTX1

#define DACC_IDR_ENDTX1   (0x1u << 9)

(DACC_IDR) End of Transmit Buffer Interrupt Disable of channel 1

Definition at line 170 of file component/dacc.h.

◆ DACC_IDR_EOC0

#define DACC_IDR_EOC0   (0x1u << 4)

(DACC_IDR) End of Conversion Interrupt Disable of channel 0

Definition at line 167 of file component/dacc.h.

◆ DACC_IDR_EOC1

#define DACC_IDR_EOC1   (0x1u << 5)

(DACC_IDR) End of Conversion Interrupt Disable of channel 1

Definition at line 168 of file component/dacc.h.

◆ DACC_IDR_TXBUFE0

#define DACC_IDR_TXBUFE0   (0x1u << 12)

(DACC_IDR) Transmit Buffer Empty Interrupt Disable of channel 0

Definition at line 171 of file component/dacc.h.

◆ DACC_IDR_TXBUFE1

#define DACC_IDR_TXBUFE1   (0x1u << 13)

(DACC_IDR) Transmit Buffer Empty Interrupt Disable of channel 1

Definition at line 172 of file component/dacc.h.

◆ DACC_IDR_TXRDY0

#define DACC_IDR_TXRDY0   (0x1u << 0)

(DACC_IDR) Transmit Ready Interrupt Disable of channel 0

Definition at line 165 of file component/dacc.h.

◆ DACC_IDR_TXRDY1

#define DACC_IDR_TXRDY1   (0x1u << 1)

(DACC_IDR) Transmit Ready Interrupt Disable of channel 1

Definition at line 166 of file component/dacc.h.

◆ DACC_IER_ENDTX0

#define DACC_IER_ENDTX0   (0x1u << 8)

(DACC_IER) End of Transmit Buffer Interrupt Enable of channel 0

Definition at line 160 of file component/dacc.h.

◆ DACC_IER_ENDTX1

#define DACC_IER_ENDTX1   (0x1u << 9)

(DACC_IER) End of Transmit Buffer Interrupt Enable of channel 1

Definition at line 161 of file component/dacc.h.

◆ DACC_IER_EOC0

#define DACC_IER_EOC0   (0x1u << 4)

(DACC_IER) End of Conversion Interrupt Enable of channel 0

Definition at line 158 of file component/dacc.h.

◆ DACC_IER_EOC1

#define DACC_IER_EOC1   (0x1u << 5)

(DACC_IER) End of Conversion Interrupt Enable of channel 1

Definition at line 159 of file component/dacc.h.

◆ DACC_IER_TXBUFE0

#define DACC_IER_TXBUFE0   (0x1u << 12)

(DACC_IER) Transmit Buffer Empty Interrupt Enable of channel 0

Definition at line 162 of file component/dacc.h.

◆ DACC_IER_TXBUFE1

#define DACC_IER_TXBUFE1   (0x1u << 13)

(DACC_IER) Transmit Buffer Empty Interrupt Enable of channel 1

Definition at line 163 of file component/dacc.h.

◆ DACC_IER_TXRDY0

#define DACC_IER_TXRDY0   (0x1u << 0)

(DACC_IER) Transmit Ready Interrupt Enable of channel 0

Definition at line 156 of file component/dacc.h.

◆ DACC_IER_TXRDY1

#define DACC_IER_TXRDY1   (0x1u << 1)

(DACC_IER) Transmit Ready Interrupt Enable of channel 1

Definition at line 157 of file component/dacc.h.

◆ DACC_IMR_ENDTX0

#define DACC_IMR_ENDTX0   (0x1u << 8)

(DACC_IMR) End of Transmit Buffer Interrupt Mask of channel 0

Definition at line 178 of file component/dacc.h.

◆ DACC_IMR_ENDTX1

#define DACC_IMR_ENDTX1   (0x1u << 9)

(DACC_IMR) End of Transmit Buffer Interrupt Mask of channel 1

Definition at line 179 of file component/dacc.h.

◆ DACC_IMR_EOC0

#define DACC_IMR_EOC0   (0x1u << 4)

(DACC_IMR) End of Conversion Interrupt Mask of channel 0

Definition at line 176 of file component/dacc.h.

◆ DACC_IMR_EOC1

#define DACC_IMR_EOC1   (0x1u << 5)

(DACC_IMR) End of Conversion Interrupt Mask of channel 1

Definition at line 177 of file component/dacc.h.

◆ DACC_IMR_TXBUFE0

#define DACC_IMR_TXBUFE0   (0x1u << 12)

(DACC_IMR) Transmit Buffer Empty Interrupt Mask of channel 0

Definition at line 180 of file component/dacc.h.

◆ DACC_IMR_TXBUFE1

#define DACC_IMR_TXBUFE1   (0x1u << 13)

(DACC_IMR) Transmit Buffer Empty Interrupt Mask of channel 1

Definition at line 181 of file component/dacc.h.

◆ DACC_IMR_TXRDY0

#define DACC_IMR_TXRDY0   (0x1u << 0)

(DACC_IMR) Transmit Ready Interrupt Mask of channel 0

Definition at line 174 of file component/dacc.h.

◆ DACC_IMR_TXRDY1

#define DACC_IMR_TXRDY1   (0x1u << 1)

(DACC_IMR) Transmit Ready Interrupt Mask of channel 1

Definition at line 175 of file component/dacc.h.

◆ DACC_ISR_ENDTX0

#define DACC_ISR_ENDTX0   (0x1u << 8)

(DACC_ISR) End of DMA Interrupt Flag of channel 0

Definition at line 187 of file component/dacc.h.

◆ DACC_ISR_ENDTX1

#define DACC_ISR_ENDTX1   (0x1u << 9)

(DACC_ISR) End of DMA Interrupt Flag of channel 1

Definition at line 188 of file component/dacc.h.

◆ DACC_ISR_EOC0

#define DACC_ISR_EOC0   (0x1u << 4)

(DACC_ISR) End of Conversion Interrupt Flag of channel 0

Definition at line 185 of file component/dacc.h.

◆ DACC_ISR_EOC1

#define DACC_ISR_EOC1   (0x1u << 5)

(DACC_ISR) End of Conversion Interrupt Flag of channel 1

Definition at line 186 of file component/dacc.h.

◆ DACC_ISR_TXBUFE0

#define DACC_ISR_TXBUFE0   (0x1u << 12)

(DACC_ISR) Transmit Buffer Empty of channel 0

Definition at line 189 of file component/dacc.h.

◆ DACC_ISR_TXBUFE1

#define DACC_ISR_TXBUFE1   (0x1u << 13)

(DACC_ISR) Transmit Buffer Empty of channel 1

Definition at line 190 of file component/dacc.h.

◆ DACC_ISR_TXRDY0

#define DACC_ISR_TXRDY0   (0x1u << 0)

(DACC_ISR) Transmit Ready Interrupt Flag of channel 0

Definition at line 183 of file component/dacc.h.

◆ DACC_ISR_TXRDY1

#define DACC_ISR_TXRDY1   (0x1u << 1)

(DACC_ISR) Transmit Ready Interrupt Flag of channel 1

Definition at line 184 of file component/dacc.h.

◆ DACC_MR_DIFF

#define DACC_MR_DIFF   (0x1u << 23)

(DACC_MR) Differential Mode

Definition at line 84 of file component/dacc.h.

◆ DACC_MR_DIFF_DISABLED

#define DACC_MR_DIFF_DISABLED   (0x0u << 23)

(DACC_MR) DAC0 and DAC1 outputs can be separately configured

Definition at line 85 of file component/dacc.h.

◆ DACC_MR_DIFF_ENABLED

#define DACC_MR_DIFF_ENABLED   (0x1u << 23)

(DACC_MR) DACP and DACN outputs are configured by the channel 0 value.

Definition at line 86 of file component/dacc.h.

◆ DACC_MR_MAXS0

#define DACC_MR_MAXS0   (0x1u << 0)

(DACC_MR) Max Speed Mode for Channel 0

Definition at line 71 of file component/dacc.h.

◆ DACC_MR_MAXS0_MAXIMUM

#define DACC_MR_MAXS0_MAXIMUM   (0x1u << 0)

(DACC_MR) Max Speed Mode enabled

Definition at line 73 of file component/dacc.h.

◆ DACC_MR_MAXS0_TRIG_EVENT

#define DACC_MR_MAXS0_TRIG_EVENT   (0x0u << 0)

(DACC_MR) Triggered by selected event

Definition at line 72 of file component/dacc.h.

◆ DACC_MR_MAXS1

#define DACC_MR_MAXS1   (0x1u << 1)

(DACC_MR) Max Speed Mode for Channel 1

Definition at line 74 of file component/dacc.h.

◆ DACC_MR_MAXS1_MAXIMUM

#define DACC_MR_MAXS1_MAXIMUM   (0x1u << 1)

(DACC_MR) Max Speed Mode enabled

Definition at line 76 of file component/dacc.h.

◆ DACC_MR_MAXS1_TRIG_EVENT

#define DACC_MR_MAXS1_TRIG_EVENT   (0x0u << 1)

(DACC_MR) Triggered by selected event

Definition at line 75 of file component/dacc.h.

◆ DACC_MR_PRESCALER

#define DACC_MR_PRESCALER (   value)    ((DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos)))

Definition at line 89 of file component/dacc.h.

◆ DACC_MR_PRESCALER_Msk

#define DACC_MR_PRESCALER_Msk   (0xfu << DACC_MR_PRESCALER_Pos)

(DACC_MR) Peripheral Clock to DAC Clock Ratio

Definition at line 88 of file component/dacc.h.

◆ DACC_MR_PRESCALER_Pos

#define DACC_MR_PRESCALER_Pos   24

Definition at line 87 of file component/dacc.h.

◆ DACC_MR_REFRESH

#define DACC_MR_REFRESH (   value)    ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos)))

Definition at line 83 of file component/dacc.h.

◆ DACC_MR_REFRESH_Msk

#define DACC_MR_REFRESH_Msk   (0xffu << DACC_MR_REFRESH_Pos)

(DACC_MR) Refresh Period

Definition at line 82 of file component/dacc.h.

◆ DACC_MR_REFRESH_Pos

#define DACC_MR_REFRESH_Pos   8

Definition at line 81 of file component/dacc.h.

◆ DACC_MR_WORD

#define DACC_MR_WORD   (0x1u << 4)

(DACC_MR) Word Transfer Mode

Definition at line 77 of file component/dacc.h.

◆ DACC_MR_WORD_DISABLED

#define DACC_MR_WORD_DISABLED   (0x0u << 4)

(DACC_MR) One data to convert is written to the FIFO per access to DACC

Definition at line 78 of file component/dacc.h.

◆ DACC_MR_WORD_ENABLED

#define DACC_MR_WORD_ENABLED   (0x1u << 4)

(DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces number of requests to DMA and the number of system bus accesses)

Definition at line 79 of file component/dacc.h.

◆ DACC_MR_ZERO

#define DACC_MR_ZERO   (0x1u << 5)

(DACC_MR) Must always be written to 0.

Definition at line 80 of file component/dacc.h.

◆ DACC_TRIGR_OSR0

#define DACC_TRIGR_OSR0 (   value)    ((DACC_TRIGR_OSR0_Msk & ((value) << DACC_TRIGR_OSR0_Pos)))

Definition at line 121 of file component/dacc.h.

◆ DACC_TRIGR_OSR0_Msk

#define DACC_TRIGR_OSR0_Msk   (0x7u << DACC_TRIGR_OSR0_Pos)

(DACC_TRIGR) Over Sampling Ratio of Channel 0

Definition at line 120 of file component/dacc.h.

◆ DACC_TRIGR_OSR0_OSR_1

#define DACC_TRIGR_OSR0_OSR_1   (0x0u << 16)

(DACC_TRIGR) OSR = 1

Definition at line 122 of file component/dacc.h.

◆ DACC_TRIGR_OSR0_OSR_16

#define DACC_TRIGR_OSR0_OSR_16   (0x4u << 16)

(DACC_TRIGR) OSR = 16

Definition at line 126 of file component/dacc.h.

◆ DACC_TRIGR_OSR0_OSR_2

#define DACC_TRIGR_OSR0_OSR_2   (0x1u << 16)

(DACC_TRIGR) OSR = 2

Definition at line 123 of file component/dacc.h.

◆ DACC_TRIGR_OSR0_OSR_32

#define DACC_TRIGR_OSR0_OSR_32   (0x5u << 16)

(DACC_TRIGR) OSR = 32

Definition at line 127 of file component/dacc.h.

◆ DACC_TRIGR_OSR0_OSR_4

#define DACC_TRIGR_OSR0_OSR_4   (0x2u << 16)

(DACC_TRIGR) OSR = 4

Definition at line 124 of file component/dacc.h.

◆ DACC_TRIGR_OSR0_OSR_8

#define DACC_TRIGR_OSR0_OSR_8   (0x3u << 16)

(DACC_TRIGR) OSR = 8

Definition at line 125 of file component/dacc.h.

◆ DACC_TRIGR_OSR0_Pos

#define DACC_TRIGR_OSR0_Pos   16

Definition at line 119 of file component/dacc.h.

◆ DACC_TRIGR_OSR1

#define DACC_TRIGR_OSR1 (   value)    ((DACC_TRIGR_OSR1_Msk & ((value) << DACC_TRIGR_OSR1_Pos)))

Definition at line 130 of file component/dacc.h.

◆ DACC_TRIGR_OSR1_Msk

#define DACC_TRIGR_OSR1_Msk   (0x7u << DACC_TRIGR_OSR1_Pos)

(DACC_TRIGR) Over Sampling Ratio of Channel 1

Definition at line 129 of file component/dacc.h.

◆ DACC_TRIGR_OSR1_OSR_1

#define DACC_TRIGR_OSR1_OSR_1   (0x0u << 20)

(DACC_TRIGR) OSR = 1

Definition at line 131 of file component/dacc.h.

◆ DACC_TRIGR_OSR1_OSR_16

#define DACC_TRIGR_OSR1_OSR_16   (0x4u << 20)

(DACC_TRIGR) OSR = 16

Definition at line 135 of file component/dacc.h.

◆ DACC_TRIGR_OSR1_OSR_2

#define DACC_TRIGR_OSR1_OSR_2   (0x1u << 20)

(DACC_TRIGR) OSR = 2

Definition at line 132 of file component/dacc.h.

◆ DACC_TRIGR_OSR1_OSR_32

#define DACC_TRIGR_OSR1_OSR_32   (0x5u << 20)

(DACC_TRIGR) OSR = 32

Definition at line 136 of file component/dacc.h.

◆ DACC_TRIGR_OSR1_OSR_4

#define DACC_TRIGR_OSR1_OSR_4   (0x2u << 20)

(DACC_TRIGR) OSR = 4

Definition at line 133 of file component/dacc.h.

◆ DACC_TRIGR_OSR1_OSR_8

#define DACC_TRIGR_OSR1_OSR_8   (0x3u << 20)

(DACC_TRIGR) OSR = 8

Definition at line 134 of file component/dacc.h.

◆ DACC_TRIGR_OSR1_Pos

#define DACC_TRIGR_OSR1_Pos   20

Definition at line 128 of file component/dacc.h.

◆ DACC_TRIGR_TRGEN0

#define DACC_TRIGR_TRGEN0   (0x1u << 0)

(DACC_TRIGR) Trigger Enable of Channel 0

Definition at line 91 of file component/dacc.h.

◆ DACC_TRIGR_TRGEN0_DIS

#define DACC_TRIGR_TRGEN0_DIS   (0x0u << 0)

(DACC_TRIGR) External trigger mode disabled. DAC is in free running mode.

Definition at line 92 of file component/dacc.h.

◆ DACC_TRIGR_TRGEN0_EN

#define DACC_TRIGR_TRGEN0_EN   (0x1u << 0)

(DACC_TRIGR) External trigger mode enabled.

Definition at line 93 of file component/dacc.h.

◆ DACC_TRIGR_TRGEN1

#define DACC_TRIGR_TRGEN1   (0x1u << 1)

(DACC_TRIGR) Trigger Enable of Channel 1

Definition at line 94 of file component/dacc.h.

◆ DACC_TRIGR_TRGEN1_DIS

#define DACC_TRIGR_TRGEN1_DIS   (0x0u << 1)

(DACC_TRIGR) External trigger mode disabled. DAC is in free running mode.

Definition at line 95 of file component/dacc.h.

◆ DACC_TRIGR_TRGEN1_EN

#define DACC_TRIGR_TRGEN1_EN   (0x1u << 1)

(DACC_TRIGR) External trigger mode enabled.

Definition at line 96 of file component/dacc.h.

◆ DACC_TRIGR_TRGSEL0

#define DACC_TRIGR_TRGSEL0 (   value)    ((DACC_TRIGR_TRGSEL0_Msk & ((value) << DACC_TRIGR_TRGSEL0_Pos)))

Definition at line 99 of file component/dacc.h.

◆ DACC_TRIGR_TRGSEL0_Msk

#define DACC_TRIGR_TRGSEL0_Msk   (0x7u << DACC_TRIGR_TRGSEL0_Pos)

(DACC_TRIGR) Trigger Selection of Channel 0

Definition at line 98 of file component/dacc.h.

◆ DACC_TRIGR_TRGSEL0_Pos

#define DACC_TRIGR_TRGSEL0_Pos   4

Definition at line 97 of file component/dacc.h.

◆ DACC_TRIGR_TRGSEL0_TRGSEL0

#define DACC_TRIGR_TRGSEL0_TRGSEL0   (0x0u << 4)

(DACC_TRIGR) DATRG

Definition at line 100 of file component/dacc.h.

◆ DACC_TRIGR_TRGSEL0_TRGSEL1

#define DACC_TRIGR_TRGSEL0_TRGSEL1   (0x1u << 4)

(DACC_TRIGR) TC0 output

Definition at line 101 of file component/dacc.h.

◆ DACC_TRIGR_TRGSEL0_TRGSEL2

#define DACC_TRIGR_TRGSEL0_TRGSEL2   (0x2u << 4)

(DACC_TRIGR) TC1 output

Definition at line 102 of file component/dacc.h.

◆ DACC_TRIGR_TRGSEL0_TRGSEL3

#define DACC_TRIGR_TRGSEL0_TRGSEL3   (0x3u << 4)

(DACC_TRIGR) TC2 output

Definition at line 103 of file component/dacc.h.

◆ DACC_TRIGR_TRGSEL0_TRGSEL4

#define DACC_TRIGR_TRGSEL0_TRGSEL4   (0x4u << 4)

(DACC_TRIGR) PWM0 event 0

Definition at line 104 of file component/dacc.h.

◆ DACC_TRIGR_TRGSEL0_TRGSEL5

#define DACC_TRIGR_TRGSEL0_TRGSEL5   (0x5u << 4)

(DACC_TRIGR) PWM0 event 1

Definition at line 105 of file component/dacc.h.

◆ DACC_TRIGR_TRGSEL0_TRGSEL6

#define DACC_TRIGR_TRGSEL0_TRGSEL6   (0x6u << 4)

(DACC_TRIGR) PWM1 event 0

Definition at line 106 of file component/dacc.h.

◆ DACC_TRIGR_TRGSEL0_TRGSEL7

#define DACC_TRIGR_TRGSEL0_TRGSEL7   (0x7u << 4)

(DACC_TRIGR) PWM1 event 1

Definition at line 107 of file component/dacc.h.

◆ DACC_TRIGR_TRGSEL1

#define DACC_TRIGR_TRGSEL1 (   value)    ((DACC_TRIGR_TRGSEL1_Msk & ((value) << DACC_TRIGR_TRGSEL1_Pos)))

Definition at line 110 of file component/dacc.h.

◆ DACC_TRIGR_TRGSEL1_Msk

#define DACC_TRIGR_TRGSEL1_Msk   (0x7u << DACC_TRIGR_TRGSEL1_Pos)

(DACC_TRIGR) Trigger Selection of Channel 1

Definition at line 109 of file component/dacc.h.

◆ DACC_TRIGR_TRGSEL1_Pos

#define DACC_TRIGR_TRGSEL1_Pos   8

Definition at line 108 of file component/dacc.h.

◆ DACC_TRIGR_TRGSEL1_TRGSEL0

#define DACC_TRIGR_TRGSEL1_TRGSEL0   (0x0u << 8)

(DACC_TRIGR) DATRG

Definition at line 111 of file component/dacc.h.

◆ DACC_TRIGR_TRGSEL1_TRGSEL1

#define DACC_TRIGR_TRGSEL1_TRGSEL1   (0x1u << 8)

(DACC_TRIGR) TC0 output

Definition at line 112 of file component/dacc.h.

◆ DACC_TRIGR_TRGSEL1_TRGSEL2

#define DACC_TRIGR_TRGSEL1_TRGSEL2   (0x2u << 8)

(DACC_TRIGR) TC1 output

Definition at line 113 of file component/dacc.h.

◆ DACC_TRIGR_TRGSEL1_TRGSEL3

#define DACC_TRIGR_TRGSEL1_TRGSEL3   (0x3u << 8)

(DACC_TRIGR) TC2 output

Definition at line 114 of file component/dacc.h.

◆ DACC_TRIGR_TRGSEL1_TRGSEL4

#define DACC_TRIGR_TRGSEL1_TRGSEL4   (0x4u << 8)

(DACC_TRIGR) PWM0 event 0

Definition at line 115 of file component/dacc.h.

◆ DACC_TRIGR_TRGSEL1_TRGSEL5

#define DACC_TRIGR_TRGSEL1_TRGSEL5   (0x5u << 8)

(DACC_TRIGR) PWM0 event 1

Definition at line 116 of file component/dacc.h.

◆ DACC_TRIGR_TRGSEL1_TRGSEL6

#define DACC_TRIGR_TRGSEL1_TRGSEL6   (0x6u << 8)

(DACC_TRIGR) PWM1 event 0

Definition at line 117 of file component/dacc.h.

◆ DACC_TRIGR_TRGSEL1_TRGSEL7

#define DACC_TRIGR_TRGSEL1_TRGSEL7   (0x7u << 8)

(DACC_TRIGR) PWM1 event 1

Definition at line 118 of file component/dacc.h.

◆ DACC_VERSION_MFN_Msk

#define DACC_VERSION_MFN_Msk   (0x7u << DACC_VERSION_MFN_Pos)

(DACC_VERSION) Metal Fix Number

Definition at line 212 of file component/dacc.h.

◆ DACC_VERSION_MFN_Pos

#define DACC_VERSION_MFN_Pos   16

Definition at line 211 of file component/dacc.h.

◆ DACC_VERSION_VERSION_Msk

#define DACC_VERSION_VERSION_Msk   (0xfffu << DACC_VERSION_VERSION_Pos)

(DACC_VERSION) Version

Definition at line 210 of file component/dacc.h.

◆ DACC_VERSION_VERSION_Pos

#define DACC_VERSION_VERSION_Pos   0

Definition at line 209 of file component/dacc.h.

◆ DACC_WPMR_WPEN

#define DACC_WPMR_WPEN   (0x1u << 0)

(DACC_WPMR) Write Protection Enable

Definition at line 199 of file component/dacc.h.

◆ DACC_WPMR_WPKEY

#define DACC_WPMR_WPKEY (   value)    ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))

Definition at line 202 of file component/dacc.h.

◆ DACC_WPMR_WPKEY_Msk

#define DACC_WPMR_WPKEY_Msk   (0xffffffu << DACC_WPMR_WPKEY_Pos)

(DACC_WPMR) Write Protect Key

Definition at line 201 of file component/dacc.h.

◆ DACC_WPMR_WPKEY_PASSWD

#define DACC_WPMR_WPKEY_PASSWD   (0x444143u << 8)

(DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0.

Definition at line 203 of file component/dacc.h.

◆ DACC_WPMR_WPKEY_Pos

#define DACC_WPMR_WPKEY_Pos   8

Definition at line 200 of file component/dacc.h.

◆ DACC_WPSR_WPVS

#define DACC_WPSR_WPVS   (0x1u << 0)

(DACC_WPSR) Write Protection Violation Status

Definition at line 205 of file component/dacc.h.

◆ DACC_WPSR_WPVSRC_Msk

#define DACC_WPSR_WPVSRC_Msk   (0xffu << DACC_WPSR_WPVSRC_Pos)

(DACC_WPSR) Write Protection Violation Source

Definition at line 207 of file component/dacc.h.

◆ DACC_WPSR_WPVSRC_Pos

#define DACC_WPSR_WPVSRC_Pos   8

Definition at line 206 of file component/dacc.h.



inertial_sense_ros
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autogenerated on Sun Feb 28 2021 03:18:01