Classes | |
| struct | Twihs |
| Twihs hardware registers. More... | |
Macros | |
| #define | TWIHS_CR_ACMDIS (0x1u << 17) |
| (TWIHS_CR) Alternative Command Mode Disable More... | |
| #define | TWIHS_CR_ACMEN (0x1u << 16) |
| (TWIHS_CR) Alternative Command Mode Enable More... | |
| #define | TWIHS_CR_CLEAR (0x1u << 15) |
| (TWIHS_CR) Bus CLEAR Command More... | |
| #define | TWIHS_CR_FIFODIS (0x1u << 29) |
| (TWIHS_CR) FIFO Disable More... | |
| #define | TWIHS_CR_FIFOEN (0x1u << 28) |
| (TWIHS_CR) FIFO Enable More... | |
| #define | TWIHS_CR_HSDIS (0x1u << 9) |
| (TWIHS_CR) TWIHS High-Speed Mode Disabled More... | |
| #define | TWIHS_CR_HSEN (0x1u << 8) |
| (TWIHS_CR) TWIHS High-Speed Mode Enabled More... | |
| #define | TWIHS_CR_LOCKCLR (0x1u << 26) |
| (TWIHS_CR) Lock Clear More... | |
| #define | TWIHS_CR_MSDIS (0x1u << 3) |
| (TWIHS_CR) TWIHS Master Mode Disabled More... | |
| #define | TWIHS_CR_MSEN (0x1u << 2) |
| (TWIHS_CR) TWIHS Master Mode Enabled More... | |
| #define | TWIHS_CR_PECDIS (0x1u << 13) |
| (TWIHS_CR) Packet Error Checking Disable More... | |
| #define | TWIHS_CR_PECEN (0x1u << 12) |
| (TWIHS_CR) Packet Error Checking Enable More... | |
| #define | TWIHS_CR_PECRQ (0x1u << 14) |
| (TWIHS_CR) PEC Request More... | |
| #define | TWIHS_CR_QUICK (0x1u << 6) |
| (TWIHS_CR) SMBus Quick Command More... | |
| #define | TWIHS_CR_SMBDIS (0x1u << 11) |
| (TWIHS_CR) SMBus Mode Disabled More... | |
| #define | TWIHS_CR_SMBEN (0x1u << 10) |
| (TWIHS_CR) SMBus Mode Enabled More... | |
| #define | TWIHS_CR_START (0x1u << 0) |
| (TWIHS_CR) Send a START Condition More... | |
| #define | TWIHS_CR_STOP (0x1u << 1) |
| (TWIHS_CR) Send a STOP Condition More... | |
| #define | TWIHS_CR_SVDIS (0x1u << 5) |
| (TWIHS_CR) TWIHS Slave Mode Disabled More... | |
| #define | TWIHS_CR_SVEN (0x1u << 4) |
| (TWIHS_CR) TWIHS Slave Mode Enabled More... | |
| #define | TWIHS_CR_SWRST (0x1u << 7) |
| (TWIHS_CR) Software Reset More... | |
| #define | TWIHS_CR_THRCLR (0x1u << 24) |
| (TWIHS_CR) Transmit Holding Register Clear More... | |
| #define | TWIHS_CWGR_CHDIV(value) ((TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos))) |
| #define | TWIHS_CWGR_CHDIV_Msk (0xffu << TWIHS_CWGR_CHDIV_Pos) |
| (TWIHS_CWGR) Clock High Divider More... | |
| #define | TWIHS_CWGR_CHDIV_Pos 8 |
| #define | TWIHS_CWGR_CKDIV(value) ((TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos))) |
| #define | TWIHS_CWGR_CKDIV_Msk (0x7u << TWIHS_CWGR_CKDIV_Pos) |
| (TWIHS_CWGR) Clock Divider More... | |
| #define | TWIHS_CWGR_CKDIV_Pos 16 |
| #define | TWIHS_CWGR_CLDIV(value) ((TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos))) |
| #define | TWIHS_CWGR_CLDIV_Msk (0xffu << TWIHS_CWGR_CLDIV_Pos) |
| (TWIHS_CWGR) Clock Low Divider More... | |
| #define | TWIHS_CWGR_CLDIV_Pos 0 |
| #define | TWIHS_CWGR_HOLD(value) ((TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos))) |
| #define | TWIHS_CWGR_HOLD_Msk (0x3fu << TWIHS_CWGR_HOLD_Pos) |
| (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling More... | |
| #define | TWIHS_CWGR_HOLD_Pos 24 |
| #define | TWIHS_DR_CLKRQ (0x1u << 1) |
| (TWIHS_DR) Clock Request More... | |
| #define | TWIHS_DR_SWEN (0x1u << 0) |
| (TWIHS_DR) SleepWalking Enable More... | |
| #define | TWIHS_DR_SWMATCH (0x1u << 2) |
| (TWIHS_DR) SleepWalking Match More... | |
| #define | TWIHS_DR_TRP (0x1u << 3) |
| (TWIHS_DR) Transfer Pending More... | |
| #define | TWIHS_FILTR_FILT (0x1u << 0) |
| (TWIHS_FILTR) RX Digital Filter More... | |
| #define | TWIHS_FILTR_PADFCFG (0x1u << 2) |
| (TWIHS_FILTR) PAD Filter Config More... | |
| #define | TWIHS_FILTR_PADFEN (0x1u << 1) |
| (TWIHS_FILTR) PAD Filter Enable More... | |
| #define | TWIHS_FILTR_THRES(value) ((TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos))) |
| #define | TWIHS_FILTR_THRES_Msk (0x7u << TWIHS_FILTR_THRES_Pos) |
| (TWIHS_FILTR) Digital Filter Threshold More... | |
| #define | TWIHS_FILTR_THRES_Pos 8 |
| #define | TWIHS_IADR_IADR(value) ((TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos))) |
| #define | TWIHS_IADR_IADR_Msk (0xffffffu << TWIHS_IADR_IADR_Pos) |
| (TWIHS_IADR) Internal Address More... | |
| #define | TWIHS_IADR_IADR_Pos 0 |
| #define | TWIHS_IDR_ARBLST (0x1u << 9) |
| (TWIHS_IDR) Arbitration Lost Interrupt Disable More... | |
| #define | TWIHS_IDR_EOSACC (0x1u << 11) |
| (TWIHS_IDR) End Of Slave Access Interrupt Disable More... | |
| #define | TWIHS_IDR_GACC (0x1u << 5) |
| (TWIHS_IDR) General Call Access Interrupt Disable More... | |
| #define | TWIHS_IDR_MCACK (0x1u << 16) |
| (TWIHS_IDR) Master Code Acknowledge Interrupt Disable More... | |
| #define | TWIHS_IDR_NACK (0x1u << 8) |
| (TWIHS_IDR) Not Acknowledge Interrupt Disable More... | |
| #define | TWIHS_IDR_OVRE (0x1u << 6) |
| (TWIHS_IDR) Overrun Error Interrupt Disable More... | |
| #define | TWIHS_IDR_PECERR (0x1u << 19) |
| (TWIHS_IDR) PEC Error Interrupt Disable More... | |
| #define | TWIHS_IDR_RXRDY (0x1u << 1) |
| (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable More... | |
| #define | TWIHS_IDR_SCL_WS (0x1u << 10) |
| (TWIHS_IDR) Clock Wait State Interrupt Disable More... | |
| #define | TWIHS_IDR_SMBDAM (0x1u << 20) |
| (TWIHS_IDR) SMBus Default Address Match Interrupt Disable More... | |
| #define | TWIHS_IDR_SMBHHM (0x1u << 21) |
| (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable More... | |
| #define | TWIHS_IDR_SVACC (0x1u << 4) |
| (TWIHS_IDR) Slave Access Interrupt Disable More... | |
| #define | TWIHS_IDR_TOUT (0x1u << 18) |
| (TWIHS_IDR) Timeout Error Interrupt Disable More... | |
| #define | TWIHS_IDR_TXCOMP (0x1u << 0) |
| (TWIHS_IDR) Transmission Completed Interrupt Disable More... | |
| #define | TWIHS_IDR_TXRDY (0x1u << 2) |
| (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable More... | |
| #define | TWIHS_IDR_UNRE (0x1u << 7) |
| (TWIHS_IDR) Underrun Error Interrupt Disable More... | |
| #define | TWIHS_IER_ARBLST (0x1u << 9) |
| (TWIHS_IER) Arbitration Lost Interrupt Enable More... | |
| #define | TWIHS_IER_EOSACC (0x1u << 11) |
| (TWIHS_IER) End Of Slave Access Interrupt Enable More... | |
| #define | TWIHS_IER_GACC (0x1u << 5) |
| (TWIHS_IER) General Call Access Interrupt Enable More... | |
| #define | TWIHS_IER_MCACK (0x1u << 16) |
| (TWIHS_IER) Master Code Acknowledge Interrupt Enable More... | |
| #define | TWIHS_IER_NACK (0x1u << 8) |
| (TWIHS_IER) Not Acknowledge Interrupt Enable More... | |
| #define | TWIHS_IER_OVRE (0x1u << 6) |
| (TWIHS_IER) Overrun Error Interrupt Enable More... | |
| #define | TWIHS_IER_PECERR (0x1u << 19) |
| (TWIHS_IER) PEC Error Interrupt Enable More... | |
| #define | TWIHS_IER_RXRDY (0x1u << 1) |
| (TWIHS_IER) Receive Holding Register Ready Interrupt Enable More... | |
| #define | TWIHS_IER_SCL_WS (0x1u << 10) |
| (TWIHS_IER) Clock Wait State Interrupt Enable More... | |
| #define | TWIHS_IER_SMBDAM (0x1u << 20) |
| (TWIHS_IER) SMBus Default Address Match Interrupt Enable More... | |
| #define | TWIHS_IER_SMBHHM (0x1u << 21) |
| (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable More... | |
| #define | TWIHS_IER_SVACC (0x1u << 4) |
| (TWIHS_IER) Slave Access Interrupt Enable More... | |
| #define | TWIHS_IER_TOUT (0x1u << 18) |
| (TWIHS_IER) Timeout Error Interrupt Enable More... | |
| #define | TWIHS_IER_TXCOMP (0x1u << 0) |
| (TWIHS_IER) Transmission Completed Interrupt Enable More... | |
| #define | TWIHS_IER_TXRDY (0x1u << 2) |
| (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable More... | |
| #define | TWIHS_IER_UNRE (0x1u << 7) |
| (TWIHS_IER) Underrun Error Interrupt Enable More... | |
| #define | TWIHS_IMR_ARBLST (0x1u << 9) |
| (TWIHS_IMR) Arbitration Lost Interrupt Mask More... | |
| #define | TWIHS_IMR_EOSACC (0x1u << 11) |
| (TWIHS_IMR) End Of Slave Access Interrupt Mask More... | |
| #define | TWIHS_IMR_GACC (0x1u << 5) |
| (TWIHS_IMR) General Call Access Interrupt Mask More... | |
| #define | TWIHS_IMR_MCACK (0x1u << 16) |
| (TWIHS_IMR) Master Code Acknowledge Interrupt Mask More... | |
| #define | TWIHS_IMR_NACK (0x1u << 8) |
| (TWIHS_IMR) Not Acknowledge Interrupt Mask More... | |
| #define | TWIHS_IMR_OVRE (0x1u << 6) |
| (TWIHS_IMR) Overrun Error Interrupt Mask More... | |
| #define | TWIHS_IMR_PECERR (0x1u << 19) |
| (TWIHS_IMR) PEC Error Interrupt Mask More... | |
| #define | TWIHS_IMR_RXRDY (0x1u << 1) |
| (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask More... | |
| #define | TWIHS_IMR_SCL_WS (0x1u << 10) |
| (TWIHS_IMR) Clock Wait State Interrupt Mask More... | |
| #define | TWIHS_IMR_SMBDAM (0x1u << 20) |
| (TWIHS_IMR) SMBus Default Address Match Interrupt Mask More... | |
| #define | TWIHS_IMR_SMBHHM (0x1u << 21) |
| (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask More... | |
| #define | TWIHS_IMR_SVACC (0x1u << 4) |
| (TWIHS_IMR) Slave Access Interrupt Mask More... | |
| #define | TWIHS_IMR_TOUT (0x1u << 18) |
| (TWIHS_IMR) Timeout Error Interrupt Mask More... | |
| #define | TWIHS_IMR_TXCOMP (0x1u << 0) |
| (TWIHS_IMR) Transmission Completed Interrupt Mask More... | |
| #define | TWIHS_IMR_TXRDY (0x1u << 2) |
| (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask More... | |
| #define | TWIHS_IMR_UNRE (0x1u << 7) |
| (TWIHS_IMR) Underrun Error Interrupt Mask More... | |
| #define | TWIHS_MMR_DADR(value) ((TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos))) |
| #define | TWIHS_MMR_DADR_Msk (0x7fu << TWIHS_MMR_DADR_Pos) |
| (TWIHS_MMR) Device Address More... | |
| #define | TWIHS_MMR_DADR_Pos 16 |
| #define | TWIHS_MMR_IADRSZ(value) ((TWIHS_MMR_IADRSZ_Msk & ((value) << TWIHS_MMR_IADRSZ_Pos))) |
| #define | TWIHS_MMR_IADRSZ_1_BYTE (0x1u << 8) |
| (TWIHS_MMR) One-byte internal device address More... | |
| #define | TWIHS_MMR_IADRSZ_2_BYTE (0x2u << 8) |
| (TWIHS_MMR) Two-byte internal device address More... | |
| #define | TWIHS_MMR_IADRSZ_3_BYTE (0x3u << 8) |
| (TWIHS_MMR) Three-byte internal device address More... | |
| #define | TWIHS_MMR_IADRSZ_Msk (0x3u << TWIHS_MMR_IADRSZ_Pos) |
| (TWIHS_MMR) Internal Device Address Size More... | |
| #define | TWIHS_MMR_IADRSZ_NONE (0x0u << 8) |
| (TWIHS_MMR) No internal device address More... | |
| #define | TWIHS_MMR_IADRSZ_Pos 8 |
| #define | TWIHS_MMR_MREAD (0x1u << 12) |
| (TWIHS_MMR) Master Read Direction More... | |
| #define | TWIHS_RHR_RXDATA_Msk (0xffu << TWIHS_RHR_RXDATA_Pos) |
| (TWIHS_RHR) Master or Slave Receive Holding Data More... | |
| #define | TWIHS_RHR_RXDATA_Pos 0 |
| #define | TWIHS_SMBTR_PRESC(value) ((TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos))) |
| #define | TWIHS_SMBTR_PRESC_Msk (0xfu << TWIHS_SMBTR_PRESC_Pos) |
| (TWIHS_SMBTR) SMBus Clock Prescaler More... | |
| #define | TWIHS_SMBTR_PRESC_Pos 0 |
| #define | TWIHS_SMBTR_THMAX(value) ((TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos))) |
| #define | TWIHS_SMBTR_THMAX_Msk (0xffu << TWIHS_SMBTR_THMAX_Pos) |
| (TWIHS_SMBTR) Clock High Maximum Cycles More... | |
| #define | TWIHS_SMBTR_THMAX_Pos 24 |
| #define | TWIHS_SMBTR_TLOWM(value) ((TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos))) |
| #define | TWIHS_SMBTR_TLOWM_Msk (0xffu << TWIHS_SMBTR_TLOWM_Pos) |
| (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles More... | |
| #define | TWIHS_SMBTR_TLOWM_Pos 16 |
| #define | TWIHS_SMBTR_TLOWS(value) ((TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos))) |
| #define | TWIHS_SMBTR_TLOWS_Msk (0xffu << TWIHS_SMBTR_TLOWS_Pos) |
| (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles More... | |
| #define | TWIHS_SMBTR_TLOWS_Pos 8 |
| #define | TWIHS_SMR_DATAMEN (0x1u << 31) |
| (TWIHS_SMR) Data Matching Enable More... | |
| #define | TWIHS_SMR_MASK(value) ((TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos))) |
| #define | TWIHS_SMR_MASK_Msk (0x7fu << TWIHS_SMR_MASK_Pos) |
| (TWIHS_SMR) Slave Address Mask More... | |
| #define | TWIHS_SMR_MASK_Pos 8 |
| #define | TWIHS_SMR_NACKEN (0x1u << 0) |
| (TWIHS_SMR) Slave Receiver Data Phase NACK enable More... | |
| #define | TWIHS_SMR_SADR(value) ((TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos))) |
| #define | TWIHS_SMR_SADR1EN (0x1u << 28) |
| (TWIHS_SMR) Slave Address 1 Enable More... | |
| #define | TWIHS_SMR_SADR2EN (0x1u << 29) |
| (TWIHS_SMR) Slave Address 2 Enable More... | |
| #define | TWIHS_SMR_SADR3EN (0x1u << 30) |
| (TWIHS_SMR) Slave Address 3 Enable More... | |
| #define | TWIHS_SMR_SADR_Msk (0x7fu << TWIHS_SMR_SADR_Pos) |
| (TWIHS_SMR) Slave Address More... | |
| #define | TWIHS_SMR_SADR_Pos 16 |
| #define | TWIHS_SMR_SCLWSDIS (0x1u << 6) |
| (TWIHS_SMR) Clock Wait State Disable More... | |
| #define | TWIHS_SMR_SMDA (0x1u << 2) |
| (TWIHS_SMR) SMBus Default Address More... | |
| #define | TWIHS_SMR_SMHH (0x1u << 3) |
| (TWIHS_SMR) SMBus Host Header More... | |
| #define | TWIHS_SR_ARBLST (0x1u << 9) |
| (TWIHS_SR) Arbitration Lost (cleared on read) More... | |
| #define | TWIHS_SR_EOSACC (0x1u << 11) |
| (TWIHS_SR) End Of Slave Access (cleared on read) More... | |
| #define | TWIHS_SR_GACC (0x1u << 5) |
| (TWIHS_SR) General Call Access (cleared on read) More... | |
| #define | TWIHS_SR_MCACK (0x1u << 16) |
| (TWIHS_SR) Master Code Acknowledge (cleared on read) More... | |
| #define | TWIHS_SR_NACK (0x1u << 8) |
| (TWIHS_SR) Not Acknowledged (cleared on read) More... | |
| #define | TWIHS_SR_OVRE (0x1u << 6) |
| (TWIHS_SR) Overrun Error (cleared on read) More... | |
| #define | TWIHS_SR_PECERR (0x1u << 19) |
| (TWIHS_SR) PEC Error (cleared on read) More... | |
| #define | TWIHS_SR_RXRDY (0x1u << 1) |
| (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) More... | |
| #define | TWIHS_SR_SCL (0x1u << 24) |
| (TWIHS_SR) SCL line value More... | |
| #define | TWIHS_SR_SCLWS (0x1u << 10) |
| (TWIHS_SR) Clock Wait State More... | |
| #define | TWIHS_SR_SDA (0x1u << 25) |
| (TWIHS_SR) SDA line value More... | |
| #define | TWIHS_SR_SMBDAM (0x1u << 20) |
| (TWIHS_SR) SMBus Default Address Match (cleared on read) More... | |
| #define | TWIHS_SR_SMBHHM (0x1u << 21) |
| (TWIHS_SR) SMBus Host Header Address Match (cleared on read) More... | |
| #define | TWIHS_SR_SVACC (0x1u << 4) |
| (TWIHS_SR) Slave Access More... | |
| #define | TWIHS_SR_SVREAD (0x1u << 3) |
| (TWIHS_SR) Slave Read More... | |
| #define | TWIHS_SR_TOUT (0x1u << 18) |
| (TWIHS_SR) Timeout Error (cleared on read) More... | |
| #define | TWIHS_SR_TXCOMP (0x1u << 0) |
| (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) More... | |
| #define | TWIHS_SR_TXRDY (0x1u << 2) |
| (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) More... | |
| #define | TWIHS_SR_UNRE (0x1u << 7) |
| (TWIHS_SR) Underrun Error (cleared on read) More... | |
| #define | TWIHS_SWMR_DATAM(value) ((TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos))) |
| #define | TWIHS_SWMR_DATAM_Msk (0xffu << TWIHS_SWMR_DATAM_Pos) |
| (TWIHS_SWMR) Data Match More... | |
| #define | TWIHS_SWMR_DATAM_Pos 24 |
| #define | TWIHS_SWMR_SADR1(value) ((TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos))) |
| #define | TWIHS_SWMR_SADR1_Msk (0x7fu << TWIHS_SWMR_SADR1_Pos) |
| (TWIHS_SWMR) Slave Address 1 More... | |
| #define | TWIHS_SWMR_SADR1_Pos 0 |
| #define | TWIHS_SWMR_SADR2(value) ((TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos))) |
| #define | TWIHS_SWMR_SADR2_Msk (0x7fu << TWIHS_SWMR_SADR2_Pos) |
| (TWIHS_SWMR) Slave Address 2 More... | |
| #define | TWIHS_SWMR_SADR2_Pos 8 |
| #define | TWIHS_SWMR_SADR3(value) ((TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos))) |
| #define | TWIHS_SWMR_SADR3_Msk (0x7fu << TWIHS_SWMR_SADR3_Pos) |
| (TWIHS_SWMR) Slave Address 3 More... | |
| #define | TWIHS_SWMR_SADR3_Pos 16 |
| #define | TWIHS_THR_TXDATA(value) ((TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos))) |
| #define | TWIHS_THR_TXDATA_Msk (0xffu << TWIHS_THR_TXDATA_Pos) |
| (TWIHS_THR) Master or Slave Transmit Holding Data More... | |
| #define | TWIHS_THR_TXDATA_Pos 0 |
| #define | TWIHS_VER_MFN_Msk (0x7u << TWIHS_VER_MFN_Pos) |
| (TWIHS_VER) Metal Fix Number More... | |
| #define | TWIHS_VER_MFN_Pos 16 |
| #define | TWIHS_VER_VERSION_Msk (0xfffu << TWIHS_VER_VERSION_Pos) |
| (TWIHS_VER) Version of the Hardware Module More... | |
| #define | TWIHS_VER_VERSION_Pos 0 |
| #define | TWIHS_WPMR_WPEN (0x1u << 0) |
| (TWIHS_WPMR) Write Protection Enable More... | |
| #define | TWIHS_WPMR_WPKEY(value) ((TWIHS_WPMR_WPKEY_Msk & ((value) << TWIHS_WPMR_WPKEY_Pos))) |
| #define | TWIHS_WPMR_WPKEY_Msk (0xffffffu << TWIHS_WPMR_WPKEY_Pos) |
| (TWIHS_WPMR) Write Protection Key More... | |
| #define | TWIHS_WPMR_WPKEY_PASSWD (0x545749u << 8) |
| (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 More... | |
| #define | TWIHS_WPMR_WPKEY_Pos 8 |
| #define | TWIHS_WPSR_WPVS (0x1u << 0) |
| (TWIHS_WPSR) Write Protection Violation Status More... | |
| #define | TWIHS_WPSR_WPVSRC_Msk (0xffffffu << TWIHS_WPSR_WPVSRC_Pos) |
| (TWIHS_WPSR) Write Protection Violation Source More... | |
| #define | TWIHS_WPSR_WPVSRC_Pos 8 |
SOFTWARE API DEFINITION FOR Two-wire Interface High Speed
| #define TWIHS_CR_ACMDIS (0x1u << 17) |
(TWIHS_CR) Alternative Command Mode Disable
Definition at line 91 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CR_ACMEN (0x1u << 16) |
(TWIHS_CR) Alternative Command Mode Enable
Definition at line 90 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CR_CLEAR (0x1u << 15) |
(TWIHS_CR) Bus CLEAR Command
Definition at line 89 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CR_FIFODIS (0x1u << 29) |
(TWIHS_CR) FIFO Disable
Definition at line 95 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CR_FIFOEN (0x1u << 28) |
(TWIHS_CR) FIFO Enable
Definition at line 94 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CR_HSDIS (0x1u << 9) |
(TWIHS_CR) TWIHS High-Speed Mode Disabled
Definition at line 83 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CR_HSEN (0x1u << 8) |
(TWIHS_CR) TWIHS High-Speed Mode Enabled
Definition at line 82 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CR_LOCKCLR (0x1u << 26) |
(TWIHS_CR) Lock Clear
Definition at line 93 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CR_MSDIS (0x1u << 3) |
(TWIHS_CR) TWIHS Master Mode Disabled
Definition at line 77 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CR_MSEN (0x1u << 2) |
(TWIHS_CR) TWIHS Master Mode Enabled
Definition at line 76 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CR_PECDIS (0x1u << 13) |
(TWIHS_CR) Packet Error Checking Disable
Definition at line 87 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CR_PECEN (0x1u << 12) |
(TWIHS_CR) Packet Error Checking Enable
Definition at line 86 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CR_PECRQ (0x1u << 14) |
(TWIHS_CR) PEC Request
Definition at line 88 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CR_QUICK (0x1u << 6) |
(TWIHS_CR) SMBus Quick Command
Definition at line 80 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CR_SMBDIS (0x1u << 11) |
(TWIHS_CR) SMBus Mode Disabled
Definition at line 85 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CR_SMBEN (0x1u << 10) |
(TWIHS_CR) SMBus Mode Enabled
Definition at line 84 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CR_START (0x1u << 0) |
(TWIHS_CR) Send a START Condition
Definition at line 74 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CR_STOP (0x1u << 1) |
(TWIHS_CR) Send a STOP Condition
Definition at line 75 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CR_SVDIS (0x1u << 5) |
(TWIHS_CR) TWIHS Slave Mode Disabled
Definition at line 79 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CR_SVEN (0x1u << 4) |
(TWIHS_CR) TWIHS Slave Mode Enabled
Definition at line 78 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CR_SWRST (0x1u << 7) |
(TWIHS_CR) Software Reset
Definition at line 81 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CR_THRCLR (0x1u << 24) |
(TWIHS_CR) Transmit Holding Register Clear
Definition at line 92 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CWGR_CHDIV | ( | value | ) | ((TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos))) |
Definition at line 133 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CWGR_CHDIV_Msk (0xffu << TWIHS_CWGR_CHDIV_Pos) |
(TWIHS_CWGR) Clock High Divider
Definition at line 132 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CWGR_CHDIV_Pos 8 |
Definition at line 131 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CWGR_CKDIV | ( | value | ) | ((TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos))) |
Definition at line 136 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CWGR_CKDIV_Msk (0x7u << TWIHS_CWGR_CKDIV_Pos) |
(TWIHS_CWGR) Clock Divider
Definition at line 135 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CWGR_CKDIV_Pos 16 |
Definition at line 134 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CWGR_CLDIV | ( | value | ) | ((TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos))) |
Definition at line 130 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CWGR_CLDIV_Msk (0xffu << TWIHS_CWGR_CLDIV_Pos) |
(TWIHS_CWGR) Clock Low Divider
Definition at line 129 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CWGR_CLDIV_Pos 0 |
Definition at line 128 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CWGR_HOLD | ( | value | ) | ((TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos))) |
Definition at line 139 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CWGR_HOLD_Msk (0x3fu << TWIHS_CWGR_HOLD_Pos) |
(TWIHS_CWGR) TWD Hold Time Versus TWCK Falling
Definition at line 138 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_CWGR_HOLD_Pos 24 |
Definition at line 137 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_DR_CLKRQ (0x1u << 1) |
(TWIHS_DR) Clock Request
Definition at line 253 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_DR_SWEN (0x1u << 0) |
(TWIHS_DR) SleepWalking Enable
Definition at line 252 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_DR_SWMATCH (0x1u << 2) |
(TWIHS_DR) SleepWalking Match
Definition at line 254 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_DR_TRP (0x1u << 3) |
(TWIHS_DR) Transfer Pending
Definition at line 255 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_FILTR_FILT (0x1u << 0) |
(TWIHS_FILTR) RX Digital Filter
Definition at line 232 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_FILTR_PADFCFG (0x1u << 2) |
(TWIHS_FILTR) PAD Filter Config
Definition at line 234 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_FILTR_PADFEN (0x1u << 1) |
(TWIHS_FILTR) PAD Filter Enable
Definition at line 233 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_FILTR_THRES | ( | value | ) | ((TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos))) |
Definition at line 237 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_FILTR_THRES_Msk (0x7u << TWIHS_FILTR_THRES_Pos) |
(TWIHS_FILTR) Digital Filter Threshold
Definition at line 236 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_FILTR_THRES_Pos 8 |
Definition at line 235 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IADR_IADR | ( | value | ) | ((TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos))) |
Definition at line 126 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IADR_IADR_Msk (0xffffffu << TWIHS_IADR_IADR_Pos) |
(TWIHS_IADR) Internal Address
Definition at line 125 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IADR_IADR_Pos 0 |
Definition at line 124 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IDR_ARBLST (0x1u << 9) |
(TWIHS_IDR) Arbitration Lost Interrupt Disable
Definition at line 186 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IDR_EOSACC (0x1u << 11) |
(TWIHS_IDR) End Of Slave Access Interrupt Disable
Definition at line 188 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IDR_GACC (0x1u << 5) |
(TWIHS_IDR) General Call Access Interrupt Disable
Definition at line 182 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IDR_MCACK (0x1u << 16) |
(TWIHS_IDR) Master Code Acknowledge Interrupt Disable
Definition at line 189 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IDR_NACK (0x1u << 8) |
(TWIHS_IDR) Not Acknowledge Interrupt Disable
Definition at line 185 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IDR_OVRE (0x1u << 6) |
(TWIHS_IDR) Overrun Error Interrupt Disable
Definition at line 183 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IDR_PECERR (0x1u << 19) |
(TWIHS_IDR) PEC Error Interrupt Disable
Definition at line 191 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IDR_RXRDY (0x1u << 1) |
(TWIHS_IDR) Receive Holding Register Ready Interrupt Disable
Definition at line 179 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IDR_SCL_WS (0x1u << 10) |
(TWIHS_IDR) Clock Wait State Interrupt Disable
Definition at line 187 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IDR_SMBDAM (0x1u << 20) |
(TWIHS_IDR) SMBus Default Address Match Interrupt Disable
Definition at line 192 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IDR_SMBHHM (0x1u << 21) |
(TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable
Definition at line 193 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IDR_SVACC (0x1u << 4) |
(TWIHS_IDR) Slave Access Interrupt Disable
Definition at line 181 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IDR_TOUT (0x1u << 18) |
(TWIHS_IDR) Timeout Error Interrupt Disable
Definition at line 190 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IDR_TXCOMP (0x1u << 0) |
(TWIHS_IDR) Transmission Completed Interrupt Disable
Definition at line 178 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IDR_TXRDY (0x1u << 2) |
(TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable
Definition at line 180 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IDR_UNRE (0x1u << 7) |
(TWIHS_IDR) Underrun Error Interrupt Disable
Definition at line 184 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IER_ARBLST (0x1u << 9) |
(TWIHS_IER) Arbitration Lost Interrupt Enable
Definition at line 169 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IER_EOSACC (0x1u << 11) |
(TWIHS_IER) End Of Slave Access Interrupt Enable
Definition at line 171 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IER_GACC (0x1u << 5) |
(TWIHS_IER) General Call Access Interrupt Enable
Definition at line 165 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IER_MCACK (0x1u << 16) |
(TWIHS_IER) Master Code Acknowledge Interrupt Enable
Definition at line 172 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IER_NACK (0x1u << 8) |
(TWIHS_IER) Not Acknowledge Interrupt Enable
Definition at line 168 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IER_OVRE (0x1u << 6) |
(TWIHS_IER) Overrun Error Interrupt Enable
Definition at line 166 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IER_PECERR (0x1u << 19) |
(TWIHS_IER) PEC Error Interrupt Enable
Definition at line 174 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IER_RXRDY (0x1u << 1) |
(TWIHS_IER) Receive Holding Register Ready Interrupt Enable
Definition at line 162 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IER_SCL_WS (0x1u << 10) |
(TWIHS_IER) Clock Wait State Interrupt Enable
Definition at line 170 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IER_SMBDAM (0x1u << 20) |
(TWIHS_IER) SMBus Default Address Match Interrupt Enable
Definition at line 175 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IER_SMBHHM (0x1u << 21) |
(TWIHS_IER) SMBus Host Header Address Match Interrupt Enable
Definition at line 176 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IER_SVACC (0x1u << 4) |
(TWIHS_IER) Slave Access Interrupt Enable
Definition at line 164 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IER_TOUT (0x1u << 18) |
(TWIHS_IER) Timeout Error Interrupt Enable
Definition at line 173 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IER_TXCOMP (0x1u << 0) |
(TWIHS_IER) Transmission Completed Interrupt Enable
Definition at line 161 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IER_TXRDY (0x1u << 2) |
(TWIHS_IER) Transmit Holding Register Ready Interrupt Enable
Definition at line 163 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IER_UNRE (0x1u << 7) |
(TWIHS_IER) Underrun Error Interrupt Enable
Definition at line 167 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IMR_ARBLST (0x1u << 9) |
(TWIHS_IMR) Arbitration Lost Interrupt Mask
Definition at line 203 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IMR_EOSACC (0x1u << 11) |
(TWIHS_IMR) End Of Slave Access Interrupt Mask
Definition at line 205 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IMR_GACC (0x1u << 5) |
(TWIHS_IMR) General Call Access Interrupt Mask
Definition at line 199 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IMR_MCACK (0x1u << 16) |
(TWIHS_IMR) Master Code Acknowledge Interrupt Mask
Definition at line 206 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IMR_NACK (0x1u << 8) |
(TWIHS_IMR) Not Acknowledge Interrupt Mask
Definition at line 202 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IMR_OVRE (0x1u << 6) |
(TWIHS_IMR) Overrun Error Interrupt Mask
Definition at line 200 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IMR_PECERR (0x1u << 19) |
(TWIHS_IMR) PEC Error Interrupt Mask
Definition at line 208 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IMR_RXRDY (0x1u << 1) |
(TWIHS_IMR) Receive Holding Register Ready Interrupt Mask
Definition at line 196 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IMR_SCL_WS (0x1u << 10) |
(TWIHS_IMR) Clock Wait State Interrupt Mask
Definition at line 204 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IMR_SMBDAM (0x1u << 20) |
(TWIHS_IMR) SMBus Default Address Match Interrupt Mask
Definition at line 209 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IMR_SMBHHM (0x1u << 21) |
(TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask
Definition at line 210 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IMR_SVACC (0x1u << 4) |
(TWIHS_IMR) Slave Access Interrupt Mask
Definition at line 198 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IMR_TOUT (0x1u << 18) |
(TWIHS_IMR) Timeout Error Interrupt Mask
Definition at line 207 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IMR_TXCOMP (0x1u << 0) |
(TWIHS_IMR) Transmission Completed Interrupt Mask
Definition at line 195 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IMR_TXRDY (0x1u << 2) |
(TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask
Definition at line 197 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_IMR_UNRE (0x1u << 7) |
(TWIHS_IMR) Underrun Error Interrupt Mask
Definition at line 201 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_MMR_DADR | ( | value | ) | ((TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos))) |
Definition at line 107 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_MMR_DADR_Msk (0x7fu << TWIHS_MMR_DADR_Pos) |
(TWIHS_MMR) Device Address
Definition at line 106 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_MMR_DADR_Pos 16 |
Definition at line 105 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_MMR_IADRSZ | ( | value | ) | ((TWIHS_MMR_IADRSZ_Msk & ((value) << TWIHS_MMR_IADRSZ_Pos))) |
Definition at line 99 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_MMR_IADRSZ_1_BYTE (0x1u << 8) |
(TWIHS_MMR) One-byte internal device address
Definition at line 101 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_MMR_IADRSZ_2_BYTE (0x2u << 8) |
(TWIHS_MMR) Two-byte internal device address
Definition at line 102 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_MMR_IADRSZ_3_BYTE (0x3u << 8) |
(TWIHS_MMR) Three-byte internal device address
Definition at line 103 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_MMR_IADRSZ_Msk (0x3u << TWIHS_MMR_IADRSZ_Pos) |
(TWIHS_MMR) Internal Device Address Size
Definition at line 98 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_MMR_IADRSZ_NONE (0x0u << 8) |
(TWIHS_MMR) No internal device address
Definition at line 100 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_MMR_IADRSZ_Pos 8 |
Definition at line 97 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_MMR_MREAD (0x1u << 12) |
(TWIHS_MMR) Master Read Direction
Definition at line 104 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_RHR_RXDATA_Msk (0xffu << TWIHS_RHR_RXDATA_Pos) |
(TWIHS_RHR) Master or Slave Receive Holding Data
Definition at line 213 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_RHR_RXDATA_Pos 0 |
Definition at line 212 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMBTR_PRESC | ( | value | ) | ((TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos))) |
Definition at line 221 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMBTR_PRESC_Msk (0xfu << TWIHS_SMBTR_PRESC_Pos) |
(TWIHS_SMBTR) SMBus Clock Prescaler
Definition at line 220 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMBTR_PRESC_Pos 0 |
Definition at line 219 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMBTR_THMAX | ( | value | ) | ((TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos))) |
Definition at line 230 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMBTR_THMAX_Msk (0xffu << TWIHS_SMBTR_THMAX_Pos) |
(TWIHS_SMBTR) Clock High Maximum Cycles
Definition at line 229 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMBTR_THMAX_Pos 24 |
Definition at line 228 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMBTR_TLOWM | ( | value | ) | ((TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos))) |
Definition at line 227 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMBTR_TLOWM_Msk (0xffu << TWIHS_SMBTR_TLOWM_Pos) |
(TWIHS_SMBTR) Master Clock Stretch Maximum Cycles
Definition at line 226 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMBTR_TLOWM_Pos 16 |
Definition at line 225 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMBTR_TLOWS | ( | value | ) | ((TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos))) |
Definition at line 224 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMBTR_TLOWS_Msk (0xffu << TWIHS_SMBTR_TLOWS_Pos) |
(TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles
Definition at line 223 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMBTR_TLOWS_Pos 8 |
Definition at line 222 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMR_DATAMEN (0x1u << 31) |
(TWIHS_SMR) Data Matching Enable
Definition at line 122 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMR_MASK | ( | value | ) | ((TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos))) |
Definition at line 115 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMR_MASK_Msk (0x7fu << TWIHS_SMR_MASK_Pos) |
(TWIHS_SMR) Slave Address Mask
Definition at line 114 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMR_MASK_Pos 8 |
Definition at line 113 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMR_NACKEN (0x1u << 0) |
(TWIHS_SMR) Slave Receiver Data Phase NACK enable
Definition at line 109 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMR_SADR | ( | value | ) | ((TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos))) |
Definition at line 118 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMR_SADR1EN (0x1u << 28) |
(TWIHS_SMR) Slave Address 1 Enable
Definition at line 119 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMR_SADR2EN (0x1u << 29) |
(TWIHS_SMR) Slave Address 2 Enable
Definition at line 120 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMR_SADR3EN (0x1u << 30) |
(TWIHS_SMR) Slave Address 3 Enable
Definition at line 121 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMR_SADR_Msk (0x7fu << TWIHS_SMR_SADR_Pos) |
(TWIHS_SMR) Slave Address
Definition at line 117 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMR_SADR_Pos 16 |
Definition at line 116 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMR_SCLWSDIS (0x1u << 6) |
(TWIHS_SMR) Clock Wait State Disable
Definition at line 112 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMR_SMDA (0x1u << 2) |
(TWIHS_SMR) SMBus Default Address
Definition at line 110 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SMR_SMHH (0x1u << 3) |
(TWIHS_SMR) SMBus Host Header
Definition at line 111 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SR_ARBLST (0x1u << 9) |
(TWIHS_SR) Arbitration Lost (cleared on read)
Definition at line 150 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SR_EOSACC (0x1u << 11) |
(TWIHS_SR) End Of Slave Access (cleared on read)
Definition at line 152 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SR_GACC (0x1u << 5) |
(TWIHS_SR) General Call Access (cleared on read)
Definition at line 146 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SR_MCACK (0x1u << 16) |
(TWIHS_SR) Master Code Acknowledge (cleared on read)
Definition at line 153 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SR_NACK (0x1u << 8) |
(TWIHS_SR) Not Acknowledged (cleared on read)
Definition at line 149 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SR_OVRE (0x1u << 6) |
(TWIHS_SR) Overrun Error (cleared on read)
Definition at line 147 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SR_PECERR (0x1u << 19) |
(TWIHS_SR) PEC Error (cleared on read)
Definition at line 155 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SR_RXRDY (0x1u << 1) |
(TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR)
Definition at line 142 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SR_SCL (0x1u << 24) |
(TWIHS_SR) SCL line value
Definition at line 158 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SR_SCLWS (0x1u << 10) |
(TWIHS_SR) Clock Wait State
Definition at line 151 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SR_SDA (0x1u << 25) |
(TWIHS_SR) SDA line value
Definition at line 159 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SR_SMBDAM (0x1u << 20) |
(TWIHS_SR) SMBus Default Address Match (cleared on read)
Definition at line 156 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SR_SMBHHM (0x1u << 21) |
(TWIHS_SR) SMBus Host Header Address Match (cleared on read)
Definition at line 157 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SR_SVACC (0x1u << 4) |
(TWIHS_SR) Slave Access
Definition at line 145 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SR_SVREAD (0x1u << 3) |
(TWIHS_SR) Slave Read
Definition at line 144 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SR_TOUT (0x1u << 18) |
(TWIHS_SR) Timeout Error (cleared on read)
Definition at line 154 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SR_TXCOMP (0x1u << 0) |
(TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR)
Definition at line 141 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SR_TXRDY (0x1u << 2) |
(TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR)
Definition at line 143 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SR_UNRE (0x1u << 7) |
(TWIHS_SR) Underrun Error (cleared on read)
Definition at line 148 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SWMR_DATAM | ( | value | ) | ((TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos))) |
Definition at line 250 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SWMR_DATAM_Msk (0xffu << TWIHS_SWMR_DATAM_Pos) |
(TWIHS_SWMR) Data Match
Definition at line 249 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SWMR_DATAM_Pos 24 |
Definition at line 248 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SWMR_SADR1 | ( | value | ) | ((TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos))) |
Definition at line 241 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SWMR_SADR1_Msk (0x7fu << TWIHS_SWMR_SADR1_Pos) |
(TWIHS_SWMR) Slave Address 1
Definition at line 240 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SWMR_SADR1_Pos 0 |
Definition at line 239 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SWMR_SADR2 | ( | value | ) | ((TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos))) |
Definition at line 244 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SWMR_SADR2_Msk (0x7fu << TWIHS_SWMR_SADR2_Pos) |
(TWIHS_SWMR) Slave Address 2
Definition at line 243 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SWMR_SADR2_Pos 8 |
Definition at line 242 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SWMR_SADR3 | ( | value | ) | ((TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos))) |
Definition at line 247 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SWMR_SADR3_Msk (0x7fu << TWIHS_SWMR_SADR3_Pos) |
(TWIHS_SWMR) Slave Address 3
Definition at line 246 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_SWMR_SADR3_Pos 16 |
Definition at line 245 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_THR_TXDATA | ( | value | ) | ((TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos))) |
Definition at line 217 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_THR_TXDATA_Msk (0xffu << TWIHS_THR_TXDATA_Pos) |
(TWIHS_THR) Master or Slave Transmit Holding Data
Definition at line 216 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_THR_TXDATA_Pos 0 |
Definition at line 215 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_VER_MFN_Msk (0x7u << TWIHS_VER_MFN_Pos) |
(TWIHS_VER) Metal Fix Number
Definition at line 270 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_VER_MFN_Pos 16 |
Definition at line 269 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_VER_VERSION_Msk (0xfffu << TWIHS_VER_VERSION_Pos) |
(TWIHS_VER) Version of the Hardware Module
Definition at line 268 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_VER_VERSION_Pos 0 |
Definition at line 267 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_WPMR_WPEN (0x1u << 0) |
(TWIHS_WPMR) Write Protection Enable
Definition at line 257 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_WPMR_WPKEY | ( | value | ) | ((TWIHS_WPMR_WPKEY_Msk & ((value) << TWIHS_WPMR_WPKEY_Pos))) |
Definition at line 260 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_WPMR_WPKEY_Msk (0xffffffu << TWIHS_WPMR_WPKEY_Pos) |
(TWIHS_WPMR) Write Protection Key
Definition at line 259 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_WPMR_WPKEY_PASSWD (0x545749u << 8) |
(TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0
Definition at line 261 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_WPMR_WPKEY_Pos 8 |
Definition at line 258 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_WPSR_WPVS (0x1u << 0) |
(TWIHS_WPSR) Write Protection Violation Status
Definition at line 263 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_WPSR_WPVSRC_Msk (0xffffffu << TWIHS_WPSR_WPVSRC_Pos) |
(TWIHS_WPSR) Write Protection Violation Source
Definition at line 265 of file utils/cmsis/same70/include/component/twihs.h.
| #define TWIHS_WPSR_WPVSRC_Pos 8 |
Definition at line 264 of file utils/cmsis/same70/include/component/twihs.h.