30 #ifndef __STM32F4xx_IWDG_H 31 #define __STM32F4xx_IWDG_H 58 #define IWDG_WriteAccess_Enable ((uint16_t)0x5555) 59 #define IWDG_WriteAccess_Disable ((uint16_t)0x0000) 60 #define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ 61 ((ACCESS) == IWDG_WriteAccess_Disable)) 69 #define IWDG_Prescaler_4 ((uint8_t)0x00) 70 #define IWDG_Prescaler_8 ((uint8_t)0x01) 71 #define IWDG_Prescaler_16 ((uint8_t)0x02) 72 #define IWDG_Prescaler_32 ((uint8_t)0x03) 73 #define IWDG_Prescaler_64 ((uint8_t)0x04) 74 #define IWDG_Prescaler_128 ((uint8_t)0x05) 75 #define IWDG_Prescaler_256 ((uint8_t)0x06) 76 #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ 77 ((PRESCALER) == IWDG_Prescaler_8) || \ 78 ((PRESCALER) == IWDG_Prescaler_16) || \ 79 ((PRESCALER) == IWDG_Prescaler_32) || \ 80 ((PRESCALER) == IWDG_Prescaler_64) || \ 81 ((PRESCALER) == IWDG_Prescaler_128)|| \ 82 ((PRESCALER) == IWDG_Prescaler_256)) 90 #define IWDG_FLAG_PVU ((uint16_t)0x0001) 91 #define IWDG_FLAG_RVU ((uint16_t)0x0002) 92 #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) 93 #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
void IWDG_Enable(void)
Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
Enables or disables write access to IWDG_PR and IWDG_RLR registers.
void IWDG_ReloadCounter(void)
Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR ...
void IWDG_SetReload(uint16_t Reload)
Sets IWDG Reload value.
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
Sets IWDG Prescaler value.
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
Checks whether the specified IWDG flag is set or not.