Type definitions for the NVIC Registers. More...
Collaboration diagram for Nested Vectored Interrupt Controller (NVIC):
|
Classes | |
| struct | NVIC_Type |
| Structure type to access the Nested Vectored Interrupt Controller (NVIC). More... | |
Macros | |
| #define | NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) |
| #define | NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) |
| #define | NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) |
| #define | NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) |
| #define | NVIC_STIR_INTID_Pos 0 |
| #define | NVIC_STIR_INTID_Pos 0 |
| #define | NVIC_STIR_INTID_Pos 0 |
| #define | NVIC_STIR_INTID_Pos 0 |
Detailed Description
Type definitions for the NVIC Registers.
Macro Definition Documentation
| #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) |
STIR: INTLINESNUM Mask
Definition at line 335 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) |
STIR: INTLINESNUM Mask
Definition at line 335 of file core_sc300.h.
| #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) |
STIR: INTLINESNUM Mask
Definition at line 382 of file core_cm4.h.
| #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) |
STIR: INTLINESNUM Mask
Definition at line 397 of file core_cm7.h.
| #define NVIC_STIR_INTID_Pos 0 |
STIR: INTLINESNUM Position
Definition at line 334 of file core_sc300.h.
| #define NVIC_STIR_INTID_Pos 0 |
STIR: INTLINESNUM Position
Definition at line 334 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.
| #define NVIC_STIR_INTID_Pos 0 |
STIR: INTLINESNUM Position
Definition at line 381 of file core_cm4.h.
| #define NVIC_STIR_INTID_Pos 0 |
STIR: INTLINESNUM Position
Definition at line 396 of file core_cm7.h.