TIM. More...
#include <stm32f407xx.h>
Public Attributes | |
| __IO uint32_t | AF1 |
| __IO uint32_t | AF2 |
| __IO uint32_t | ARR |
| __IO uint32_t | BDTR |
| __IO uint32_t | CCER |
| __IO uint32_t | CCMR1 |
| __IO uint32_t | CCMR2 |
| __IO uint32_t | CCMR3 |
| __IO uint32_t | CCR1 |
| __IO uint32_t | CCR2 |
| __IO uint32_t | CCR3 |
| __IO uint32_t | CCR4 |
| __IO uint32_t | CCR5 |
| __IO uint32_t | CCR6 |
| __IO uint32_t | CNT |
| __IO uint32_t | CR1 |
| __IO uint32_t | CR2 |
| __IO uint32_t | DCR |
| __IO uint32_t | DIER |
| __IO uint32_t | DMAR |
| __IO uint32_t | EGR |
| __IO uint32_t | OR |
| __IO uint32_t | PSC |
| __IO uint32_t | RCR |
| uint32_t | RESERVED1 |
| __IO uint32_t | SMCR |
| __IO uint32_t | SR |
| __IO uint32_t | TISEL |
TIM.
Definition at line 729 of file stm32f407xx.h.
| __IO uint32_t TIM_TypeDef::AF1 |
TIM Alternate function option register 1, Address offset: 0x60
TIM alternate function option register 1, Address offset: 0x60
Definition at line 981 of file stm32f769xx.h.
| __IO uint32_t TIM_TypeDef::AF2 |
TIM Alternate function option register 2, Address offset: 0x64
TIM alternate function option register 2, Address offset: 0x64
Definition at line 982 of file stm32f769xx.h.
| __IO uint32_t TIM_TypeDef::ARR |
TIM auto-reload register, Address offset: 0x2C
Definition at line 742 of file stm32f407xx.h.
| __IO uint32_t TIM_TypeDef::BDTR |
TIM break and dead-time register, Address offset: 0x44
Definition at line 748 of file stm32f407xx.h.
| __IO uint32_t TIM_TypeDef::CCER |
TIM capture/compare enable register, Address offset: 0x20
Definition at line 739 of file stm32f407xx.h.
| __IO uint32_t TIM_TypeDef::CCMR1 |
TIM capture/compare mode register 1, Address offset: 0x18
Definition at line 737 of file stm32f407xx.h.
| __IO uint32_t TIM_TypeDef::CCMR2 |
TIM capture/compare mode register 2, Address offset: 0x1C
Definition at line 738 of file stm32f407xx.h.
| __IO uint32_t TIM_TypeDef::CCMR3 |
TIM capture/compare mode register 3, Address offset: 0x54
Definition at line 978 of file stm32f769xx.h.
| __IO uint32_t TIM_TypeDef::CCR1 |
TIM capture/compare register 1, Address offset: 0x34
Definition at line 744 of file stm32f407xx.h.
| __IO uint32_t TIM_TypeDef::CCR2 |
TIM capture/compare register 2, Address offset: 0x38
Definition at line 745 of file stm32f407xx.h.
| __IO uint32_t TIM_TypeDef::CCR3 |
TIM capture/compare register 3, Address offset: 0x3C
Definition at line 746 of file stm32f407xx.h.
| __IO uint32_t TIM_TypeDef::CCR4 |
TIM capture/compare register 4, Address offset: 0x40
Definition at line 747 of file stm32f407xx.h.
| __IO uint32_t TIM_TypeDef::CCR5 |
TIM capture/compare mode register5, Address offset: 0x58
TIM capture/compare register5, Address offset: 0x58
Definition at line 979 of file stm32f769xx.h.
| __IO uint32_t TIM_TypeDef::CCR6 |
TIM capture/compare mode register6, Address offset: 0x5C
TIM capture/compare register6, Address offset: 0x5C
Definition at line 980 of file stm32f769xx.h.
| __IO uint32_t TIM_TypeDef::CNT |
TIM counter register, Address offset: 0x24
Definition at line 740 of file stm32f407xx.h.
| __IO uint32_t TIM_TypeDef::CR1 |
TIM control register 1, Address offset: 0x00
Definition at line 731 of file stm32f407xx.h.
| __IO uint32_t TIM_TypeDef::CR2 |
TIM control register 2, Address offset: 0x04
Definition at line 732 of file stm32f407xx.h.
| __IO uint32_t TIM_TypeDef::DCR |
TIM DMA control register, Address offset: 0x48
Definition at line 749 of file stm32f407xx.h.
| __IO uint32_t TIM_TypeDef::DIER |
TIM DMA/interrupt enable register, Address offset: 0x0C
Definition at line 734 of file stm32f407xx.h.
| __IO uint32_t TIM_TypeDef::DMAR |
TIM DMA address for full transfer, Address offset: 0x4C
Definition at line 750 of file stm32f407xx.h.
| __IO uint32_t TIM_TypeDef::EGR |
TIM event generation register, Address offset: 0x14
Definition at line 736 of file stm32f407xx.h.
| __IO uint32_t TIM_TypeDef::OR |
TIM option register, Address offset: 0x50
Definition at line 751 of file stm32f407xx.h.
| __IO uint32_t TIM_TypeDef::PSC |
TIM prescaler, Address offset: 0x28
Definition at line 741 of file stm32f407xx.h.
| __IO uint32_t TIM_TypeDef::RCR |
TIM repetition counter register, Address offset: 0x30
Definition at line 743 of file stm32f407xx.h.
| uint32_t TIM_TypeDef::RESERVED1 |
Reserved, 0x50
Definition at line 1551 of file stm32h735xx.h.
| __IO uint32_t TIM_TypeDef::SMCR |
TIM slave mode control register, Address offset: 0x08
Definition at line 733 of file stm32f407xx.h.
| __IO uint32_t TIM_TypeDef::SR |
TIM status register, Address offset: 0x10
Definition at line 735 of file stm32f407xx.h.
| __IO uint32_t TIM_TypeDef::TISEL |
TIM Input Selection register, Address offset: 0x68
Definition at line 1557 of file stm32h735xx.h.