SD host Interface. More...

#include <stm32f769xx.h>

Public Attributes
__IO uint32_t	ACKTIME

__IO uint32_t	ARG

__IO uint32_t	CLKCR

__IO uint32_t	CMD

__I uint32_t	DCOUNT

__IO uint32_t	DCTRL

__IO uint32_t	DLEN

__IO uint32_t	DTIMER

__IO uint32_t	FIFO

__I uint32_t	FIFOCNT

__IO uint32_t	ICR

__IO uint32_t	IDMABASE0

__IO uint32_t	IDMABASE1

__IO uint32_t	IDMABSIZE

__IO uint32_t	IDMACTRL

__IO uint32_t	IPVR

__IO uint32_t	MASK

__IO uint32_t	POWER

uint32_t	RESERVED0 [2]

uint32_t	RESERVED1 [13]

uint32_t	RESERVED2 [222]

__I uint32_t	RESP1

__I uint32_t	RESP2

__I uint32_t	RESP3

__I uint32_t	RESP4

__I uint32_t	RESPCMD

__I uint32_t	STA

Detailed Description

SD host Interface.

Secure digital input/output Interface.

Definition at line 889 of file stm32f769xx.h.

Member Data Documentation

◆ ACKTIME

__IO uint32_t SDMMC_TypeDef::ACKTIME

SDMMC Acknowledgement timer register, Address offset: 0x40

Definition at line 1430 of file stm32h735xx.h.

◆ ARG

__IO uint32_t SDMMC_TypeDef::ARG

SDMMC argument register, Address offset: 0x08

Definition at line 893 of file stm32f769xx.h.

◆ CLKCR

__IO uint32_t SDMMC_TypeDef::CLKCR

SDMMClock control register, Address offset: 0x04

SDMMC clock control register, Address offset: 0x04

Definition at line 892 of file stm32f769xx.h.

◆ CMD

__IO uint32_t SDMMC_TypeDef::CMD

SDMMC command register, Address offset: 0x0C

Definition at line 894 of file stm32f769xx.h.

◆ DCOUNT

__I uint32_t SDMMC_TypeDef::DCOUNT

SDMMC data counter register, Address offset: 0x30

Definition at line 903 of file stm32f769xx.h.

◆ DCTRL

__IO uint32_t SDMMC_TypeDef::DCTRL

SDMMC data control register, Address offset: 0x2C

Definition at line 902 of file stm32f769xx.h.

◆ DLEN

__IO uint32_t SDMMC_TypeDef::DLEN

SDMMC data length register, Address offset: 0x28

Definition at line 901 of file stm32f769xx.h.

◆ DTIMER

__IO uint32_t SDMMC_TypeDef::DTIMER

SDMMC data timer register, Address offset: 0x24

Definition at line 900 of file stm32f769xx.h.

◆ FIFO

__IO uint32_t SDMMC_TypeDef::FIFO

SDMMC data FIFO register, Address offset: 0x80

Definition at line 910 of file stm32f769xx.h.

◆ FIFOCNT

__I uint32_t SDMMC_TypeDef::FIFOCNT

SDMMC FIFO counter register, Address offset: 0x48

Definition at line 908 of file stm32f769xx.h.

◆ ICR

__IO uint32_t SDMMC_TypeDef::ICR

SDMMC interrupt clear register, Address offset: 0x38

Definition at line 905 of file stm32f769xx.h.

◆ IDMABASE0

__IO uint32_t SDMMC_TypeDef::IDMABASE0

SDMMC DMA buffer 0 base address register, Address offset: 0x58

Definition at line 1434 of file stm32h735xx.h.

◆ IDMABASE1

__IO uint32_t SDMMC_TypeDef::IDMABASE1

SDMMC DMA buffer 1 base address register, Address offset: 0x5C

Definition at line 1435 of file stm32h735xx.h.

◆ IDMABSIZE

__IO uint32_t SDMMC_TypeDef::IDMABSIZE

SDMMC DMA buffer size register, Address offset: 0x54

Definition at line 1433 of file stm32h735xx.h.

◆ IDMACTRL

__IO uint32_t SDMMC_TypeDef::IDMACTRL

SDMMC DMA control register, Address offset: 0x50

Definition at line 1432 of file stm32h735xx.h.

◆ IPVR

__IO uint32_t SDMMC_TypeDef::IPVR

SDMMC data FIFO register, Address offset: 0x3FC

Definition at line 1439 of file stm32h735xx.h.

◆ MASK

__IO uint32_t SDMMC_TypeDef::MASK

SDMMC mask register, Address offset: 0x3C

Definition at line 906 of file stm32f769xx.h.

◆ POWER

__IO uint32_t SDMMC_TypeDef::POWER

SDMMC power control register, Address offset: 0x00

Definition at line 891 of file stm32f769xx.h.

◆ RESERVED0

uint32_t SDMMC_TypeDef::RESERVED0

Reserved, 0x40-0x44

Reserved, 0x44 - 0x4C - 0x4C

Definition at line 907 of file stm32f769xx.h.

◆ RESERVED1

uint32_t SDMMC_TypeDef::RESERVED1

Reserved, 0x4C-0x7C

Reserved, 0x60-0x7C

Definition at line 909 of file stm32f769xx.h.

◆ RESERVED2

uint32_t SDMMC_TypeDef::RESERVED2

Reserved, 0x84-0x3F8

Definition at line 1438 of file stm32h735xx.h.

◆ RESP1

__I uint32_t SDMMC_TypeDef::RESP1

SDMMC response 1 register, Address offset: 0x14

Definition at line 896 of file stm32f769xx.h.

◆ RESP2

__I uint32_t SDMMC_TypeDef::RESP2

SDMMC response 2 register, Address offset: 0x18

Definition at line 897 of file stm32f769xx.h.

◆ RESP3

__I uint32_t SDMMC_TypeDef::RESP3

SDMMC response 3 register, Address offset: 0x1C

Definition at line 898 of file stm32f769xx.h.

◆ RESP4

__I uint32_t SDMMC_TypeDef::RESP4

SDMMC response 4 register, Address offset: 0x20

Definition at line 899 of file stm32f769xx.h.

◆ RESPCMD

__I uint32_t SDMMC_TypeDef::RESPCMD

SDMMC command response register, Address offset: 0x10

Definition at line 895 of file stm32f769xx.h.

◆ STA

__I uint32_t SDMMC_TypeDef::STA

SDMMC status register, Address offset: 0x34

Definition at line 904 of file stm32f769xx.h.

The documentation for this struct was generated from the following files:

Public Attributes