Power Control. More...

#include <stm32f407xx.h>

Public Attributes
__IO uint32_t	CPU2CR

__IO uint32_t	CPUCR

__IO uint32_t	CR

__IO uint32_t	CR1

__IO uint32_t	CR2

__IO uint32_t	CR3

__IO uint32_t	CSR

__IO uint32_t	CSR1

__IO uint32_t	CSR2

__IO uint32_t	D3CR

uint32_t	RESERVED0

uint32_t	RESERVED1

__IO uint32_t	WKUPCR

__IO uint32_t	WKUPEPR

__IO uint32_t	WKUPFR

Detailed Description

Power Control.

Definition at line 587 of file stm32f407xx.h.

Member Data Documentation

◆ CPU2CR

__IO uint32_t PWR_TypeDef::CPU2CR

PWR CPU2 control register, Address offset: 0x14

Definition at line 1337 of file stm32h747xx.h.

◆ CPUCR

__IO uint32_t PWR_TypeDef::CPUCR

PWR CPU control register, Address offset: 0x10

Definition at line 1224 of file stm32h735xx.h.

◆ CR

__IO uint32_t PWR_TypeDef::CR

PWR power control register, Address offset: 0x00

Definition at line 589 of file stm32f407xx.h.

◆ CR1

__IO uint32_t PWR_TypeDef::CR1

PWR power control register 1, Address offset: 0x00

Definition at line 739 of file stm32f769xx.h.

◆ CR2

__IO uint32_t PWR_TypeDef::CR2

PWR power control register 2, Address offset: 0x08

Definition at line 741 of file stm32f769xx.h.

◆ CR3

__IO uint32_t PWR_TypeDef::CR3

PWR power control register 3, Address offset: 0x0C

Definition at line 1223 of file stm32h735xx.h.

◆ CSR

__IO uint32_t PWR_TypeDef::CSR

PWR power control/status register, Address offset: 0x04

Definition at line 590 of file stm32f407xx.h.

◆ CSR1

__IO uint32_t PWR_TypeDef::CSR1

PWR power control/status register 2, Address offset: 0x04

PWR power control status register 1, Address offset: 0x04

Definition at line 740 of file stm32f769xx.h.

◆ CSR2

__IO uint32_t PWR_TypeDef::CSR2

PWR power control/status register 2, Address offset: 0x0C

Definition at line 742 of file stm32f769xx.h.

◆ D3CR

__IO uint32_t PWR_TypeDef::D3CR

PWR D3 domain control register, Address offset: 0x18

Definition at line 1226 of file stm32h735xx.h.

◆ RESERVED0

uint32_t PWR_TypeDef::RESERVED0

Reserved, Address offset: 0x14

Definition at line 1225 of file stm32h735xx.h.

◆ RESERVED1

uint32_t PWR_TypeDef::RESERVED1

Reserved, Address offset: 0x1C

Definition at line 1227 of file stm32h735xx.h.

◆ WKUPCR

__IO uint32_t PWR_TypeDef::WKUPCR

PWR wakeup clear register, Address offset: 0x20

Definition at line 1228 of file stm32h735xx.h.

◆ WKUPEPR

__IO uint32_t PWR_TypeDef::WKUPEPR

PWR wakeup enable and polarity register, Address offset: 0x28

Definition at line 1230 of file stm32h735xx.h.

◆ WKUPFR

__IO uint32_t PWR_TypeDef::WKUPFR

PWR wakeup flag register, Address offset: 0x24

Definition at line 1229 of file stm32h735xx.h.

The documentation for this struct was generated from the following files:

Public Attributes