DMA2D Controller. More...
#include <stm32f469xx.h>
Public Attributes | |
| __IO uint32_t | AMTCR |
| __IO uint32_t | BGCLUT [256] |
| __IO uint32_t | BGCMAR |
| __IO uint32_t | BGCOLR |
| __IO uint32_t | BGMAR |
| __IO uint32_t | BGOR |
| __IO uint32_t | BGPFCCR |
| __IO uint32_t | CR |
| __IO uint32_t | FGCLUT [256] |
| __IO uint32_t | FGCMAR |
| __IO uint32_t | FGCOLR |
| __IO uint32_t | FGMAR |
| __IO uint32_t | FGOR |
| __IO uint32_t | FGPFCCR |
| __IO uint32_t | IFCR |
| __IO uint32_t | ISR |
| __IO uint32_t | LWR |
| __IO uint32_t | NLR |
| __IO uint32_t | OCOLR |
| __IO uint32_t | OMAR |
| __IO uint32_t | OOR |
| __IO uint32_t | OPFCCR |
| uint32_t | RESERVED [236] |
DMA2D Controller.
Definition at line 377 of file stm32f469xx.h.
| __IO uint32_t DMA2D_TypeDef::AMTCR |
DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C
Definition at line 398 of file stm32f469xx.h.
| __IO uint32_t DMA2D_TypeDef::BGCLUT |
DMA2D Background CLUT, Address offset:800-BFF
Definition at line 401 of file stm32f469xx.h.
| __IO uint32_t DMA2D_TypeDef::BGCMAR |
DMA2D Background CLUT Memory Address Register, Address offset: 0x30
Definition at line 391 of file stm32f469xx.h.
| __IO uint32_t DMA2D_TypeDef::BGCOLR |
DMA2D Background Color Register, Address offset: 0x28
Definition at line 389 of file stm32f469xx.h.
| __IO uint32_t DMA2D_TypeDef::BGMAR |
DMA2D Background Memory Address Register, Address offset: 0x14
Definition at line 384 of file stm32f469xx.h.
| __IO uint32_t DMA2D_TypeDef::BGOR |
DMA2D Background Offset Register, Address offset: 0x18
Definition at line 385 of file stm32f469xx.h.
| __IO uint32_t DMA2D_TypeDef::BGPFCCR |
DMA2D Background PFC Control Register, Address offset: 0x24
Definition at line 388 of file stm32f469xx.h.
| __IO uint32_t DMA2D_TypeDef::CR |
DMA2D Control Register, Address offset: 0x00
Definition at line 379 of file stm32f469xx.h.
| __IO uint32_t DMA2D_TypeDef::FGCLUT |
DMA2D Foreground CLUT, Address offset:400-7FF
Definition at line 400 of file stm32f469xx.h.
| __IO uint32_t DMA2D_TypeDef::FGCMAR |
DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C
Definition at line 390 of file stm32f469xx.h.
| __IO uint32_t DMA2D_TypeDef::FGCOLR |
DMA2D Foreground Color Register, Address offset: 0x20
Definition at line 387 of file stm32f469xx.h.
| __IO uint32_t DMA2D_TypeDef::FGMAR |
DMA2D Foreground Memory Address Register, Address offset: 0x0C
Definition at line 382 of file stm32f469xx.h.
| __IO uint32_t DMA2D_TypeDef::FGOR |
DMA2D Foreground Offset Register, Address offset: 0x10
Definition at line 383 of file stm32f469xx.h.
| __IO uint32_t DMA2D_TypeDef::FGPFCCR |
DMA2D Foreground PFC Control Register, Address offset: 0x1C
Definition at line 386 of file stm32f469xx.h.
| __IO uint32_t DMA2D_TypeDef::IFCR |
DMA2D Interrupt Flag Clear Register, Address offset: 0x08
Definition at line 381 of file stm32f469xx.h.
| __IO uint32_t DMA2D_TypeDef::ISR |
DMA2D Interrupt Status Register, Address offset: 0x04
Definition at line 380 of file stm32f469xx.h.
| __IO uint32_t DMA2D_TypeDef::LWR |
DMA2D Line Watermark Register, Address offset: 0x48
Definition at line 397 of file stm32f469xx.h.
| __IO uint32_t DMA2D_TypeDef::NLR |
DMA2D Number of Line Register, Address offset: 0x44
Definition at line 396 of file stm32f469xx.h.
| __IO uint32_t DMA2D_TypeDef::OCOLR |
DMA2D Output Color Register, Address offset: 0x38
Definition at line 393 of file stm32f469xx.h.
| __IO uint32_t DMA2D_TypeDef::OMAR |
DMA2D Output Memory Address Register, Address offset: 0x3C
Definition at line 394 of file stm32f469xx.h.
| __IO uint32_t DMA2D_TypeDef::OOR |
DMA2D Output Offset Register, Address offset: 0x40
Definition at line 395 of file stm32f469xx.h.
| __IO uint32_t DMA2D_TypeDef::OPFCCR |
DMA2D Output PFC Control Register, Address offset: 0x34
Definition at line 392 of file stm32f469xx.h.
| uint32_t DMA2D_TypeDef::RESERVED |
Reserved, 0x50-0x3FF
Definition at line 399 of file stm32f469xx.h.