stm32f7xx_hal_tim.h
Go to the documentation of this file.
1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32F7xx_HAL_TIM_H
22 #define STM32F7xx_HAL_TIM_H
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f7xx_hal_def.h"
30 
39 /* Exported types ------------------------------------------------------------*/
47 typedef struct
48 {
49  uint32_t Prescaler;
52  uint32_t CounterMode;
55  uint32_t Period;
59  uint32_t ClockDivision;
62  uint32_t RepetitionCounter;
71  uint32_t AutoReloadPreload;
73 } TIM_Base_InitTypeDef;
74 
78 typedef struct
79 {
80  uint32_t OCMode;
83  uint32_t Pulse;
86  uint32_t OCPolarity;
89  uint32_t OCNPolarity;
93  uint32_t OCFastMode;
98  uint32_t OCIdleState;
102  uint32_t OCNIdleState;
105 } TIM_OC_InitTypeDef;
106 
110 typedef struct
111 {
112  uint32_t OCMode;
115  uint32_t Pulse;
118  uint32_t OCPolarity;
121  uint32_t OCNPolarity;
125  uint32_t OCIdleState;
129  uint32_t OCNIdleState;
133  uint32_t ICPolarity;
136  uint32_t ICSelection;
139  uint32_t ICFilter;
141 } TIM_OnePulse_InitTypeDef;
142 
146 typedef struct
147 {
148  uint32_t ICPolarity;
151  uint32_t ICSelection;
154  uint32_t ICPrescaler;
157  uint32_t ICFilter;
159 } TIM_IC_InitTypeDef;
160 
164 typedef struct
165 {
166  uint32_t EncoderMode;
169  uint32_t IC1Polarity;
172  uint32_t IC1Selection;
175  uint32_t IC1Prescaler;
178  uint32_t IC1Filter;
181  uint32_t IC2Polarity;
184  uint32_t IC2Selection;
187  uint32_t IC2Prescaler;
190  uint32_t IC2Filter;
192 } TIM_Encoder_InitTypeDef;
193 
197 typedef struct
198 {
199  uint32_t ClockSource;
201  uint32_t ClockPolarity;
203  uint32_t ClockPrescaler;
205  uint32_t ClockFilter;
207 } TIM_ClockConfigTypeDef;
208 
212 typedef struct
213 {
214  uint32_t ClearInputState;
216  uint32_t ClearInputSource;
218  uint32_t ClearInputPolarity;
220  uint32_t ClearInputPrescaler;
222  uint32_t ClearInputFilter;
224 } TIM_ClearInputConfigTypeDef;
225 
231 typedef struct
232 {
233  uint32_t MasterOutputTrigger;
235  uint32_t MasterOutputTrigger2;
237  uint32_t MasterSlaveMode;
244 } TIM_MasterConfigTypeDef;
245 
249 typedef struct
250 {
251  uint32_t SlaveMode;
253  uint32_t InputTrigger;
255  uint32_t TriggerPolarity;
257  uint32_t TriggerPrescaler;
259  uint32_t TriggerFilter;
262 } TIM_SlaveConfigTypeDef;
263 
269 typedef struct
270 {
271  uint32_t OffStateRunMode;
273  uint32_t OffStateIDLEMode;
275  uint32_t LockLevel;
277  uint32_t DeadTime;
279  uint32_t BreakState;
281  uint32_t BreakPolarity;
283  uint32_t BreakFilter;
285  uint32_t Break2State;
287  uint32_t Break2Polarity;
289  uint32_t Break2Filter;
291  uint32_t AutomaticOutput;
293 } TIM_BreakDeadTimeConfigTypeDef;
294 
298 typedef enum
299 {
300  HAL_TIM_STATE_RESET = 0x00U,
301  HAL_TIM_STATE_READY = 0x01U,
302  HAL_TIM_STATE_BUSY = 0x02U,
303  HAL_TIM_STATE_TIMEOUT = 0x03U,
304  HAL_TIM_STATE_ERROR = 0x04U
305 } HAL_TIM_StateTypeDef;
306 
310 typedef enum
311 {
312  HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
313  HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
314  HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
315  HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
316  HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U,
317  HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U,
318  HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U
319 } HAL_TIM_ActiveChannel;
320 
324 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
325 typedef struct __TIM_HandleTypeDef
326 #else
327 typedef struct
328 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
329 {
330  TIM_TypeDef *Instance;
331  TIM_Base_InitTypeDef Init;
332  HAL_TIM_ActiveChannel Channel;
333  DMA_HandleTypeDef *hdma[7];
335  HAL_LockTypeDef Lock;
336  __IO HAL_TIM_StateTypeDef State;
338 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
339  void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
340  void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
341  void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
342  void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
343  void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
344  void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
345  void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
346  void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
347  void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
348  void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
349  void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
350  void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
351  void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
352  void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
353  void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);
354  void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);
355  void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);
356  void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);
357  void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);
358  void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);
359  void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);
360  void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);
361  void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);
362  void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);
363  void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim);
364  void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);
365  void (* BreakCallback)(struct __TIM_HandleTypeDef *htim);
366  void (* Break2Callback)(struct __TIM_HandleTypeDef *htim);
367 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
368 } TIM_HandleTypeDef;
369 
370 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
371 
374 typedef enum
375 {
376  HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U
377  ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U
378  ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U
379  ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U
380  ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U
381  ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U
382  ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U
383  ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U
384  ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U
385  ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U
386  ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU
387  ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU
388  ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU
389  ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU
390  ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU
391  ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU
392  ,HAL_TIM_TRIGGER_CB_ID = 0x10U
393  ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U
395  ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U
396  ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U
397  ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U
398  ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U
399  ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U
400  ,HAL_TIM_ERROR_CB_ID = 0x17U
401  ,HAL_TIM_COMMUTATION_CB_ID = 0x18U
402  ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U
403  ,HAL_TIM_BREAK_CB_ID = 0x1AU
404  ,HAL_TIM_BREAK2_CB_ID = 0x1BU
405 } HAL_TIM_CallbackIDTypeDef;
406 
410 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);
412 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
413 
417 /* End of exported types -----------------------------------------------------*/
418 
419 /* Exported constants --------------------------------------------------------*/
427 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U
428 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U
436 #define TIM_DMABASE_CR1 0x00000000U
437 #define TIM_DMABASE_CR2 0x00000001U
438 #define TIM_DMABASE_SMCR 0x00000002U
439 #define TIM_DMABASE_DIER 0x00000003U
440 #define TIM_DMABASE_SR 0x00000004U
441 #define TIM_DMABASE_EGR 0x00000005U
442 #define TIM_DMABASE_CCMR1 0x00000006U
443 #define TIM_DMABASE_CCMR2 0x00000007U
444 #define TIM_DMABASE_CCER 0x00000008U
445 #define TIM_DMABASE_CNT 0x00000009U
446 #define TIM_DMABASE_PSC 0x0000000AU
447 #define TIM_DMABASE_ARR 0x0000000BU
448 #define TIM_DMABASE_RCR 0x0000000CU
449 #define TIM_DMABASE_CCR1 0x0000000DU
450 #define TIM_DMABASE_CCR2 0x0000000EU
451 #define TIM_DMABASE_CCR3 0x0000000FU
452 #define TIM_DMABASE_CCR4 0x00000010U
453 #define TIM_DMABASE_BDTR 0x00000011U
454 #define TIM_DMABASE_DCR 0x00000012U
455 #define TIM_DMABASE_DMAR 0x00000013U
456 #define TIM_DMABASE_OR 0x00000014U
457 #define TIM_DMABASE_CCMR3 0x00000015U
458 #define TIM_DMABASE_CCR5 0x00000016U
459 #define TIM_DMABASE_CCR6 0x00000017U
460 #if defined(TIM_BREAK_INPUT_SUPPORT)
461 #define TIM_DMABASE_AF1 0x00000018U
462 #define TIM_DMABASE_AF2 0x00000019U
463 #endif /* TIM_BREAK_INPUT_SUPPORT */
464 
471 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
472 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
473 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
474 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
475 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
476 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG
477 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
478 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
479 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G
487 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U
488 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P
489 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)
497 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP
498 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U
506 #define TIM_ETRPRESCALER_DIV1 0x00000000U
507 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0
508 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1
509 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS
517 #define TIM_COUNTERMODE_UP 0x00000000U
518 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
519 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
520 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
521 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
529 #define TIM_UIFREMAP_DISABLE 0x00000000U
530 #define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP
538 #define TIM_CLOCKDIVISION_DIV1 0x00000000U
539 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
540 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1
548 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U
549 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E
557 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U
558 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE
567 #define TIM_OCFAST_DISABLE 0x00000000U
568 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE
576 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U
577 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE
585 #define TIM_OCPOLARITY_HIGH 0x00000000U
586 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P
594 #define TIM_OCNPOLARITY_HIGH 0x00000000U
595 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP
603 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1
604 #define TIM_OCIDLESTATE_RESET 0x00000000U
612 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N
613 #define TIM_OCNIDLESTATE_RESET 0x00000000U
621 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
622 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
623 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
631 #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
632 #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
640 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0
642 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1
644 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S
652 #define TIM_ICPSC_DIV1 0x00000000U
653 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0
654 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1
655 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC
663 #define TIM_OPMODE_SINGLE TIM_CR1_OPM
664 #define TIM_OPMODE_REPETITIVE 0x00000000U
672 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0
673 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1
674 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
682 #define TIM_IT_UPDATE TIM_DIER_UIE
683 #define TIM_IT_CC1 TIM_DIER_CC1IE
684 #define TIM_IT_CC2 TIM_DIER_CC2IE
685 #define TIM_IT_CC3 TIM_DIER_CC3IE
686 #define TIM_IT_CC4 TIM_DIER_CC4IE
687 #define TIM_IT_COM TIM_DIER_COMIE
688 #define TIM_IT_TRIGGER TIM_DIER_TIE
689 #define TIM_IT_BREAK TIM_DIER_BIE
697 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS
698 #define TIM_COMMUTATION_SOFTWARE 0x00000000U
706 #define TIM_DMA_UPDATE TIM_DIER_UDE
707 #define TIM_DMA_CC1 TIM_DIER_CC1DE
708 #define TIM_DMA_CC2 TIM_DIER_CC2DE
709 #define TIM_DMA_CC3 TIM_DIER_CC3DE
710 #define TIM_DMA_CC4 TIM_DIER_CC4DE
711 #define TIM_DMA_COM TIM_DIER_COMDE
712 #define TIM_DMA_TRIGGER TIM_DIER_TDE
720 #define TIM_FLAG_UPDATE TIM_SR_UIF
721 #define TIM_FLAG_CC1 TIM_SR_CC1IF
722 #define TIM_FLAG_CC2 TIM_SR_CC2IF
723 #define TIM_FLAG_CC3 TIM_SR_CC3IF
724 #define TIM_FLAG_CC4 TIM_SR_CC4IF
725 #define TIM_FLAG_CC5 TIM_SR_CC5IF
726 #define TIM_FLAG_CC6 TIM_SR_CC6IF
727 #define TIM_FLAG_COM TIM_SR_COMIF
728 #define TIM_FLAG_TRIGGER TIM_SR_TIF
729 #define TIM_FLAG_BREAK TIM_SR_BIF
730 #define TIM_FLAG_BREAK2 TIM_SR_B2IF
731 #define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF
732 #define TIM_FLAG_CC1OF TIM_SR_CC1OF
733 #define TIM_FLAG_CC2OF TIM_SR_CC2OF
734 #define TIM_FLAG_CC3OF TIM_SR_CC3OF
735 #define TIM_FLAG_CC4OF TIM_SR_CC4OF
743 #define TIM_CHANNEL_1 0x00000000U
744 #define TIM_CHANNEL_2 0x00000004U
745 #define TIM_CHANNEL_3 0x00000008U
746 #define TIM_CHANNEL_4 0x0000000CU
747 #define TIM_CHANNEL_5 0x00000010U
748 #define TIM_CHANNEL_6 0x00000014U
749 #define TIM_CHANNEL_ALL 0x0000003CU
757 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1
758 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0
759 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0
760 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1
761 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2
762 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3
763 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED
764 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1
765 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2
766 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF
774 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
775 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
776 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
777 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
778 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
786 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
787 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
788 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
789 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
797 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
798 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
806 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
807 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
808 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
809 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
817 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR
818 #define TIM_OSSR_DISABLE 0x00000000U
826 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI
827 #define TIM_OSSI_DISABLE 0x00000000U
834 #define TIM_LOCKLEVEL_OFF 0x00000000U
835 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
836 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
837 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK
845 #define TIM_BREAK_ENABLE TIM_BDTR_BKE
846 #define TIM_BREAK_DISABLE 0x00000000U
854 #define TIM_BREAKPOLARITY_LOW 0x00000000U
855 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP
863 #define TIM_BREAK2_DISABLE 0x00000000U
864 #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E
872 #define TIM_BREAK2POLARITY_LOW 0x00000000U
873 #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P
881 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
882 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE
891 #define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
892 #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
893 #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
894 #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
895 
902 #define TIM_TRGO_RESET 0x00000000U
903 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0
904 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1
905 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
906 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2
907 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
908 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
909 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
917 #define TIM_TRGO2_RESET 0x00000000U
918 #define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0
919 #define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1
920 #define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
921 #define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2
922 #define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
923 #define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)
924 #define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
925 #define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3
926 #define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)
927 #define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)
928 #define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
929 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)
930 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
931 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)
932 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
940 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM
941 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U
949 #define TIM_SLAVEMODE_DISABLE 0x00000000U
950 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
951 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
952 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
953 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
954 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3
962 #define TIM_OCMODE_TIMING 0x00000000U
963 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
964 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
965 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
966 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
967 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
968 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
969 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
970 #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3
971 #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
972 #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
973 #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
974 #define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
975 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M
983 #define TIM_TS_ITR0 0x00000000U
984 #define TIM_TS_ITR1 TIM_SMCR_TS_0
985 #define TIM_TS_ITR2 TIM_SMCR_TS_1
986 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
987 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2
988 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
989 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
990 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
991 #define TIM_TS_NONE 0x0000FFFFU
999 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
1000 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
1001 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
1002 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
1003 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
1011 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
1012 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
1013 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
1014 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
1022 #define TIM_TI1SELECTION_CH1 0x00000000U
1023 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S
1031 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
1032 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
1033 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
1034 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
1035 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
1036 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
1037 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
1038 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
1039 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
1040 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
1041 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
1042 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
1043 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
1044 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
1045 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
1046 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
1047 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
1048 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
1056 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000)
1057 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001)
1058 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002)
1059 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003)
1060 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004)
1061 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005)
1062 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006)
1070 #define TIM_CCx_ENABLE 0x00000001U
1071 #define TIM_CCx_DISABLE 0x00000000U
1072 #define TIM_CCxN_ENABLE 0x00000004U
1073 #define TIM_CCxN_DISABLE 0x00000000U
1081 #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL
1082 #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL
1083 #define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL
1084 #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL
1092 /* End of exported constants -------------------------------------------------*/
1093 
1094 /* Exported macros -----------------------------------------------------------*/
1103 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1104 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
1105  (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
1106  (__HANDLE__)->Base_MspInitCallback = NULL; \
1107  (__HANDLE__)->Base_MspDeInitCallback = NULL; \
1108  (__HANDLE__)->IC_MspInitCallback = NULL; \
1109  (__HANDLE__)->IC_MspDeInitCallback = NULL; \
1110  (__HANDLE__)->OC_MspInitCallback = NULL; \
1111  (__HANDLE__)->OC_MspDeInitCallback = NULL; \
1112  (__HANDLE__)->PWM_MspInitCallback = NULL; \
1113  (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
1114  (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
1115  (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
1116  (__HANDLE__)->Encoder_MspInitCallback = NULL; \
1117  (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
1118  (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
1119  (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
1120  } while(0)
1121 #else
1122 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
1123 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1124 
1130 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
1131 
1137 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
1138 
1144 #define __HAL_TIM_DISABLE(__HANDLE__) \
1145  do { \
1146  if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1147  { \
1148  if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1149  { \
1150  (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
1151  } \
1152  } \
1153  } while(0)
1154 
1161 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
1162  do { \
1163  if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1164  { \
1165  if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1166  { \
1167  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
1168  } \
1169  } \
1170  } while(0)
1171 
1178 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
1179 
1194 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
1195 
1210 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
1211 
1225 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
1226 
1240 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
1241 
1264 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
1265 
1288 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
1289 
1305 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
1306  == (__INTERRUPT__)) ? SET : RESET)
1307 
1322 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
1323 
1331 #define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
1332 
1339 #define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
1340 
1347 #define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
1348 
1356 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
1357 
1364 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
1365 
1374 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
1375 
1381 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
1382 
1389 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
1390  do{ \
1391  (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
1392  (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
1393  } while(0)
1394 
1400 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
1401 
1412 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
1413  do{ \
1414  (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
1415  (__HANDLE__)->Instance->CR1 |= (__CKD__); \
1416  (__HANDLE__)->Init.ClockDivision = (__CKD__); \
1417  } while(0)
1418 
1427 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1428 
1446 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
1447  do{ \
1448  TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
1449  TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1450  } while(0)
1451 
1467 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
1468  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1469  ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
1470  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1471  (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
1472 
1487 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
1488  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
1489  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
1490  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
1491  ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
1492  ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
1493  ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
1494 
1508 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
1509  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
1510  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
1511  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
1512  ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
1513  ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
1514  ((__HANDLE__)->Instance->CCR6))
1515 
1529 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
1530  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
1531  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
1532  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
1533  ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
1534  ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
1535  ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
1536 
1550 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
1551  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
1552  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
1553  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
1554  ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
1555  ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
1556  ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
1557 
1575 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
1576  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
1577  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
1578  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
1579  ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
1580  ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
1581  ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
1582 
1600 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
1601  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
1602  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
1603  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
1604  ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
1605  ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
1606  ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
1607 
1616 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
1617 
1629 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
1630 
1646 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1647  do{ \
1648  TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
1649  TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
1650  }while(0)
1651 
1655 /* End of exported macros ----------------------------------------------------*/
1656 
1657 /* Private constants ---------------------------------------------------------*/
1661 /* The counter of a timer instance is disabled only if all the CCx and CCxN
1662  channels have been disabled */
1663 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
1664 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
1665 
1668 /* End of private constants --------------------------------------------------*/
1669 
1670 /* Private macros ------------------------------------------------------------*/
1674 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \
1675  ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
1676 
1677 #if defined(TIM_AF1_BKINE)&&defined(TIM_AF2_BKINE)
1678 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
1679  ((__BASE__) == TIM_DMABASE_CR2) || \
1680  ((__BASE__) == TIM_DMABASE_SMCR) || \
1681  ((__BASE__) == TIM_DMABASE_DIER) || \
1682  ((__BASE__) == TIM_DMABASE_SR) || \
1683  ((__BASE__) == TIM_DMABASE_EGR) || \
1684  ((__BASE__) == TIM_DMABASE_CCMR1) || \
1685  ((__BASE__) == TIM_DMABASE_CCMR2) || \
1686  ((__BASE__) == TIM_DMABASE_CCER) || \
1687  ((__BASE__) == TIM_DMABASE_CNT) || \
1688  ((__BASE__) == TIM_DMABASE_PSC) || \
1689  ((__BASE__) == TIM_DMABASE_ARR) || \
1690  ((__BASE__) == TIM_DMABASE_RCR) || \
1691  ((__BASE__) == TIM_DMABASE_CCR1) || \
1692  ((__BASE__) == TIM_DMABASE_CCR2) || \
1693  ((__BASE__) == TIM_DMABASE_CCR3) || \
1694  ((__BASE__) == TIM_DMABASE_CCR4) || \
1695  ((__BASE__) == TIM_DMABASE_BDTR) || \
1696  ((__BASE__) == TIM_DMABASE_OR) || \
1697  ((__BASE__) == TIM_DMABASE_CCMR3) || \
1698  ((__BASE__) == TIM_DMABASE_CCR5) || \
1699  ((__BASE__) == TIM_DMABASE_CCR6) || \
1700  ((__BASE__) == TIM_DMABASE_AF1) || \
1701  ((__BASE__) == TIM_DMABASE_AF2))
1702 #else
1703 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
1704  ((__BASE__) == TIM_DMABASE_CR2) || \
1705  ((__BASE__) == TIM_DMABASE_SMCR) || \
1706  ((__BASE__) == TIM_DMABASE_DIER) || \
1707  ((__BASE__) == TIM_DMABASE_SR) || \
1708  ((__BASE__) == TIM_DMABASE_EGR) || \
1709  ((__BASE__) == TIM_DMABASE_CCMR1) || \
1710  ((__BASE__) == TIM_DMABASE_CCMR2) || \
1711  ((__BASE__) == TIM_DMABASE_CCER) || \
1712  ((__BASE__) == TIM_DMABASE_CNT) || \
1713  ((__BASE__) == TIM_DMABASE_PSC) || \
1714  ((__BASE__) == TIM_DMABASE_ARR) || \
1715  ((__BASE__) == TIM_DMABASE_RCR) || \
1716  ((__BASE__) == TIM_DMABASE_CCR1) || \
1717  ((__BASE__) == TIM_DMABASE_CCR2) || \
1718  ((__BASE__) == TIM_DMABASE_CCR3) || \
1719  ((__BASE__) == TIM_DMABASE_CCR4) || \
1720  ((__BASE__) == TIM_DMABASE_BDTR) || \
1721  ((__BASE__) == TIM_DMABASE_OR) || \
1722  ((__BASE__) == TIM_DMABASE_CCMR3) || \
1723  ((__BASE__) == TIM_DMABASE_CCR5) || \
1724  ((__BASE__) == TIM_DMABASE_CCR6))
1725 #endif /* TIM_AF1_BKINE && TIM_AF1_BKINE */
1726 
1727 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1728 
1729 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
1730  ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
1731  ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
1732  ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
1733  ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
1734 
1735 #define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
1736  ((__MODE__) == TIM_UIFREMAP_ENALE))
1737 
1738 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
1739  ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
1740  ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
1741 
1742 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
1743  ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
1744 
1745 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
1746  ((__STATE__) == TIM_OCFAST_ENABLE))
1747 
1748 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
1749  ((__POLARITY__) == TIM_OCPOLARITY_LOW))
1750 
1751 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
1752  ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
1753 
1754 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
1755  ((__STATE__) == TIM_OCIDLESTATE_RESET))
1756 
1757 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
1758  ((__STATE__) == TIM_OCNIDLESTATE_RESET))
1759 
1760 #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
1761  ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
1762 
1763 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
1764  ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
1765  ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
1766 
1767 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
1768  ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
1769  ((__SELECTION__) == TIM_ICSELECTION_TRC))
1770 
1771 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
1772  ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
1773  ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
1774  ((__PRESCALER__) == TIM_ICPSC_DIV8))
1775 
1776 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
1777  ((__MODE__) == TIM_OPMODE_REPETITIVE))
1778 
1779 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
1780  ((__MODE__) == TIM_ENCODERMODE_TI2) || \
1781  ((__MODE__) == TIM_ENCODERMODE_TI12))
1782 
1783 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1784 
1785 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1786  ((__CHANNEL__) == TIM_CHANNEL_2) || \
1787  ((__CHANNEL__) == TIM_CHANNEL_3) || \
1788  ((__CHANNEL__) == TIM_CHANNEL_4) || \
1789  ((__CHANNEL__) == TIM_CHANNEL_5) || \
1790  ((__CHANNEL__) == TIM_CHANNEL_6) || \
1791  ((__CHANNEL__) == TIM_CHANNEL_ALL))
1792 
1793 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1794  ((__CHANNEL__) == TIM_CHANNEL_2))
1795 
1796 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1797  ((__CHANNEL__) == TIM_CHANNEL_2) || \
1798  ((__CHANNEL__) == TIM_CHANNEL_3))
1799 
1800 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
1801  ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
1802  ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
1803  ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
1804  ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
1805  ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
1806  ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
1807  ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
1808  ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
1809  ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
1810 
1811 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
1812  ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
1813  ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
1814  ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
1815  ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
1816 
1817 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
1818  ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
1819  ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
1820  ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
1821 
1822 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1823 
1824 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
1825  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
1826 
1827 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
1828  ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
1829  ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
1830  ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
1831 
1832 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1833 
1834 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
1835  ((__STATE__) == TIM_OSSR_DISABLE))
1836 
1837 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
1838  ((__STATE__) == TIM_OSSI_DISABLE))
1839 
1840 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
1841  ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
1842  ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
1843  ((__LEVEL__) == TIM_LOCKLEVEL_3))
1844 
1845 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
1846 
1847 
1848 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
1849  ((__STATE__) == TIM_BREAK_DISABLE))
1850 
1851 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
1852  ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
1853 
1854 #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \
1855  ((__STATE__) == TIM_BREAK2_DISABLE))
1856 
1857 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
1858  ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
1859 
1860 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
1861  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
1862 
1863 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
1864 
1865 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
1866  ((__SOURCE__) == TIM_TRGO_ENABLE) || \
1867  ((__SOURCE__) == TIM_TRGO_UPDATE) || \
1868  ((__SOURCE__) == TIM_TRGO_OC1) || \
1869  ((__SOURCE__) == TIM_TRGO_OC1REF) || \
1870  ((__SOURCE__) == TIM_TRGO_OC2REF) || \
1871  ((__SOURCE__) == TIM_TRGO_OC3REF) || \
1872  ((__SOURCE__) == TIM_TRGO_OC4REF))
1873 
1874 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \
1875  ((__SOURCE__) == TIM_TRGO2_ENABLE) || \
1876  ((__SOURCE__) == TIM_TRGO2_UPDATE) || \
1877  ((__SOURCE__) == TIM_TRGO2_OC1) || \
1878  ((__SOURCE__) == TIM_TRGO2_OC1REF) || \
1879  ((__SOURCE__) == TIM_TRGO2_OC2REF) || \
1880  ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
1881  ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
1882  ((__SOURCE__) == TIM_TRGO2_OC4REF) || \
1883  ((__SOURCE__) == TIM_TRGO2_OC5REF) || \
1884  ((__SOURCE__) == TIM_TRGO2_OC6REF) || \
1885  ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
1886  ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
1887  ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
1888  ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
1889  ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
1890  ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
1891 
1892 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
1893  ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
1894 
1895 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
1896  ((__MODE__) == TIM_SLAVEMODE_RESET) || \
1897  ((__MODE__) == TIM_SLAVEMODE_GATED) || \
1898  ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
1899  ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
1900  ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
1901 
1902 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
1903  ((__MODE__) == TIM_OCMODE_PWM2) || \
1904  ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
1905  ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
1906  ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
1907  ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
1908 
1909 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
1910  ((__MODE__) == TIM_OCMODE_ACTIVE) || \
1911  ((__MODE__) == TIM_OCMODE_INACTIVE) || \
1912  ((__MODE__) == TIM_OCMODE_TOGGLE) || \
1913  ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
1914  ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \
1915  ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
1916  ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
1917 
1918 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
1919  ((__SELECTION__) == TIM_TS_ITR1) || \
1920  ((__SELECTION__) == TIM_TS_ITR2) || \
1921  ((__SELECTION__) == TIM_TS_ITR3) || \
1922  ((__SELECTION__) == TIM_TS_TI1F_ED) || \
1923  ((__SELECTION__) == TIM_TS_TI1FP1) || \
1924  ((__SELECTION__) == TIM_TS_TI2FP2) || \
1925  ((__SELECTION__) == TIM_TS_ETRF))
1926 
1927 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
1928  ((__SELECTION__) == TIM_TS_ITR1) || \
1929  ((__SELECTION__) == TIM_TS_ITR2) || \
1930  ((__SELECTION__) == TIM_TS_ITR3) || \
1931  ((__SELECTION__) == TIM_TS_NONE))
1932 
1933 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
1934  ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
1935  ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
1936  ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
1937  ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
1938 
1939 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
1940  ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
1941  ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
1942  ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
1943 
1944 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1945 
1946 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
1947  ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
1948 
1949 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
1950  ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
1951  ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
1952  ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
1953  ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
1954  ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
1955  ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
1956  ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
1957  ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
1958  ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
1959  ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
1960  ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
1961  ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
1962  ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
1963  ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
1964  ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
1965  ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
1966  ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
1967 
1968 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1969 
1970 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
1971 
1972 #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \
1973  ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \
1974  ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \
1975  ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
1976 
1977 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
1978  ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
1979 
1980 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
1981  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
1982  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
1983  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
1984  ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
1985 
1986 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
1987  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
1988  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
1989  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
1990  ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
1991 
1992 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1993  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
1994  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
1995  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
1996  ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
1997 
1998 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
1999  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
2000  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
2001  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
2002  ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
2003 
2007 /* End of private macros -----------------------------------------------------*/
2008 
2009 /* Include TIM HAL Extended module */
2010 #include "stm32f7xx_hal_tim_ex.h"
2011 
2012 /* Exported functions --------------------------------------------------------*/
2021 /* Time Base functions ********************************************************/
2022 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
2023 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
2024 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
2025 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
2026 /* Blocking mode: Polling */
2027 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
2028 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
2029 /* Non-Blocking mode: Interrupt */
2030 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
2031 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
2032 /* Non-Blocking mode: DMA */
2033 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
2034 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
2043 /* Timer Output Compare functions *********************************************/
2044 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
2045 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
2046 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
2047 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
2048 /* Blocking mode: Polling */
2049 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2050 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2051 /* Non-Blocking mode: Interrupt */
2052 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2053 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2054 /* Non-Blocking mode: DMA */
2055 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
2056 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2065 /* Timer PWM functions ********************************************************/
2066 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
2067 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
2068 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
2069 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
2070 /* Blocking mode: Polling */
2071 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2072 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2073 /* Non-Blocking mode: Interrupt */
2074 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2075 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2076 /* Non-Blocking mode: DMA */
2077 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
2078 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2087 /* Timer Input Capture functions **********************************************/
2088 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
2089 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
2090 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
2091 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
2092 /* Blocking mode: Polling */
2093 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2094 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2095 /* Non-Blocking mode: Interrupt */
2096 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2097 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2098 /* Non-Blocking mode: DMA */
2099 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
2100 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2109 /* Timer One Pulse functions **************************************************/
2110 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
2111 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
2112 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
2113 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
2114 /* Blocking mode: Polling */
2115 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2116 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2117 /* Non-Blocking mode: Interrupt */
2118 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2119 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2128 /* Timer Encoder functions ****************************************************/
2129 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
2130 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
2131 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
2132 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
2133 /* Blocking mode: Polling */
2134 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2135 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2136 /* Non-Blocking mode: Interrupt */
2137 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2138 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2139 /* Non-Blocking mode: DMA */
2140 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
2141  uint32_t *pData2, uint16_t Length);
2142 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2151 /* Interrupt Handler functions ***********************************************/
2152 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
2161 /* Control functions *********************************************************/
2162 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
2163 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
2164 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
2165 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
2166  uint32_t OutputChannel, uint32_t InputChannel);
2167 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
2168  uint32_t Channel);
2169 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
2170 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
2171 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
2172 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
2173 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2174  uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
2175 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
2176 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2177  uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
2178 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
2179 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
2180 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
2189 /* Callback in non blocking modes (Interrupt and DMA) *************************/
2190 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
2191 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
2192 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
2193 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
2194 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
2195 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
2196 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
2197 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
2198 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
2199 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
2200 
2201 /* Callbacks Register/UnRegister functions ***********************************/
2202 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2203 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
2204  pTIM_CallbackTypeDef pCallback);
2205 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
2206 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2207 
2216 /* Peripheral State functions ************************************************/
2217 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
2218 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
2219 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
2220 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
2221 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
2222 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
2230 /* End of exported functions -------------------------------------------------*/
2231 
2232 /* Private functions----------------------------------------------------------*/
2236 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
2237 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
2238 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
2239 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
2240  uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
2241 
2242 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
2243 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
2244 void TIM_DMAError(DMA_HandleTypeDef *hdma);
2245 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
2246 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
2247 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
2248 
2249 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2250 void TIM_ResetCallback(TIM_HandleTypeDef *htim);
2251 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2252 
2256 /* End of private functions --------------------------------------------------*/
2257 
2266 #ifdef __cplusplus
2267 }
2268 #endif
2269 
2270 #endif /* STM32F7xx_HAL_TIM_H */
2271 
2272 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_TIM_TriggerHalfCpltCallback
void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
HAL_TIM_STATE_TIMEOUT
@ HAL_TIM_STATE_TIMEOUT
Definition: stm32f7xx_hal_tim.h:303
HAL_TIM_IC_Start_DMA
HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
TIM_DMACaptureHalfCplt
void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
__IO
#define __IO
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:237
Init
napi_value Init(napi_env env, napi_value exports)
Definition: porcupine/demo/c/pvrecorder/node/pv_recorder_napi.c:197
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
HAL_TIM_Encoder_Init
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
HAL_TIM_ActiveChannel
HAL_TIM_ActiveChannel
HAL Active channel structures definition.
Definition: stm32f7xx_hal_tim.h:310
HAL_TIM_Base_Stop_IT
HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:139
TIM_CCxChannelCmd
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
HAL_TIM_OC_GetState
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
HAL_TIM_PWM_PulseFinishedHalfCpltCallback
void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
HAL_TIM_IRQHandler
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
HAL_TIM_ConfigTI1Input
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
HAL_TIM_PWM_ConfigChannel
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
HAL_TIM_OnePulse_Stop
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
HAL_TIM_OnePulse_Stop_IT
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
HAL_TIM_IC_GetState
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
HAL_TIM_OC_Stop_DMA
HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
TIM_ETR_SetConfig
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
HAL_TIM_ReadCapturedValue
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_OnePulse_Start
HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
TIM_MasterConfigTypeDef::MasterOutputTrigger2
uint32_t MasterOutputTrigger2
Definition: stm32f7xx_hal_tim.h:235
HAL_TIM_ACTIVE_CHANNEL_3
@ HAL_TIM_ACTIVE_CHANNEL_3
Definition: stm32f7xx_hal_tim.h:314
HAL_TIM_IC_MspDeInit
void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
HAL_TIM_OC_ConfigChannel
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
TIM_DMAError
void TIM_DMAError(DMA_HandleTypeDef *hdma)
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:51
TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:164
HAL_TIM_TriggerCallback
void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
HAL_TIM_IC_Start_IT
HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_OnePulse_MspInit
void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
HAL_TIM_PeriodElapsedHalfCpltCallback
void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
HAL_TIM_Base_Start
HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
HAL_TIM_DMABurst_ReadStart
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
HAL_TIM_ErrorCallback
void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
HAL_TIM_Base_Init
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
TIM_BreakDeadTimeConfigTypeDef::Break2Polarity
uint32_t Break2Polarity
Definition: stm32f7xx_hal_tim.h:287
TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:146
HAL_TIM_SlaveConfigSynchro_IT
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
stm32f7xx_hal_tim_ex.h
Header file of TIM HAL Extended module.
HAL_TIM_PeriodElapsedCallback
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
TIM_TypeDef
TIM.
Definition: stm32f407xx.h:729
HAL_TIM_OC_DelayElapsedCallback
void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
HAL_TIM_OC_Stop_IT
HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:47
HAL_TIM_ACTIVE_CHANNEL_6
@ HAL_TIM_ACTIVE_CHANNEL_6
Definition: stm32f7xx_hal_tim.h:317
HAL_TIM_IC_Init
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
HAL_TIM_Encoder_Stop
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_PWM_Start
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_ACTIVE_CHANNEL_2
@ HAL_TIM_ACTIVE_CHANNEL_2
Definition: stm32f7xx_hal_tim.h:313
HAL_TIM_OnePulse_DeInit
HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
HAL_TIM_Encoder_Start_IT
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_STATE_RESET
@ HAL_TIM_STATE_RESET
Definition: stm32f7xx_hal_tim.h:300
TIM_DMADelayPulseCplt
void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
HAL_TIM_Base_MspInit
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
HAL_TIM_Base_GetState
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
HAL_TIM_Encoder_DeInit
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
HAL_TIM_ACTIVE_CHANNEL_5
@ HAL_TIM_ACTIVE_CHANNEL_5
Definition: stm32f7xx_hal_tim.h:316
HAL_TIM_IC_Stop_DMA
HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:78
HAL_TIM_OC_Start_DMA
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
TIM_HandleTypeDef
TIM Time Base Handle Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:315
HAL_TIM_GenerateEvent
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
HAL_TIM_Base_Stop
HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
HAL_TIM_PWM_PulseFinishedCallback
void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
HAL_TIM_PWM_MspDeInit
void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
TIM_ClockConfigTypeDef
Clock Configuration Handle Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:197
HAL_TIM_OC_Stop
HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
TIM_BreakDeadTimeConfigTypeDef::Break2State
uint32_t Break2State
Definition: stm32f7xx_hal_tim.h:285
HAL_TIM_IC_Stop_IT
HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_OnePulse_ConfigChannel
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
HAL_TIM_Encoder_MspDeInit
void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
HAL_TIM_StateTypeDef
HAL_TIM_StateTypeDef
HAL State structures definition.
Definition: stm32f7xx_hal_tim.h:298
HAL_TIM_Encoder_Stop_IT
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_ConfigClockSource
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
HAL_TIM_PWM_Init
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
TIM_Base_SetConfig
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
HAL_TIM_ACTIVE_CHANNEL_CLEARED
@ HAL_TIM_ACTIVE_CHANNEL_CLEARED
Definition: stm32f7xx_hal_tim.h:318
HAL_TIM_IC_Stop
HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_IC_DeInit
HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
HAL_TIM_IC_ConfigChannel
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
HAL_TIM_STATE_ERROR
@ HAL_TIM_STATE_ERROR
Definition: stm32f7xx_hal_tim.h:304
HAL_TIM_Encoder_MspInit
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
HAL_TIM_OC_Init
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
HAL_TIM_IC_CaptureCallback
void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
TIM_OC2_SetConfig
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
TIM_DMADelayPulseHalfCplt
void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
HAL_TIM_OC_MspDeInit
void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
HAL_TIM_PWM_Stop
HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_OC_Start
HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_Encoder_Stop_DMA
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_SlaveConfigSynchro
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
stm32f7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
TIM_MasterConfigTypeDef
TIM Master configuration Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:229
HAL_TIM_PWM_Start_IT
HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_OnePulse_Start_IT
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
HAL_TIM_PWM_Stop_DMA
HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_Encoder_Start
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_Base_MspDeInit
void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
HAL_TIM_STATE_BUSY
@ HAL_TIM_STATE_BUSY
Definition: stm32f7xx_hal_tim.h:302
HAL_TIM_IC_Start
HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_Encoder_Start_DMA
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
TIM_DMACaptureCplt
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
TIM_BreakDeadTimeConfigTypeDef::Break2Filter
uint32_t Break2Filter
Definition: stm32f7xx_hal_tim.h:289
HAL_TIM_PWM_MspInit
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
HAL_TIM_OC_Start_IT
HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_DMABurst_WriteStart
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
HAL_TIM_OnePulse_MspDeInit
void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
HAL_TIM_DMABurst_WriteStop
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
HAL_TIM_OC_MspInit
void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
HAL_TIM_ConfigOCrefClear
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
HAL_TIM_Encoder_GetState
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
HAL_TIM_PWM_Stop_IT
HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
TIM_ClearInputConfigTypeDef
TIM Clear Input Configuration Handle Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:212
HAL_TIM_OnePulse_Init
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:110
HAL_TIM_OnePulse_GetState
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
HAL_TIM_PWM_Start_DMA
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
HAL_TIM_OC_DeInit
HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
HAL_TIM_DMABurst_ReadStop
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
HAL_TIM_IC_CaptureHalfCpltCallback
void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
HAL_TIM_IC_MspInit
void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
HAL_TIM_Base_Start_DMA
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
HAL_TIM_PWM_DeInit
HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
TIM_BreakDeadTimeConfigTypeDef
TIM Break input(s) and Dead time configuration Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:265
HAL_TIM_Base_Stop_DMA
HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
HAL_TIM_Base_Start_IT
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
HAL_TIM_STATE_READY
@ HAL_TIM_STATE_READY
Definition: stm32f7xx_hal_tim.h:301
HAL_TIM_PWM_GetState
HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
HAL_TIM_ACTIVE_CHANNEL_4
@ HAL_TIM_ACTIVE_CHANNEL_4
Definition: stm32f7xx_hal_tim.h:315
TIM_TI1_SetConfig
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
HAL_TIM_ACTIVE_CHANNEL_1
@ HAL_TIM_ACTIVE_CHANNEL_1
Definition: stm32f7xx_hal_tim.h:312
TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h:245
HAL_TIM_Base_DeInit
HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)

picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:14:53