stm32f7xx_hal_smbus.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32F7xx_HAL_SMBUS_H
22 #define STM32F7xx_HAL_SMBUS_H
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f7xx_hal_def.h"
30 
39 /* Exported types ------------------------------------------------------------*/
48 typedef struct
49 {
50  uint32_t Timing;
53  uint32_t AnalogFilter;
56  uint32_t OwnAddress1;
59  uint32_t AddressingMode;
62  uint32_t DualAddressMode;
65  uint32_t OwnAddress2;
68  uint32_t OwnAddress2Masks;
71  uint32_t GeneralCallMode;
74  uint32_t NoStretchMode;
77  uint32_t PacketErrorCheckMode;
80  uint32_t PeripheralMode;
83  uint32_t SMBusTimeout;
87 } SMBUS_InitTypeDef;
96 #define HAL_SMBUS_STATE_RESET (0x00000000U)
97 #define HAL_SMBUS_STATE_READY (0x00000001U)
98 #define HAL_SMBUS_STATE_BUSY (0x00000002U)
99 #define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U)
100 #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U)
101 #define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U)
102 #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U)
103 #define HAL_SMBUS_STATE_TIMEOUT (0x00000003U)
104 #define HAL_SMBUS_STATE_ERROR (0x00000004U)
105 #define HAL_SMBUS_STATE_LISTEN (0x00000008U)
114 #define HAL_SMBUS_ERROR_NONE (0x00000000U)
115 #define HAL_SMBUS_ERROR_BERR (0x00000001U)
116 #define HAL_SMBUS_ERROR_ARLO (0x00000002U)
117 #define HAL_SMBUS_ERROR_ACKF (0x00000004U)
118 #define HAL_SMBUS_ERROR_OVR (0x00000008U)
119 #define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U)
120 #define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U)
121 #define HAL_SMBUS_ERROR_ALERT (0x00000040U)
122 #define HAL_SMBUS_ERROR_PECERR (0x00000080U)
123 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
124 #define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U)
125 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
126 #define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U)
135 typedef struct __SMBUS_HandleTypeDef
136 {
137  I2C_TypeDef *Instance;
139  SMBUS_InitTypeDef Init;
141  uint8_t *pBuffPtr;
143  uint16_t XferSize;
145  __IO uint16_t XferCount;
147  __IO uint32_t XferOptions;
149  __IO uint32_t PreviousState;
151  HAL_LockTypeDef Lock;
153  __IO uint32_t State;
155  __IO uint32_t ErrorCode;
157 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
158  void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
159  void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
160  void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
161  void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
162  void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
163  void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
165  void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
167  void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
168  void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
170 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
171 } SMBUS_HandleTypeDef;
172 
173 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
174 
177 typedef enum
178 {
179  HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U,
180  HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U,
181  HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U,
182  HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U,
183  HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U,
184  HAL_SMBUS_ERROR_CB_ID = 0x05U,
186  HAL_SMBUS_MSPINIT_CB_ID = 0x06U,
187  HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U
189 } HAL_SMBUS_CallbackIDTypeDef;
190 
194 typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus);
195 typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
197 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
198 
205 /* Exported constants --------------------------------------------------------*/
206 
214 #define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
215 #define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
216 
223 #define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
224 #define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
225 
233 #define SMBUS_DUALADDRESS_DISABLE (0x00000000U)
234 #define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
235 
243 #define SMBUS_OA2_NOMASK ((uint8_t)0x00U)
244 #define SMBUS_OA2_MASK01 ((uint8_t)0x01U)
245 #define SMBUS_OA2_MASK02 ((uint8_t)0x02U)
246 #define SMBUS_OA2_MASK03 ((uint8_t)0x03U)
247 #define SMBUS_OA2_MASK04 ((uint8_t)0x04U)
248 #define SMBUS_OA2_MASK05 ((uint8_t)0x05U)
249 #define SMBUS_OA2_MASK06 ((uint8_t)0x06U)
250 #define SMBUS_OA2_MASK07 ((uint8_t)0x07U)
251 
259 #define SMBUS_GENERALCALL_DISABLE (0x00000000U)
260 #define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
261 
268 #define SMBUS_NOSTRETCH_DISABLE (0x00000000U)
269 #define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
270 
277 #define SMBUS_PEC_DISABLE (0x00000000U)
278 #define SMBUS_PEC_ENABLE I2C_CR1_PECEN
279 
286 #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
287 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
288 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
289 
297 #define SMBUS_SOFTEND_MODE (0x00000000U)
298 #define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
299 #define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
300 #define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
301 
309 #define SMBUS_NO_STARTSTOP (0x00000000U)
310 #define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
311 #define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
312 #define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
313 
321 /* List of XferOptions in usage of :
322  * 1- Restart condition when direction change
323  * 2- No Restart condition in other use cases
324  */
325 #define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
326 #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
327 #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
328 #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
329 #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
330 #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
331 
332 /* List of XferOptions in usage of :
333  * 1- Restart condition in all use cases (direction change or not)
334  */
335 #define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
336 #define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
337 #define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
338 #define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
339 
349 #define SMBUS_IT_ERRI I2C_CR1_ERRIE
350 #define SMBUS_IT_TCI I2C_CR1_TCIE
351 #define SMBUS_IT_STOPI I2C_CR1_STOPIE
352 #define SMBUS_IT_NACKI I2C_CR1_NACKIE
353 #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
354 #define SMBUS_IT_RXI I2C_CR1_RXIE
355 #define SMBUS_IT_TXI I2C_CR1_TXIE
356 #define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
357 #define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
358 #define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
359 #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
360 
371 #define SMBUS_FLAG_TXE I2C_ISR_TXE
372 #define SMBUS_FLAG_TXIS I2C_ISR_TXIS
373 #define SMBUS_FLAG_RXNE I2C_ISR_RXNE
374 #define SMBUS_FLAG_ADDR I2C_ISR_ADDR
375 #define SMBUS_FLAG_AF I2C_ISR_NACKF
376 #define SMBUS_FLAG_STOPF I2C_ISR_STOPF
377 #define SMBUS_FLAG_TC I2C_ISR_TC
378 #define SMBUS_FLAG_TCR I2C_ISR_TCR
379 #define SMBUS_FLAG_BERR I2C_ISR_BERR
380 #define SMBUS_FLAG_ARLO I2C_ISR_ARLO
381 #define SMBUS_FLAG_OVR I2C_ISR_OVR
382 #define SMBUS_FLAG_PECERR I2C_ISR_PECERR
383 #define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
384 #define SMBUS_FLAG_ALERT I2C_ISR_ALERT
385 #define SMBUS_FLAG_BUSY I2C_ISR_BUSY
386 #define SMBUS_FLAG_DIR I2C_ISR_DIR
387 
395 /* Exported macros ------------------------------------------------------------*/
404 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
405 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
406  (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
407  (__HANDLE__)->MspInitCallback = NULL; \
408  (__HANDLE__)->MspDeInitCallback = NULL; \
409  } while(0)
410 #else
411 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
412 #endif
413 
428 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
429 
444 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
445 
460 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
461 
485 #define SMBUS_FLAG_MASK (0x0001FFFFU)
486 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
487 
504 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
505 
510 #define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
511 
516 #define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
517 
522 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
523 
529 /* Private constants ---------------------------------------------------------*/
530 
531 /* Private macros ------------------------------------------------------------*/
536 #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
537  ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
538 
539 #define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
540 
541 #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
542  ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
543 
544 #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
545  ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
546 
547 #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
548  ((MASK) == SMBUS_OA2_MASK01) || \
549  ((MASK) == SMBUS_OA2_MASK02) || \
550  ((MASK) == SMBUS_OA2_MASK03) || \
551  ((MASK) == SMBUS_OA2_MASK04) || \
552  ((MASK) == SMBUS_OA2_MASK05) || \
553  ((MASK) == SMBUS_OA2_MASK06) || \
554  ((MASK) == SMBUS_OA2_MASK07))
555 
556 #define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
557  ((CALL) == SMBUS_GENERALCALL_ENABLE))
558 
559 #define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
560  ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
561 
562 #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
563  ((PEC) == SMBUS_PEC_ENABLE))
564 
565 #define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
566  ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
567  ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
568 
569 #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
570  ((MODE) == SMBUS_AUTOEND_MODE) || \
571  ((MODE) == SMBUS_SOFTEND_MODE) || \
572  ((MODE) == SMBUS_SENDPEC_MODE) || \
573  ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
574  ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
575  ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
576  ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
577 
578 
579 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
580  ((REQUEST) == SMBUS_GENERATE_START_READ) || \
581  ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
582  ((REQUEST) == SMBUS_NO_STARTSTOP))
583 
584 
585 #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
586  ((REQUEST) == SMBUS_FIRST_FRAME) || \
587  ((REQUEST) == SMBUS_NEXT_FRAME) || \
588  ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
589  ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
590  ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
591  ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
592 
593 #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
594  ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
595  ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
596  ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
597 
598 #define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
599 #define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
600 
601 #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
602  (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
603 
604 #define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
605 #define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
606 #define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
607 #define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
608 #define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
609 
610 #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
611 #define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
612 
613 #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
614 #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
615 
620 /* Exported functions --------------------------------------------------------*/
629 /* Initialization and de-initialization functions ****************************/
630 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
631 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
632 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
633 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
634 HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
635 HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
636 
637 /* Callbacks Register/UnRegister functions ***********************************/
638 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
639 HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback);
640 HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID);
641 
642 HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback);
643 HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
644 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
645 
653 /* IO operation functions *****************************************************/
657 /******* Blocking mode: Polling */
658 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
666 /******* Non-Blocking mode: Interrupt */
667 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
668 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
669 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
670 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
671 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
672 
673 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
674 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
675 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
676 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
684 /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
685 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
686 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
687 void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
688 void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
689 void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
690 void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
691 void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
692 void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
693 void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
694 
703 /* Peripheral State and Errors functions **************************************************/
704 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
705 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
706 
715 /* Private Functions ---------------------------------------------------------*/
719 /* Private functions are defined in stm32f7xx_hal_smbus.c file */
736 #ifdef __cplusplus
737 }
738 #endif
739 
740 
741 #endif /* STM32F7xx_HAL_SMBUS_H */
742 
743 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
__IO
#define __IO
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:237
Init
napi_value Init(napi_env env, napi_value exports)
Definition: porcupine/demo/c/pvrecorder/node/pv_recorder_napi.c:197
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
__SMARTCARD_HandleTypeDef::Instance
USART_TypeDef * Instance
Definition: stm32f4xx_hal_smartcard.h:156
SMBUS_InitTypeDef::SMBusTimeout
uint32_t SMBusTimeout
Definition: stm32f7xx_hal_smbus.h:83
SMBUS_InitTypeDef::Timing
uint32_t Timing
Definition: stm32f7xx_hal_smbus.h:50
HAL_SMBUS_Master_Abort_IT
HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
HAL_SMBUS_AddrCallback
void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
HAL_SMBUS_EV_IRQHandler
void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
HAL_SMBUS_Slave_Transmit_IT
HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
HAL_SMBUS_MasterRxCpltCallback
void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
HAL_SMBUS_GetState
HAL_SMBUS_StateTypeDef HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
HAL_SMBUS_DeInit
HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
HAL_SMBUS_Master_Receive_IT
HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
__SMARTCARD_HandleTypeDef::Lock
HAL_LockTypeDef Lock
Definition: stm32f4xx_hal_smartcard.h:176
__SMBUS_HandleTypeDef::XferOptions
__IO uint32_t XferOptions
Definition: stm32f4xx_hal_smbus.h:164
__SMBUS_HandleTypeDef
SMBUS handle Structure definition.
Definition: stm32f4xx_hal_smbus.h:152
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f407xx.h:557
HAL_SMBUS_MspDeInit
void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
HAL_SMBUS_IsDeviceReady
HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:51
HAL_SMBUS_ListenCpltCallback
void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
SMBUS_HandleTypeDef
struct __SMBUS_HandleTypeDef SMBUS_HandleTypeDef
SMBUS_InitTypeDef
SMBUS Configuration Structure definition.
Definition: stm32f4xx_hal_smbus.h:47
HAL_SMBUS_GetError
uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
HAL_SMBUS_MasterTxCpltCallback
void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
HAL_SMBUS_ConfigAnalogFilter
HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
HAL_SMBUS_EnableListen_IT
HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
HAL_SMBUS_ConfigDigitalFilter
HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
HAL_SMBUS_SlaveTxCpltCallback
void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
HAL_SMBUS_SlaveRxCpltCallback
void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
SMBUS_InitTypeDef::OwnAddress2Masks
uint32_t OwnAddress2Masks
Definition: stm32f7xx_hal_smbus.h:68
HAL_SMBUS_Slave_Receive_IT
HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
HAL_SMBUS_Master_Transmit_IT
HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
HAL_SMBUS_DisableListen_IT
HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
stm32f7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_SMBUS_EnableAlert_IT
HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
HAL_SMBUS_ErrorCallback
void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
__SMBUS_HandleTypeDef::State
__IO uint32_t State
Definition: stm32f7xx_hal_smbus.h:153
__SMARTCARD_HandleTypeDef::ErrorCode
__IO uint32_t ErrorCode
Definition: stm32f4xx_hal_smartcard.h:185
HAL_SMBUS_DisableAlert_IT
HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
HAL_SMBUS_ER_IRQHandler
void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
HAL_SMBUS_MspInit
void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
HAL_SMBUS_Init
HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)

picovoice_driver
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autogenerated on Fri Apr 1 2022 02:14:53