stm32f7xx_hal_rcc_ex.c
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1 
24 /* Includes ------------------------------------------------------------------*/
25 #include "stm32f7xx_hal.h"
26 
36 #ifdef HAL_RCC_MODULE_ENABLED
37 
38 /* Private typedef -----------------------------------------------------------*/
39 /* Private define ------------------------------------------------------------*/
46 /* Private macro -------------------------------------------------------------*/
63 /* Private variables ---------------------------------------------------------*/
64 /* Private function prototypes -----------------------------------------------*/
65 /* Private functions ---------------------------------------------------------*/
66 
90 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || \
91  defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || \
92  defined (STM32F750xx)
93 
107 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
108 {
109  uint32_t tickstart = 0;
110  uint32_t tmpreg0 = 0;
111  uint32_t tmpreg1 = 0;
112  uint32_t plli2sused = 0;
113  uint32_t pllsaiused = 0;
114 
115  /* Check the parameters */
116  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
117 
118  /*----------------------------------- I2S configuration ----------------------------------*/
119  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
120  {
121  /* Check the parameters */
122  assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
123 
124  /* Configure I2S Clock source */
125  __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
126 
127  /* Enable the PLLI2S when it's used as clock source for I2S */
128  if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
129  {
130  plli2sused = 1;
131  }
132  }
133 
134  /*------------------------------------ SAI1 configuration --------------------------------------*/
135  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
136  {
137  /* Check the parameters */
138  assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
139 
140  /* Configure SAI1 Clock source */
141  __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
142  /* Enable the PLLI2S when it's used as clock source for SAI */
143  if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
144  {
145  plli2sused = 1;
146  }
147  /* Enable the PLLSAI when it's used as clock source for SAI */
148  if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
149  {
150  pllsaiused = 1;
151  }
152  }
153 
154  /*------------------------------------ SAI2 configuration --------------------------------------*/
155  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
156  {
157  /* Check the parameters */
158  assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
159 
160  /* Configure SAI2 Clock source */
161  __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
162 
163  /* Enable the PLLI2S when it's used as clock source for SAI */
164  if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
165  {
166  plli2sused = 1;
167  }
168  /* Enable the PLLSAI when it's used as clock source for SAI */
169  if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
170  {
171  pllsaiused = 1;
172  }
173  }
174 
175  /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/
176  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
177  {
178  plli2sused = 1;
179  }
180 
181  /*------------------------------------ RTC configuration --------------------------------------*/
182  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
183  {
184  /* Check for RTC Parameters used to output RTCCLK */
185  assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
186 
187  /* Enable Power Clock*/
188  __HAL_RCC_PWR_CLK_ENABLE();
189 
190  /* Enable write access to Backup domain */
191  PWR->CR1 |= PWR_CR1_DBP;
192 
193  /* Get Start Tick*/
194  tickstart = HAL_GetTick();
195 
196  /* Wait for Backup domain Write protection disable */
197  while((PWR->CR1 & PWR_CR1_DBP) == RESET)
198  {
199  if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
200  {
201  return HAL_TIMEOUT;
202  }
203  }
204 
205  /* Reset the Backup domain only if the RTC Clock source selection is modified */
206  tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
207 
208  if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
209  {
210  /* Store the content of BDCR register before the reset of Backup Domain */
211  tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
212 
213  /* RTC Clock selection can be changed only if the Backup Domain is reset */
214  __HAL_RCC_BACKUPRESET_FORCE();
215  __HAL_RCC_BACKUPRESET_RELEASE();
216 
217  /* Restore the Content of BDCR register */
218  RCC->BDCR = tmpreg0;
219 
220  /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
221  if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
222  {
223  /* Get Start Tick*/
224  tickstart = HAL_GetTick();
225 
226  /* Wait till LSE is ready */
227  while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
228  {
229  if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
230  {
231  return HAL_TIMEOUT;
232  }
233  }
234  }
235  }
236  __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
237  }
238 
239  /*------------------------------------ TIM configuration --------------------------------------*/
240  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
241  {
242  /* Check the parameters */
243  assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
244 
245  /* Configure Timer Prescaler */
246  __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
247  }
248 
249  /*-------------------------------------- I2C1 Configuration -----------------------------------*/
250  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
251  {
252  /* Check the parameters */
253  assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
254 
255  /* Configure the I2C1 clock source */
256  __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
257  }
258 
259  /*-------------------------------------- I2C2 Configuration -----------------------------------*/
260  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
261  {
262  /* Check the parameters */
263  assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
264 
265  /* Configure the I2C2 clock source */
266  __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
267  }
268 
269  /*-------------------------------------- I2C3 Configuration -----------------------------------*/
270  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
271  {
272  /* Check the parameters */
273  assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
274 
275  /* Configure the I2C3 clock source */
276  __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
277  }
278 
279  /*-------------------------------------- I2C4 Configuration -----------------------------------*/
280  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
281  {
282  /* Check the parameters */
283  assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
284 
285  /* Configure the I2C4 clock source */
286  __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
287  }
288 
289  /*-------------------------------------- USART1 Configuration -----------------------------------*/
290  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
291  {
292  /* Check the parameters */
293  assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
294 
295  /* Configure the USART1 clock source */
296  __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
297  }
298 
299  /*-------------------------------------- USART2 Configuration -----------------------------------*/
300  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
301  {
302  /* Check the parameters */
303  assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
304 
305  /* Configure the USART2 clock source */
306  __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
307  }
308 
309  /*-------------------------------------- USART3 Configuration -----------------------------------*/
310  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
311  {
312  /* Check the parameters */
313  assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
314 
315  /* Configure the USART3 clock source */
316  __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
317  }
318 
319  /*-------------------------------------- UART4 Configuration -----------------------------------*/
320  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
321  {
322  /* Check the parameters */
323  assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
324 
325  /* Configure the UART4 clock source */
326  __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
327  }
328 
329  /*-------------------------------------- UART5 Configuration -----------------------------------*/
330  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
331  {
332  /* Check the parameters */
333  assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
334 
335  /* Configure the UART5 clock source */
336  __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
337  }
338 
339  /*-------------------------------------- USART6 Configuration -----------------------------------*/
340  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
341  {
342  /* Check the parameters */
343  assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
344 
345  /* Configure the USART6 clock source */
346  __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
347  }
348 
349  /*-------------------------------------- UART7 Configuration -----------------------------------*/
350  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
351  {
352  /* Check the parameters */
353  assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
354 
355  /* Configure the UART7 clock source */
356  __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
357  }
358 
359  /*-------------------------------------- UART8 Configuration -----------------------------------*/
360  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
361  {
362  /* Check the parameters */
363  assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
364 
365  /* Configure the UART8 clock source */
366  __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
367  }
368 
369  /*--------------------------------------- CEC Configuration -----------------------------------*/
370  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
371  {
372  /* Check the parameters */
373  assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
374 
375  /* Configure the CEC clock source */
376  __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
377  }
378 
379  /*-------------------------------------- CK48 Configuration -----------------------------------*/
380  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
381  {
382  /* Check the parameters */
383  assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
384 
385  /* Configure the CLK48 source */
386  __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
387 
388  /* Enable the PLLSAI when it's used as clock source for CK48 */
389  if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
390  {
391  pllsaiused = 1;
392  }
393  }
394 
395  /*-------------------------------------- LTDC Configuration -----------------------------------*/
396 #if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
397  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
398  {
399  pllsaiused = 1;
400  }
401 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
402 
403  /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
404  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
405  {
406  /* Check the parameters */
407  assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
408 
409  /* Configure the LTPIM1 clock source */
410  __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
411  }
412 
413  /*------------------------------------- SDMMC1 Configuration ------------------------------------*/
414  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
415  {
416  /* Check the parameters */
417  assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
418 
419  /* Configure the SDMMC1 clock source */
420  __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
421  }
422 
423 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
424  /*------------------------------------- SDMMC2 Configuration ------------------------------------*/
425  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
426  {
427  /* Check the parameters */
428  assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
429 
430  /* Configure the SDMMC2 clock source */
431  __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
432  }
433 
434  /*------------------------------------- DFSDM1 Configuration -------------------------------------*/
435  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
436  {
437  /* Check the parameters */
438  assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
439 
440  /* Configure the DFSDM1 interface clock source */
441  __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
442  }
443 
444  /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/
445  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
446  {
447  /* Check the parameters */
448  assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
449 
450  /* Configure the DFSDM interface clock source */
451  __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
452  }
453 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
454 
455  /*-------------------------------------- PLLI2S Configuration ---------------------------------*/
456  /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
457  if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
458  {
459  /* Disable the PLLI2S */
460  __HAL_RCC_PLLI2S_DISABLE();
461 
462  /* Get Start Tick*/
463  tickstart = HAL_GetTick();
464 
465  /* Wait till PLLI2S is disabled */
466  while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
467  {
468  if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
469  {
470  /* return in case of Timeout detected */
471  return HAL_TIMEOUT;
472  }
473  }
474 
475  /* check for common PLLI2S Parameters */
476  assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
477 
478  /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
479  if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
480  {
481  /* check for Parameters */
482  assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
483 
484  /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
485  tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
486  tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
487  /* Configure the PLLI2S division factors */
488  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
489  /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
490  __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
491  }
492 
493  /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
494  if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
495  ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
496  {
497  /* Check for PLLI2S Parameters */
498  assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
499  /* Check for PLLI2S/DIVQ parameters */
500  assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
501 
502  /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
503  tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
504  tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
505  /* Configure the PLLI2S division factors */
506  /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
507  /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
508  /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
509  __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
510 
511  /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
512  __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
513  }
514 
515  /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/
516  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
517  {
518  /* check for Parameters */
519  assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
520 
521  /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */
522  tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
523  tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
524  /* Configure the PLLI2S division factors */
525  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
526  /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
527  __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
528  }
529 
530  /*----------------- In Case of PLLI2S is just selected -----------------*/
531  if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
532  {
533  /* Check for Parameters */
534  assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
535  assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
536  assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
537 
538  /* Configure the PLLI2S division factors */
539  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
540  /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
541  __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
542  }
543 
544  /* Enable the PLLI2S */
545  __HAL_RCC_PLLI2S_ENABLE();
546 
547  /* Get Start Tick*/
548  tickstart = HAL_GetTick();
549 
550  /* Wait till PLLI2S is ready */
551  while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
552  {
553  if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
554  {
555  /* return in case of Timeout detected */
556  return HAL_TIMEOUT;
557  }
558  }
559  }
560 
561  /*-------------------------------------- PLLSAI Configuration ---------------------------------*/
562  /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
563  if(pllsaiused == 1)
564  {
565  /* Disable PLLSAI Clock */
566  __HAL_RCC_PLLSAI_DISABLE();
567 
568  /* Get Start Tick*/
569  tickstart = HAL_GetTick();
570 
571  /* Wait till PLLSAI is disabled */
572  while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
573  {
574  if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
575  {
576  /* return in case of Timeout detected */
577  return HAL_TIMEOUT;
578  }
579  }
580 
581  /* Check the PLLSAI division factors */
582  assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
583 
584  /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
585  if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
586  ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
587  {
588  /* check for PLLSAIQ Parameter */
589  assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
590  /* check for PLLSAI/DIVQ Parameter */
591  assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
592 
593  /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
594  tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
595  tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
596  /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
597  /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
598  /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
599  __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
600 
601  /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
602  __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
603  }
604 
605  /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
606  /* In Case of PLLI2S is selected as source clock for CK48 */
607  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
608  {
609  /* check for Parameters */
610  assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
611  /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
612  tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
613  tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
614 
615  /* Configure the PLLSAI division factors */
616  /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
617  /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
618  __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
619  }
620 
621 #if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
622  /*---------------------------- LTDC configuration -------------------------------*/
623  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
624  {
625  assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
626  assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
627 
628  /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */
629  tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
630  tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
631 
632  /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
633  /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
634  /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
635  __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);
636 
637  /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
638  __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
639  }
640 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
641 
642  /* Enable PLLSAI Clock */
643  __HAL_RCC_PLLSAI_ENABLE();
644 
645  /* Get Start Tick*/
646  tickstart = HAL_GetTick();
647 
648  /* Wait till PLLSAI is ready */
649  while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
650  {
651  if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
652  {
653  /* return in case of Timeout detected */
654  return HAL_TIMEOUT;
655  }
656  }
657  }
658  return HAL_OK;
659 }
660 
667 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
668 {
669  uint32_t tempreg = 0;
670 
671  /* Set all possible values for the extended clock type parameter------------*/
672 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
673  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\
674  RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\
675  RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\
676  RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\
677  RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\
678  RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\
679  RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\
680  RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\
681  RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\
682  RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\
683  RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2 |\
684  RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1_AUDIO;
685 #else
686  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\
687  RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\
688  RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\
689  RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\
690  RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\
691  RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\
692  RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\
693  RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\
694  RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\
695  RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\
696  RCC_PERIPHCLK_CLK48;
697 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
698 
699  /* Get the PLLI2S Clock configuration -----------------------------------------------*/
700  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
701  PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
702  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
703  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
704 
705  /* Get the PLLSAI Clock configuration -----------------------------------------------*/
706  PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
707  PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
708  PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
709  PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
710 
711  /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/
712  PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos);
713  PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos);
714  PeriphClkInit->PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> RCC_DCKCFGR1_PLLSAIDIVR_Pos);
715 
716  /* Get the SAI1 clock configuration ----------------------------------------------*/
717  PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
718 
719  /* Get the SAI2 clock configuration ----------------------------------------------*/
720  PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
721 
722  /* Get the I2S clock configuration ------------------------------------------*/
723  PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE();
724 
725  /* Get the I2C1 clock configuration ------------------------------------------*/
726  PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
727 
728  /* Get the I2C2 clock configuration ------------------------------------------*/
729  PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
730 
731  /* Get the I2C3 clock configuration ------------------------------------------*/
732  PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
733 
734  /* Get the I2C4 clock configuration ------------------------------------------*/
735  PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();
736 
737  /* Get the USART1 clock configuration ------------------------------------------*/
738  PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
739 
740  /* Get the USART2 clock configuration ------------------------------------------*/
741  PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
742 
743  /* Get the USART3 clock configuration ------------------------------------------*/
744  PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
745 
746  /* Get the UART4 clock configuration ------------------------------------------*/
747  PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
748 
749  /* Get the UART5 clock configuration ------------------------------------------*/
750  PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
751 
752  /* Get the USART6 clock configuration ------------------------------------------*/
753  PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();
754 
755  /* Get the UART7 clock configuration ------------------------------------------*/
756  PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE();
757 
758  /* Get the UART8 clock configuration ------------------------------------------*/
759  PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE();
760 
761  /* Get the LPTIM1 clock configuration ------------------------------------------*/
762  PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
763 
764  /* Get the CEC clock configuration -----------------------------------------------*/
765  PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
766 
767  /* Get the CK48 clock configuration -----------------------------------------------*/
768  PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
769 
770  /* Get the SDMMC1 clock configuration -----------------------------------------------*/
771  PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();
772 
773 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
774  /* Get the SDMMC2 clock configuration -----------------------------------------------*/
775  PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE();
776 
777  /* Get the DFSDM clock configuration -----------------------------------------------*/
778  PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();
779 
780  /* Get the DFSDM AUDIO clock configuration -----------------------------------------------*/
781  PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();
782 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
783 
784  /* Get the RTC Clock configuration -----------------------------------------------*/
785  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
786  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
787 
788  /* Get the TIM Prescaler configuration --------------------------------------------*/
789  if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET)
790  {
791  PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
792  }
793  else
794  {
795  PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
796  }
797 }
798 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
799 
800 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
801 
815 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
816 {
817  uint32_t tickstart = 0;
818  uint32_t tmpreg0 = 0;
819  uint32_t plli2sused = 0;
820  uint32_t pllsaiused = 0;
821 
822  /* Check the parameters */
823  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
824 
825  /*----------------------------------- I2S configuration ----------------------------------*/
826  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
827  {
828  /* Check the parameters */
829  assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
830 
831  /* Configure I2S Clock source */
832  __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
833 
834  /* Enable the PLLI2S when it's used as clock source for I2S */
835  if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
836  {
837  plli2sused = 1;
838  }
839  }
840 
841  /*------------------------------------ SAI1 configuration --------------------------------------*/
842  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
843  {
844  /* Check the parameters */
845  assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
846 
847  /* Configure SAI1 Clock source */
848  __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
849  /* Enable the PLLI2S when it's used as clock source for SAI */
850  if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
851  {
852  plli2sused = 1;
853  }
854  /* Enable the PLLSAI when it's used as clock source for SAI */
855  if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
856  {
857  pllsaiused = 1;
858  }
859  }
860 
861  /*------------------------------------ SAI2 configuration --------------------------------------*/
862  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
863  {
864  /* Check the parameters */
865  assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
866 
867  /* Configure SAI2 Clock source */
868  __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
869 
870  /* Enable the PLLI2S when it's used as clock source for SAI */
871  if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
872  {
873  plli2sused = 1;
874  }
875  /* Enable the PLLSAI when it's used as clock source for SAI */
876  if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
877  {
878  pllsaiused = 1;
879  }
880  }
881 
882  /*------------------------------------ RTC configuration --------------------------------------*/
883  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
884  {
885  /* Check for RTC Parameters used to output RTCCLK */
886  assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
887 
888  /* Enable Power Clock*/
889  __HAL_RCC_PWR_CLK_ENABLE();
890 
891  /* Enable write access to Backup domain */
892  PWR->CR1 |= PWR_CR1_DBP;
893 
894  /* Get Start Tick*/
895  tickstart = HAL_GetTick();
896 
897  /* Wait for Backup domain Write protection disable */
898  while((PWR->CR1 & PWR_CR1_DBP) == RESET)
899  {
900  if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
901  {
902  return HAL_TIMEOUT;
903  }
904  }
905 
906  /* Reset the Backup domain only if the RTC Clock source selection is modified */
907  tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
908 
909  if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
910  {
911  /* Store the content of BDCR register before the reset of Backup Domain */
912  tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
913 
914  /* RTC Clock selection can be changed only if the Backup Domain is reset */
915  __HAL_RCC_BACKUPRESET_FORCE();
916  __HAL_RCC_BACKUPRESET_RELEASE();
917 
918  /* Restore the Content of BDCR register */
919  RCC->BDCR = tmpreg0;
920 
921  /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
922  if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
923  {
924  /* Get Start Tick*/
925  tickstart = HAL_GetTick();
926 
927  /* Wait till LSE is ready */
928  while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
929  {
930  if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
931  {
932  return HAL_TIMEOUT;
933  }
934  }
935  }
936  }
937  __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
938  }
939 
940  /*------------------------------------ TIM configuration --------------------------------------*/
941  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
942  {
943  /* Check the parameters */
944  assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
945 
946  /* Configure Timer Prescaler */
947  __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
948  }
949 
950  /*-------------------------------------- I2C1 Configuration -----------------------------------*/
951  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
952  {
953  /* Check the parameters */
954  assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
955 
956  /* Configure the I2C1 clock source */
957  __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
958  }
959 
960  /*-------------------------------------- I2C2 Configuration -----------------------------------*/
961  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
962  {
963  /* Check the parameters */
964  assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
965 
966  /* Configure the I2C2 clock source */
967  __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
968  }
969 
970  /*-------------------------------------- I2C3 Configuration -----------------------------------*/
971  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
972  {
973  /* Check the parameters */
974  assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
975 
976  /* Configure the I2C3 clock source */
977  __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
978  }
979 
980  /*-------------------------------------- USART1 Configuration -----------------------------------*/
981  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
982  {
983  /* Check the parameters */
984  assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
985 
986  /* Configure the USART1 clock source */
987  __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
988  }
989 
990  /*-------------------------------------- USART2 Configuration -----------------------------------*/
991  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
992  {
993  /* Check the parameters */
994  assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
995 
996  /* Configure the USART2 clock source */
997  __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
998  }
999 
1000  /*-------------------------------------- USART3 Configuration -----------------------------------*/
1001  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
1002  {
1003  /* Check the parameters */
1004  assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
1005 
1006  /* Configure the USART3 clock source */
1007  __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
1008  }
1009 
1010  /*-------------------------------------- UART4 Configuration -----------------------------------*/
1011  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
1012  {
1013  /* Check the parameters */
1014  assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
1015 
1016  /* Configure the UART4 clock source */
1017  __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
1018  }
1019 
1020  /*-------------------------------------- UART5 Configuration -----------------------------------*/
1021  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
1022  {
1023  /* Check the parameters */
1024  assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
1025 
1026  /* Configure the UART5 clock source */
1027  __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
1028  }
1029 
1030  /*-------------------------------------- USART6 Configuration -----------------------------------*/
1031  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
1032  {
1033  /* Check the parameters */
1034  assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
1035 
1036  /* Configure the USART6 clock source */
1037  __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
1038  }
1039 
1040  /*-------------------------------------- UART7 Configuration -----------------------------------*/
1041  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
1042  {
1043  /* Check the parameters */
1044  assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
1045 
1046  /* Configure the UART7 clock source */
1047  __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
1048  }
1049 
1050  /*-------------------------------------- UART8 Configuration -----------------------------------*/
1051  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
1052  {
1053  /* Check the parameters */
1054  assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
1055 
1056  /* Configure the UART8 clock source */
1057  __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
1058  }
1059 
1060  /*-------------------------------------- CK48 Configuration -----------------------------------*/
1061  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
1062  {
1063  /* Check the parameters */
1064  assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
1065 
1066  /* Configure the CLK48 source */
1067  __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
1068 
1069  /* Enable the PLLSAI when it's used as clock source for CK48 */
1070  if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
1071  {
1072  pllsaiused = 1;
1073  }
1074  }
1075 
1076  /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
1077  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
1078  {
1079  /* Check the parameters */
1080  assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
1081 
1082  /* Configure the LTPIM1 clock source */
1083  __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
1084  }
1085 
1086  /*------------------------------------- SDMMC1 Configuration ------------------------------------*/
1087  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
1088  {
1089  /* Check the parameters */
1090  assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
1091 
1092  /* Configure the SDMMC1 clock source */
1093  __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
1094  }
1095 
1096  /*------------------------------------- SDMMC2 Configuration ------------------------------------*/
1097  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
1098  {
1099  /* Check the parameters */
1100  assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
1101 
1102  /* Configure the SDMMC2 clock source */
1103  __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
1104  }
1105 
1106  /*-------------------------------------- PLLI2S Configuration ---------------------------------*/
1107  /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2 or I2S */
1108  if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
1109  {
1110  /* Disable the PLLI2S */
1111  __HAL_RCC_PLLI2S_DISABLE();
1112 
1113  /* Get Start Tick*/
1114  tickstart = HAL_GetTick();
1115 
1116  /* Wait till PLLI2S is disabled */
1117  while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
1118  {
1119  if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
1120  {
1121  /* return in case of Timeout detected */
1122  return HAL_TIMEOUT;
1123  }
1124  }
1125 
1126  /* check for common PLLI2S Parameters */
1127  assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
1128 
1129  /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
1130  if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
1131  {
1132  /* check for Parameters */
1133  assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
1134 
1135  /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
1136  tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
1137  /* Configure the PLLI2S division factors */
1138  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
1139  /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
1140  __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, PeriphClkInit->PLLI2S.PLLI2SR);
1141  }
1142 
1143  /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
1144  if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
1145  ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
1146  {
1147  /* Check for PLLI2S Parameters */
1148  assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
1149  /* Check for PLLI2S/DIVQ parameters */
1150  assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
1151 
1152  /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
1153  tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
1154  /* Configure the PLLI2S division factors */
1155  /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
1156  /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
1157  /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
1158  __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg0);
1159 
1160  /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
1161  __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
1162  }
1163 
1164  /*----------------- In Case of PLLI2S is just selected -----------------*/
1165  if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
1166  {
1167  /* Check for Parameters */
1168  assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
1169  assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
1170 
1171  /* Configure the PLLI2S division factors */
1172  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
1173  __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
1174  }
1175 
1176  /* Enable the PLLI2S */
1177  __HAL_RCC_PLLI2S_ENABLE();
1178 
1179  /* Get Start Tick*/
1180  tickstart = HAL_GetTick();
1181 
1182  /* Wait till PLLI2S is ready */
1183  while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
1184  {
1185  if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
1186  {
1187  /* return in case of Timeout detected */
1188  return HAL_TIMEOUT;
1189  }
1190  }
1191  }
1192 
1193  /*-------------------------------------- PLLSAI Configuration ---------------------------------*/
1194  /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
1195  if(pllsaiused == 1)
1196  {
1197  /* Disable PLLSAI Clock */
1198  __HAL_RCC_PLLSAI_DISABLE();
1199 
1200  /* Get Start Tick*/
1201  tickstart = HAL_GetTick();
1202 
1203  /* Wait till PLLSAI is disabled */
1204  while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
1205  {
1206  if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
1207  {
1208  /* return in case of Timeout detected */
1209  return HAL_TIMEOUT;
1210  }
1211  }
1212 
1213  /* Check the PLLSAI division factors */
1214  assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
1215 
1216  /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
1217  if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
1218  ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
1219  {
1220  /* check for PLLSAIQ Parameter */
1221  assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
1222  /* check for PLLSAI/DIVQ Parameter */
1223  assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
1224 
1225  /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
1226  tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
1227  /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
1228  /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
1229  /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
1230  __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ);
1231 
1232  /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
1233  __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
1234  }
1235 
1236  /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
1237  /* In Case of PLLI2S is selected as source clock for CK48 */
1238  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
1239  {
1240  /* check for Parameters */
1241  assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
1242  /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
1243  tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
1244 
1245  /* Configure the PLLSAI division factors */
1246  /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
1247  /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
1248  __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0);
1249  }
1250 
1251  /* Enable PLLSAI Clock */
1252  __HAL_RCC_PLLSAI_ENABLE();
1253 
1254  /* Get Start Tick*/
1255  tickstart = HAL_GetTick();
1256 
1257  /* Wait till PLLSAI is ready */
1258  while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
1259  {
1260  if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
1261  {
1262  /* return in case of Timeout detected */
1263  return HAL_TIMEOUT;
1264  }
1265  }
1266  }
1267  return HAL_OK;
1268 }
1269 
1276 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
1277 {
1278  uint32_t tempreg = 0;
1279 
1280  /* Set all possible values for the extended clock type parameter------------*/
1281  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\
1282  RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\
1283  RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\
1284  RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\
1285  RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\
1286  RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\
1287  RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\
1288  RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\
1289  RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\
1290  RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2;
1291 
1292  /* Get the PLLI2S Clock configuration -----------------------------------------------*/
1293  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
1294  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
1295  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
1296 
1297  /* Get the PLLSAI Clock configuration -----------------------------------------------*/
1298  PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
1299  PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
1300  PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
1301 
1302  /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/
1303  PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos);
1304  PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos);
1305 
1306  /* Get the SAI1 clock configuration ----------------------------------------------*/
1307  PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
1308 
1309  /* Get the SAI2 clock configuration ----------------------------------------------*/
1310  PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
1311 
1312  /* Get the I2S clock configuration ------------------------------------------*/
1313  PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE();
1314 
1315  /* Get the I2C1 clock configuration ------------------------------------------*/
1316  PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
1317 
1318  /* Get the I2C2 clock configuration ------------------------------------------*/
1319  PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
1320 
1321  /* Get the I2C3 clock configuration ------------------------------------------*/
1322  PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
1323 
1324  /* Get the USART1 clock configuration ------------------------------------------*/
1325  PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
1326 
1327  /* Get the USART2 clock configuration ------------------------------------------*/
1328  PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
1329 
1330  /* Get the USART3 clock configuration ------------------------------------------*/
1331  PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
1332 
1333  /* Get the UART4 clock configuration ------------------------------------------*/
1334  PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
1335 
1336  /* Get the UART5 clock configuration ------------------------------------------*/
1337  PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
1338 
1339  /* Get the USART6 clock configuration ------------------------------------------*/
1340  PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();
1341 
1342  /* Get the UART7 clock configuration ------------------------------------------*/
1343  PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE();
1344 
1345  /* Get the UART8 clock configuration ------------------------------------------*/
1346  PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE();
1347 
1348  /* Get the LPTIM1 clock configuration ------------------------------------------*/
1349  PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
1350 
1351  /* Get the CK48 clock configuration -----------------------------------------------*/
1352  PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
1353 
1354  /* Get the SDMMC1 clock configuration -----------------------------------------------*/
1355  PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();
1356 
1357  /* Get the SDMMC2 clock configuration -----------------------------------------------*/
1358  PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE();
1359 
1360  /* Get the RTC Clock configuration -----------------------------------------------*/
1361  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
1362  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
1363 
1364  /* Get the TIM Prescaler configuration --------------------------------------------*/
1365  if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET)
1366  {
1367  PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
1368  }
1369  else
1370  {
1371  PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
1372  }
1373 }
1374 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */
1375 
1385 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
1386 {
1387  uint32_t tmpreg = 0;
1388  /* This variable is used to store the SAI clock frequency (value in Hz) */
1389  uint32_t frequency = 0;
1390  /* This variable is used to store the VCO Input (value in Hz) */
1391  uint32_t vcoinput = 0;
1392  /* This variable is used to store the SAI clock source */
1393  uint32_t saiclocksource = 0;
1394 
1395  if (PeriphClk == RCC_PERIPHCLK_SAI1)
1396  {
1397  saiclocksource = RCC->DCKCFGR1;
1398  saiclocksource &= RCC_DCKCFGR1_SAI1SEL;
1399  switch (saiclocksource)
1400  {
1401  case 0: /* PLLSAI is the clock source for SAI1 */
1402  {
1403  /* Configure the PLLSAI division factor */
1404  /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
1405  if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
1406  {
1407  /* In Case the PLL Source is HSI (Internal Clock) */
1408  vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
1409  }
1410  else
1411  {
1412  /* In Case the PLL Source is HSE (External Clock) */
1413  vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
1414  }
1415  /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
1416  /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
1417  tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
1418  frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
1419 
1420  /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
1421  tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);
1422  frequency = frequency/(tmpreg);
1423  break;
1424  }
1425  case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI1 */
1426  {
1427  /* Configure the PLLI2S division factor */
1428  /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
1429  if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
1430  {
1431  /* In Case the PLL Source is HSI (Internal Clock) */
1432  vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
1433  }
1434  else
1435  {
1436  /* In Case the PLL Source is HSE (External Clock) */
1437  vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
1438  }
1439 
1440  /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
1441  /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
1442  tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
1443  frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
1444 
1445  /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
1446  tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1);
1447  frequency = frequency/(tmpreg);
1448  break;
1449  }
1450  case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI1 */
1451  {
1452  frequency = EXTERNAL_CLOCK_VALUE;
1453  break;
1454  }
1455 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1456  case RCC_DCKCFGR1_SAI1SEL: /* HSI or HSE is the clock source for SAI*/
1457  {
1458  if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
1459  {
1460  /* In Case the main PLL Source is HSI */
1461  frequency = HSI_VALUE;
1462  }
1463  else
1464  {
1465  /* In Case the main PLL Source is HSE */
1466  frequency = HSE_VALUE;
1467  }
1468  break;
1469  }
1470 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1471  default :
1472  {
1473  break;
1474  }
1475  }
1476  }
1477 
1478  if (PeriphClk == RCC_PERIPHCLK_SAI2)
1479  {
1480  saiclocksource = RCC->DCKCFGR1;
1481  saiclocksource &= RCC_DCKCFGR1_SAI2SEL;
1482  switch (saiclocksource)
1483  {
1484  case 0: /* PLLSAI is the clock source for SAI*/
1485  {
1486  /* Configure the PLLSAI division factor */
1487  /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
1488  if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
1489  {
1490  /* In Case the PLL Source is HSI (Internal Clock) */
1491  vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
1492  }
1493  else
1494  {
1495  /* In Case the PLL Source is HSE (External Clock) */
1496  vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
1497  }
1498  /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
1499  /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
1500  tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
1501  frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
1502 
1503  /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
1504  tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);
1505  frequency = frequency/(tmpreg);
1506  break;
1507  }
1508  case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI2 */
1509  {
1510  /* Configure the PLLI2S division factor */
1511  /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
1512  if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
1513  {
1514  /* In Case the PLL Source is HSI (Internal Clock) */
1515  vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
1516  }
1517  else
1518  {
1519  /* In Case the PLL Source is HSE (External Clock) */
1520  vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
1521  }
1522 
1523  /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
1524  /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
1525  tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
1526  frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
1527 
1528  /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
1529  tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1);
1530  frequency = frequency/(tmpreg);
1531  break;
1532  }
1533  case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI2 */
1534  {
1535  frequency = EXTERNAL_CLOCK_VALUE;
1536  break;
1537  }
1538 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1539  case RCC_DCKCFGR1_SAI2SEL: /* HSI or HSE is the clock source for SAI2 */
1540  {
1541  if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
1542  {
1543  /* In Case the main PLL Source is HSI */
1544  frequency = HSI_VALUE;
1545  }
1546  else
1547  {
1548  /* In Case the main PLL Source is HSE */
1549  frequency = HSE_VALUE;
1550  }
1551  break;
1552  }
1553 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1554  default :
1555  {
1556  break;
1557  }
1558  }
1559  }
1560 
1561  return frequency;
1562 }
1563 
1588 HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)
1589 {
1590  uint32_t tickstart;
1591 
1592  /* Check for parameters */
1593  assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN));
1594  assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR));
1595  assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ));
1596 #if defined(RCC_PLLI2SCFGR_PLLI2SP)
1597  assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP));
1598 #endif /* RCC_PLLI2SCFGR_PLLI2SP */
1599 
1600  /* Disable the PLLI2S */
1601  __HAL_RCC_PLLI2S_DISABLE();
1602 
1603  /* Wait till PLLI2S is disabled */
1604  tickstart = HAL_GetTick();
1605  while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
1606  {
1607  if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
1608  {
1609  /* return in case of Timeout detected */
1610  return HAL_TIMEOUT;
1611  }
1612  }
1613 
1614  /* Configure the PLLI2S division factors */
1615 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
1616  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */
1617  /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
1618  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
1619  __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
1620 #else
1621  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */
1622  /* I2SPCLK = PLLI2S_VCO / PLLI2SP */
1623  /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
1624  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
1625  __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
1626 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */
1627 
1628  /* Enable the PLLI2S */
1629  __HAL_RCC_PLLI2S_ENABLE();
1630 
1631  /* Wait till PLLI2S is ready */
1632  tickstart = HAL_GetTick();
1633  while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
1634  {
1635  if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
1636  {
1637  /* return in case of Timeout detected */
1638  return HAL_TIMEOUT;
1639  }
1640  }
1641 
1642  return HAL_OK;
1643 }
1644 
1649 HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
1650 {
1651  uint32_t tickstart;
1652 
1653  /* Disable the PLLI2S */
1654  __HAL_RCC_PLLI2S_DISABLE();
1655 
1656  /* Wait till PLLI2S is disabled */
1657  tickstart = HAL_GetTick();
1658  while(READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)
1659  {
1660  if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
1661  {
1662  /* return in case of Timeout detected */
1663  return HAL_TIMEOUT;
1664  }
1665  }
1666 
1667  return HAL_OK;
1668 }
1669 
1676 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit)
1677 {
1678  uint32_t tickstart;
1679 
1680  /* Check for parameters */
1681  assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN));
1682  assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ));
1683  assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP));
1684 #if defined(RCC_PLLSAICFGR_PLLSAIR)
1685  assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR));
1686 #endif /* RCC_PLLSAICFGR_PLLSAIR */
1687 
1688  /* Disable the PLLSAI */
1689  __HAL_RCC_PLLSAI_DISABLE();
1690 
1691  /* Wait till PLLSAI is disabled */
1692  tickstart = HAL_GetTick();
1693  while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
1694  {
1695  if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
1696  {
1697  /* return in case of Timeout detected */
1698  return HAL_TIMEOUT;
1699  }
1700  }
1701 
1702  /* Configure the PLLSAI division factors */
1703 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
1704  /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */
1705  /* SAIPCLK = PLLSAI_VCO / PLLSAIP */
1706  /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
1707  __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ);
1708 #else
1709  /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */
1710  /* SAIPCLK = PLLSAI_VCO / PLLSAIP */
1711  /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
1712  /* SAIRCLK = PLLSAI_VCO / PLLSAIR */
1713  __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \
1714  PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR);
1715 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */
1716 
1717  /* Enable the PLLSAI */
1718  __HAL_RCC_PLLSAI_ENABLE();
1719 
1720  /* Wait till PLLSAI is ready */
1721  tickstart = HAL_GetTick();
1722  while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
1723  {
1724  if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
1725  {
1726  /* return in case of Timeout detected */
1727  return HAL_TIMEOUT;
1728  }
1729  }
1730 
1731  return HAL_OK;
1732 }
1733 
1738 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void)
1739 {
1740  uint32_t tickstart;
1741 
1742  /* Disable the PLLSAI */
1743  __HAL_RCC_PLLSAI_DISABLE();
1744 
1745  /* Wait till PLLSAI is disabled */
1746  tickstart = HAL_GetTick();
1747  while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
1748  {
1749  if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
1750  {
1751  /* return in case of Timeout detected */
1752  return HAL_TIMEOUT;
1753  }
1754  }
1755 
1756  return HAL_OK;
1757 }
1758 
1767 #endif /* HAL_RCC_MODULE_ENABLED */
1768 
1776 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
__HAL_RCC_I2C1_CONFIG
#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__)
Macro to configure the I2C1 clock (I2C1CLK).
Definition: stm32f7xx_hal_rcc_ex.h:2823
IS_RCC_I2C1CLKSOURCE
#define IS_RCC_I2C1CLKSOURCE(SOURCE)
Definition: stm32f7xx_hal_rcc_ex.h:3433
__HAL_RCC_LPTIM1_CONFIG
#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__)
Macro to configure the LPTIM1 clock (LPTIM1CLK).
Definition: stm32f7xx_hal_rcc_ex.h:3068
assert_param
#define assert_param(expr)
Include module's header file.
Definition: stm32f407/stm32f407g-disc1/Inc/stm32f4xx_hal_conf.h:353
__HAL_RCC_UART7_CONFIG
#define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__)
Macro to configure the UART7 clock (UART7CLK).
Definition: stm32f7xx_hal_rcc_ex.h:3026
RCC_PLLI2SCFGR_PLLI2SN
#define RCC_PLLI2SCFGR_PLLI2SN
Definition: stm32f407xx.h:10348
__HAL_RCC_TIMCLKPRESCALER
#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__)
Macro to configure the Timers clocks prescalers.
Definition: stm32f7xx_hal_rcc_ex.h:2597
RCC_PeriphCLKInitTypeDef::PLLI2SDivQ
uint32_t PLLI2SDivQ
Definition: stm32f7xx_hal_rcc_ex.h:137
RCC_PLLI2SCFGR_PLLI2SN_Pos
#define RCC_PLLI2SCFGR_PLLI2SN_Pos
Definition: stm32f407xx.h:10346
RCC_DCKCFGR1_PLLSAIDIVR
#define RCC_DCKCFGR1_PLLSAIDIVR
Definition: stm32f769xx.h:12057
RCC_PERIPHCLK_USART6
#define RCC_PERIPHCLK_USART6
Definition: stm32f7xx_hal_rcc_ex.h:248
RCC_PeriphCLKInitTypeDef::Usart6ClockSelection
uint32_t Usart6ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:178
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG
#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__)
Macro to configure the SAI clock Divider coming from PLLI2S.
Definition: stm32f7xx_hal_rcc_ex.h:2697
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
__HAL_RCC_UART5_CONFIG
#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__)
Macro to configure the UART5 clock (UART5CLK).
Definition: stm32f7xx_hal_rcc_ex.h:2984
RCC_SAI1CLKSOURCE_PLLSAI
#define RCC_SAI1CLKSOURCE_PLLSAI
Definition: stm32f7xx_hal_rcc_ex.h:325
__HAL_RCC_GET_SDMMC1_SOURCE
#define __HAL_RCC_GET_SDMMC1_SOURCE()
macro to get the SDMMC1 clock source.
Definition: stm32f7xx_hal_rcc_ex.h:3129
RCC_PLLSAIInitTypeDef::PLLSAIN
uint32_t PLLSAIN
Definition: stm32f7xx_hal_rcc_ex.h:103
__HAL_RCC_CEC_CONFIG
#define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__)
Macro to configure the CEC clock (CECCLK).
Definition: stm32f7xx_hal_rcc_ex.h:3087
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#define RCC_PLLSOURCE_HSI
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:181
__HAL_RCC_PLLSAI_DISABLE
#define __HAL_RCC_PLLSAI_DISABLE()
Definition: stm32f7xx_hal_rcc_ex.h:2605
IS_RCC_PLLSAI_DIVQ_VALUE
#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE)
Definition: stm32f7xx_hal_rcc_ex.h:3371
RCC_DCKCFGR1_TIMPRE
#define RCC_DCKCFGR1_TIMPRE
Definition: stm32f769xx.h:12083
__HAL_RCC_SAI1_CONFIG
#define __HAL_RCC_SAI1_CONFIG(__SOURCE__)
Macro to configure SAI1 clock source selection.
Definition: stm32f7xx_hal_rcc_ex.h:2735
IS_RCC_UART7CLKSOURCE
#define IS_RCC_UART7CLKSOURCE(SOURCE)
Definition: stm32f7xx_hal_rcc_ex.h:3422
PWR
#define PWR
Definition: stm32f407xx.h:1083
HAL_RCCEx_GetPeriphCLKFreq
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
__HAL_RCC_GET_I2C4_SOURCE
#define __HAL_RCC_GET_I2C4_SOURCE()
macro to get the I2C4 clock source.
Definition: stm32f7xx_hal_rcc_ex.h:2889
RCC_PLLSAIInitTypeDef::PLLSAIP
uint32_t PLLSAIP
Definition: stm32f7xx_hal_rcc_ex.h:118
IS_RCC_PLLSAI_DIVR_VALUE
#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE)
Definition: stm32f7xx_hal_rcc_ex.h:3375
__HAL_RCC_I2C4_CONFIG
#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__)
Macro to configure the I2C4 clock (I2C4CLK).
Definition: stm32f7xx_hal_rcc_ex.h:2880
RCC_PeriphCLKInitTypeDef::Uart5ClockSelection
uint32_t Uart5ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:175
RCC_PERIPHCLK_SPDIFRX
#define RCC_PERIPHCLK_SPDIFRX
Definition: stm32f7xx_hal_rcc_ex.h:261
RCC_PeriphCLKInitTypeDef::Usart3ClockSelection
uint32_t Usart3ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:169
IS_RCC_USART6CLKSOURCE
#define IS_RCC_USART6CLKSOURCE(SOURCE)
Definition: stm32f7xx_hal_rcc_ex.h:3416
IS_RCC_TIMPRES
#define IS_RCC_TIMPRES(VALUE)
Definition: stm32f7xx_hal_rcc_ex.h:3458
RCC_FLAG_LSERDY
#define RCC_FLAG_LSERDY
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:355
RCC_PERIPHCLK_PLLI2S
#define RCC_PERIPHCLK_PLLI2S
Definition: stm32f7xx_hal_rcc_ex.h:262
RCC_PERIPHCLK_DFSDM1
#define RCC_PERIPHCLK_DFSDM1
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:434
IS_RCC_USART3CLKSOURCE
#define IS_RCC_USART3CLKSOURCE(SOURCE)
Definition: stm32f7xx_hal_rcc_ex.h:3398
RCC_PeriphCLKInitTypeDef::PeriphClockSelection
uint32_t PeriphClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:128
RCC_PERIPHCLK_UART7
#define RCC_PERIPHCLK_UART7
Definition: stm32f7xx_hal_rcc_ex.h:249
RCC_PeriphCLKInitTypeDef::Sdmmc1ClockSelection
uint32_t Sdmmc1ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:208
__HAL_RCC_PLLSAI_CONFIG
#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__)
Macro to configure the PLLSAI clock multiplication and division factors.
Definition: stm32f7xx_hal_rcc_ex.h:2661
IS_RCC_CECCLKSOURCE
#define IS_RCC_CECCLKSOURCE(SOURCE)
Definition: stm32f7xx_hal_rcc_ex.h:3385
RCC_CFGR_RTCPRE
#define RCC_CFGR_RTCPRE
Definition: stm32f407xx.h:9604
__HAL_RCC_GET_DFSDM1_SOURCE
#define __HAL_RCC_GET_DFSDM1_SOURCE()
Macro to get the DFSDM1 clock source.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3179
RCC_PERIPHCLK_I2S
#define RCC_PERIPHCLK_I2S
Definition: stm32f7xx_hal_rcc_ex.h:237
__HAL_RCC_I2C2_CONFIG
#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__)
Macro to configure the I2C2 clock (I2C2CLK).
Definition: stm32f7xx_hal_rcc_ex.h:2842
RCC_PLLI2SCFGR_PLLI2SQ
#define RCC_PLLI2SCFGR_PLLI2SQ
Definition: stm32f469xx.h:14551
HAL_GetTick
uint32_t HAL_GetTick(void)
Provides a tick value in millisecond.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:323
__HAL_RCC_GET_USART1_SOURCE
#define __HAL_RCC_GET_USART1_SOURCE()
macro to get the USART1 clock source.
Definition: stm32f7xx_hal_rcc_ex.h:2910
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#define RCC_PERIPHCLK_CLK48
Definition: stm32f7xx_hal_rcc_ex.h:258
RCC_PeriphCLKInitTypeDef::TIMPresSelection
uint32_t TIMPresSelection
Definition: stm32f7xx_hal_rcc_ex.h:154
RCC_PeriphCLKInitTypeDef::Usart1ClockSelection
uint32_t Usart1ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:163
__HAL_RCC_GET_UART7_SOURCE
#define __HAL_RCC_GET_UART7_SOURCE()
macro to get the UART7 clock source.
Definition: stm32f7xx_hal_rcc_ex.h:3036
RCC_PeriphCLKInitTypeDef::PLLI2S
RCC_PLLI2SInitTypeDef PLLI2S
Definition: stm32f7xx_hal_rcc_ex.h:131
RCC_DCKCFGR1_SAI1SEL_1
#define RCC_DCKCFGR1_SAI1SEL_1
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IS_RCC_UART4CLKSOURCE
#define IS_RCC_UART4CLKSOURCE(SOURCE)
Definition: stm32f7xx_hal_rcc_ex.h:3404
IS_RCC_PLLSAIR_VALUE
#define IS_RCC_PLLSAIR_VALUE(VALUE)
Definition: stm32f7xx_hal_rcc_ex.h:3369
RCC_PLLSAICFGR_PLLSAIQ_Pos
#define RCC_PLLSAICFGR_PLLSAIQ_Pos
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RCC_PeriphCLKInitTypeDef::PLLSAI
RCC_PLLSAIInitTypeDef PLLSAI
Definition: stm32f7xx_hal_rcc_ex.h:134
RCC_PLLCFGR_PLLSRC
#define RCC_PLLCFGR_PLLSRC
Definition: stm32f407xx.h:9516
HAL_OK
@ HAL_OK
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:42
RCC_PLLSAICFGR_PLLSAIP_Pos
#define RCC_PLLSAICFGR_PLLSAIP_Pos
Definition: stm32f469xx.h:14577
__HAL_RCC_CLK48_CONFIG
#define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__)
Macro to configure the CLK48 source (CLK48CLK).
Definition: stm32f7xx_hal_rcc_ex.h:3104
RCC_DCKCFGR1_SAI2SEL_0
#define RCC_DCKCFGR1_SAI2SEL_0
Definition: stm32f769xx.h:12078
__HAL_RCC_UART4_CONFIG
#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__)
Macro to configure the UART4 clock (UART4CLK).
Definition: stm32f7xx_hal_rcc_ex.h:2963
__HAL_RCC_GET_SAI1_SOURCE
#define __HAL_RCC_GET_SAI1_SOURCE()
Macro to get the SAI1 clock source.
Definition: stm32f7xx_hal_rcc_ex.h:2750
RCC_DCKCFGR1_PLLI2SDIVQ_Pos
#define RCC_DCKCFGR1_PLLI2SDIVQ_Pos
Definition: stm32f769xx.h:12037
HAL_RCCEx_DisablePLLI2S
HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
RCC_PLLI2SCFGR_PLLI2SR_Pos
#define RCC_PLLI2SCFGR_PLLI2SR_Pos
Definition: stm32f407xx.h:10359
__HAL_RCC_GET_I2C2_SOURCE
#define __HAL_RCC_GET_I2C2_SOURCE()
Macro to get the I2C2 clock source.
Definition: stm32f7xx_hal_rcc_ex.h:2851
__HAL_RCC_GET_USART2_SOURCE
#define __HAL_RCC_GET_USART2_SOURCE()
macro to get the USART2 clock source.
Definition: stm32f7xx_hal_rcc_ex.h:2931
RCC_PERIPHCLK_USART3
#define RCC_PERIPHCLK_USART3
Definition: stm32f7xx_hal_rcc_ex.h:245
IS_RCC_CLK48SOURCE
#define IS_RCC_CLK48SOURCE(SOURCE)
Definition: stm32f7xx_hal_rcc_ex.h:3455
RCC_PLLCFGR_PLLM
#define RCC_PLLCFGR_PLLM
Definition: stm32f407xx.h:9487
__HAL_RCC_GET_SAI2_SOURCE
#define __HAL_RCC_GET_SAI2_SOURCE()
Macro to get the SAI2 clock source.
Definition: stm32f7xx_hal_rcc_ex.h:2783
__HAL_RCC_PLLI2S_ENABLE
#define __HAL_RCC_PLLI2S_ENABLE()
Macros to enable or disable the PLLI2S.
Definition: stm32f7xx_hal_rcc.h:931
IS_RCC_PLLSAIP_VALUE
#define IS_RCC_PLLSAIP_VALUE(VALUE)
Definition: stm32f7xx_hal_rcc_ex.h:3364
IS_RCC_UART8CLKSOURCE
#define IS_RCC_UART8CLKSOURCE(SOURCE)
Definition: stm32f7xx_hal_rcc_ex.h:3428
RCC_PLLSAICFGR_PLLSAIN_Pos
#define RCC_PLLSAICFGR_PLLSAIN_Pos
Definition: stm32f469xx.h:14564
RCC_PeriphCLKInitTypeDef::PLLSAIDivQ
uint32_t PLLSAIDivQ
Definition: stm32f7xx_hal_rcc_ex.h:141
RCC_CLK48SOURCE_PLLSAIP
#define RCC_CLK48SOURCE_PLLSAIP
Definition: stm32f7xx_hal_rcc_ex.h:502
HAL_RCCEx_DisablePLLSAI
HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void)
HSI_VALUE
#define HSI_VALUE
Internal High Speed oscillator (HSI) value. This value is used by the RCC HAL module to compute the s...
Definition: stm32f407/stm32f407g-disc1/Inc/stm32f4xx_hal_conf.h:82
RCC_SAI1CLKSOURCE_PLLI2S
#define RCC_SAI1CLKSOURCE_PLLI2S
Definition: stm32f7xx_hal_rcc_ex.h:326
RCC_CR_PLLI2SRDY
#define RCC_CR_PLLI2SRDY
Definition: stm32f407xx.h:9482
RCC_PERIPHCLK_UART5
#define RCC_PERIPHCLK_UART5
Definition: stm32f7xx_hal_rcc_ex.h:247
RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection
uint32_t Lptim1ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:199
RCC_SAI2CLKSOURCE_PLLSAI
#define RCC_SAI2CLKSOURCE_PLLSAI
Definition: stm32f7xx_hal_rcc_ex.h:338
__HAL_RCC_I2S_CONFIG
#define __HAL_RCC_I2S_CONFIG(__SOURCE__)
Macro to configure the I2S clock source (I2SCLK).
Definition: stm32f7xx_hal_rcc.h:924
__HAL_RCC_GET_CEC_SOURCE
#define __HAL_RCC_GET_CEC_SOURCE()
macro to get the CEC clock source.
Definition: stm32f7xx_hal_rcc_ex.h:3095
RCC_PeriphCLKInitTypeDef::Sai2ClockSelection
uint32_t Sai2ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:160
__HAL_RCC_PLLSAI_ENABLE
#define __HAL_RCC_PLLSAI_ENABLE()
Macros to Enable or Disable the PLLISAI.
Definition: stm32f7xx_hal_rcc_ex.h:2604
IS_RCC_I2C3CLKSOURCE
#define IS_RCC_I2C3CLKSOURCE(SOURCE)
Definition: stm32f7xx_hal_rcc_ex.h:3442
RCC_TIMPRES_ACTIVATED
#define RCC_TIMPRES_ACTIVATED
Definition: stm32f7xx_hal_rcc_ex.h:511
RCC_PLLI2SInitTypeDef::PLLI2SN
uint32_t PLLI2SN
Definition: stm32f7xx_hal_rcc_ex.h:78
__HAL_RCC_BACKUPRESET_RELEASE
#define __HAL_RCC_BACKUPRESET_RELEASE()
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:1021
RCC_PeriphCLKInitTypeDef::Dfsdm1ClockSelection
uint32_t Dfsdm1ClockSelection
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:205
IS_RCC_PLLI2SN_VALUE
#define IS_RCC_PLLI2SN_VALUE(VALUE)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:6878
RCC_PERIPHCLK_UART8
#define RCC_PERIPHCLK_UART8
Definition: stm32f7xx_hal_rcc_ex.h:250
RESET
@ RESET
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:187
IS_RCC_LPTIM1CLK
#define IS_RCC_LPTIM1CLK(SOURCE)
Definition: stm32f7xx_hal_rcc_ex.h:3450
EXTERNAL_CLOCK_VALUE
#define EXTERNAL_CLOCK_VALUE
External clock source for I2S peripheral This value is used by the I2S HAL module to compute the I2S ...
Definition: stm32f407/stm32f407g-disc1/Inc/stm32f4xx_hal_conf.h:110
IS_RCC_I2SCLKSOURCE
#define IS_RCC_I2SCLKSOURCE(SOURCE)
Definition: stm32f7xx_hal_rcc_ex.h:3379
RCC_PERIPHCLK_I2C3
#define RCC_PERIPHCLK_I2C3
Definition: stm32f7xx_hal_rcc_ex.h:253
RCC_PeriphCLKInitTypeDef::I2c1ClockSelection
uint32_t I2c1ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:187
RCC_TIMPRES_DESACTIVATED
#define RCC_TIMPRES_DESACTIVATED
Definition: stm32f7xx_hal_rcc_ex.h:510
IS_RCC_PLLI2SR_VALUE
#define IS_RCC_PLLI2SR_VALUE(VALUE)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:6913
__HAL_RCC_USART2_CONFIG
#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__)
Macro to configure the USART2 clock (USART2CLK).
Definition: stm32f7xx_hal_rcc_ex.h:2921
IS_RCC_I2C2CLKSOURCE
#define IS_RCC_I2C2CLKSOURCE(SOURCE)
Definition: stm32f7xx_hal_rcc_ex.h:3437
RCC_PERIPHCLK_I2C1
#define RCC_PERIPHCLK_I2C1
Definition: stm32f7xx_hal_rcc_ex.h:251
PWR_CR1_DBP
#define PWR_CR1_DBP
Definition: stm32f769xx.h:10473
__HAL_RCC_GET_I2C1_SOURCE
#define __HAL_RCC_GET_I2C1_SOURCE()
Macro to get the I2C1 clock source.
Definition: stm32f7xx_hal_rcc_ex.h:2832
__HAL_RCC_GET_UART4_SOURCE
#define __HAL_RCC_GET_UART4_SOURCE()
macro to get the UART4 clock source.
Definition: stm32f7xx_hal_rcc_ex.h:2973
IS_RCC_I2C4CLKSOURCE
#define IS_RCC_I2C4CLKSOURCE(SOURCE)
Definition: stm32f7xx_hal_rcc_ex.h:3446
RCC_DCKCFGR1_PLLSAIDIVQ_Pos
#define RCC_DCKCFGR1_PLLSAIDIVQ_Pos
Definition: stm32f769xx.h:12046
RCC_PERIPHCLK_SAI2
#define RCC_PERIPHCLK_SAI2
Definition: stm32f7xx_hal_rcc_ex.h:257
RCC_PLLI2SInitTypeDef::PLLI2SR
uint32_t PLLI2SR
Definition: stm32f7xx_hal_rcc_ex.h:82
RCC_PERIPHCLK_UART4
#define RCC_PERIPHCLK_UART4
Definition: stm32f7xx_hal_rcc_ex.h:246
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:216
RCC_PERIPHCLK_I2C4
#define RCC_PERIPHCLK_I2C4
Definition: stm32f7xx_hal_rcc_ex.h:254
RCC_PLLI2SInitTypeDef
PLLI2S Clock structure definition.
Definition: stm32f7xx_hal_rcc_ex.h:76
RCC_PERIPHCLK_USART1
#define RCC_PERIPHCLK_USART1
Definition: stm32f7xx_hal_rcc_ex.h:243
RCC_PLLI2SCFGR_PLLI2SQ_Pos
#define RCC_PLLI2SCFGR_PLLI2SQ_Pos
Definition: stm32f469xx.h:14549
__HAL_RCC_GET_I2SCLKSOURCE
#define __HAL_RCC_GET_I2SCLKSOURCE()
Macro to Get I2S clock source selection.
Definition: stm32f7xx_hal_rcc_ex.h:2813
__HAL_RCC_I2C3_CONFIG
#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__)
Macro to configure the I2C3 clock (I2C3CLK).
Definition: stm32f7xx_hal_rcc_ex.h:2861
RCC_DCKCFGR1_PLLSAIDIVR_Pos
#define RCC_DCKCFGR1_PLLSAIDIVR_Pos
Definition: stm32f769xx.h:12055
RCC_DCKCFGR1_SAI1SEL_0
#define RCC_DCKCFGR1_SAI1SEL_0
Definition: stm32f769xx.h:12068
RCC_PeriphCLKInitTypeDef::CecClockSelection
uint32_t CecClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:202
RCC_LSE_TIMEOUT_VALUE
#define RCC_LSE_TIMEOUT_VALUE
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:1336
RCC_PeriphCLKInitTypeDef::I2c3ClockSelection
uint32_t I2c3ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:193
RCC_PeriphCLKInitTypeDef::Clk48ClockSelection
uint32_t Clk48ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:205
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG
#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__)
Macro to configure the SAI clock Divider coming from PLLSAI.
Definition: stm32f7xx_hal_rcc_ex.h:2705
IS_RCC_PLLSAIQ_VALUE
#define IS_RCC_PLLSAIQ_VALUE(VALUE)
Definition: stm32f7xx_hal_rcc_ex.h:3368
__HAL_RCC_GET_I2C3_SOURCE
#define __HAL_RCC_GET_I2C3_SOURCE()
macro to get the I2C3 clock source.
Definition: stm32f7xx_hal_rcc_ex.h:2870
RCC_PERIPHCLK_USART2
#define RCC_PERIPHCLK_USART2
Definition: stm32f7xx_hal_rcc_ex.h:244
RCC_PLLSAIInitTypeDef::PLLSAIQ
uint32_t PLLSAIQ
Definition: stm32f7xx_hal_rcc_ex.h:107
RCC_PLLI2SCFGR_PLLI2SP
#define RCC_PLLI2SCFGR_PLLI2SP
Definition: stm32f769xx.h:11987
RCC
#define RCC
Definition: stm32f407xx.h:1113
__HAL_RCC_PWR_CLK_ENABLE
#define __HAL_RCC_PWR_CLK_ENABLE()
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:512
HAL_TIMEOUT
@ HAL_TIMEOUT
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:45
RCC_PERIPHCLK_CEC
#define RCC_PERIPHCLK_CEC
Definition: stm32f7xx_hal_rcc_ex.h:259
IS_RCC_USART2CLKSOURCE
#define IS_RCC_USART2CLKSOURCE(SOURCE)
Definition: stm32f7xx_hal_rcc_ex.h:3393
RCC_PeriphCLKInitTypeDef::Uart7ClockSelection
uint32_t Uart7ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:181
IS_RCC_PLLI2S_DIVQ_VALUE
#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE)
Definition: stm32f7xx_hal_rcc_ex.h:3373
RCC_PeriphCLKInitTypeDef::I2c4ClockSelection
uint32_t I2c4ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:196
RCC_PLLSAIInitTypeDef
PLLSAI Clock structure definition.
Definition: stm32f7xx_hal_rcc_ex.h:101
__HAL_RCC_GET_USART3_SOURCE
#define __HAL_RCC_GET_USART3_SOURCE()
macro to get the USART3 clock source.
Definition: stm32f7xx_hal_rcc_ex.h:2952
RCC_PERIPHCLK_SAI1
#define RCC_PERIPHCLK_SAI1
Definition: stm32f7xx_hal_rcc_ex.h:256
RCC_PLLSAICFGR_PLLSAIR_Pos
#define RCC_PLLSAICFGR_PLLSAIR_Pos
Definition: stm32f469xx.h:14591
IS_RCC_PLLI2SQ_VALUE
#define IS_RCC_PLLI2SQ_VALUE(VALUE)
Definition: stm32f7xx_hal_rcc_ex.h:3360
RCC_PLLI2SCFGR_PLLI2SP_Pos
#define RCC_PLLI2SCFGR_PLLI2SP_Pos
Definition: stm32f769xx.h:11985
__HAL_RCC_USART6_CONFIG
#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__)
Macro to configure the USART6 clock (USART6CLK).
Definition: stm32f7xx_hal_rcc_ex.h:3005
RCC_PLLSAICFGR_PLLSAIP
#define RCC_PLLSAICFGR_PLLSAIP
Definition: stm32f469xx.h:14579
RCC_DCKCFGR1_SAI2SEL_1
#define RCC_DCKCFGR1_SAI2SEL_1
Definition: stm32f769xx.h:12079
RCC_PLLI2SCFGR_PLLI2SR
#define RCC_PLLI2SCFGR_PLLI2SR
Definition: stm32f407xx.h:10361
__HAL_RCC_USART1_CONFIG
#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__)
Macro to configure the USART1 clock (USART1CLK).
Definition: stm32f7xx_hal_rcc_ex.h:2900
RCC_PLLSAICFGR_PLLSAIN
#define RCC_PLLSAICFGR_PLLSAIN
Definition: stm32f469xx.h:14566
HAL_RCCEx_PeriphCLKConfig
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
__HAL_RCC_GET_FLAG
#define __HAL_RCC_GET_FLAG(__FLAG__)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:1230
RCC_DCKCFGR1_SAI2SEL
#define RCC_DCKCFGR1_SAI2SEL
Definition: stm32f769xx.h:12077
RCC_PERIPHCLK_TIM
#define RCC_PERIPHCLK_TIM
Definition: stm32f7xx_hal_rcc_ex.h:241
RCC_BDCR_LSEON
#define RCC_BDCR_LSEON
Definition: stm32f407xx.h:10275
RCC_FLAG_PLLI2SRDY
#define RCC_FLAG_PLLI2SRDY
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:352
__HAL_RCC_GET_CLK48_SOURCE
#define __HAL_RCC_GET_CLK48_SOURCE()
macro to get the CLK48 source.
Definition: stm32f7xx_hal_rcc_ex.h:3112
RCC_PeriphCLKInitTypeDef::Sai1ClockSelection
uint32_t Sai1ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:157
RCC_PeriphCLKInitTypeDef::Uart8ClockSelection
uint32_t Uart8ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:184
IS_RCC_UART5CLKSOURCE
#define IS_RCC_UART5CLKSOURCE(SOURCE)
Definition: stm32f7xx_hal_rcc_ex.h:3410
__HAL_RCC_GET_UART5_SOURCE
#define __HAL_RCC_GET_UART5_SOURCE()
macro to get the UART5 clock source.
Definition: stm32f7xx_hal_rcc_ex.h:2994
RCC_I2SCLKSOURCE_PLLI2S
#define RCC_I2SCLKSOURCE_PLLI2S
Definition: stm32f7xx_hal_rcc_ex.h:315
RCC_PeriphCLKInitTypeDef::PLLSAIDivR
uint32_t PLLSAIDivR
Definition: stm32f7xx_hal_rcc_ex.h:145
__HAL_RCC_GET_USART6_SOURCE
#define __HAL_RCC_GET_USART6_SOURCE()
macro to get the USART6 clock source.
Definition: stm32f7xx_hal_rcc_ex.h:3015
RCC_DCKCFGR1_PLLSAIDIVQ
#define RCC_DCKCFGR1_PLLSAIDIVQ
Definition: stm32f769xx.h:12048
RCC_PLLSAICFGR_PLLSAIQ
#define RCC_PLLSAICFGR_PLLSAIQ
Definition: stm32f469xx.h:14585
IS_RCC_PLLSAIN_VALUE
#define IS_RCC_PLLSAIN_VALUE(VALUE)
Definition: stm32f7xx_hal_rcc_ex.h:3363
__HAL_RCC_USART3_CONFIG
#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__)
Macro to configure the USART3 clock (USART3CLK).
Definition: stm32f7xx_hal_rcc_ex.h:2942
RCC_DCKCFGR1_SAI1SEL
#define RCC_DCKCFGR1_SAI1SEL
Definition: stm32f769xx.h:12067
RCC_DBP_TIMEOUT_VALUE
#define RCC_DBP_TIMEOUT_VALUE
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:1335
__HAL_RCC_BACKUPRESET_FORCE
#define __HAL_RCC_BACKUPRESET_FORCE()
Macros to force or release the Backup domain reset.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:1020
RCC_PeriphCLKInitTypeDef::Usart2ClockSelection
uint32_t Usart2ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:166
__HAL_RCC_PLLI2S_CONFIG
#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__)
Macro to configure the PLLI2S clock multiplication and division factors .
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:5914
RCC_PERIPHCLK_LPTIM1
#define RCC_PERIPHCLK_LPTIM1
Definition: stm32f7xx_hal_rcc_ex.h:255
RCC_PERIPHCLK_RTC
#define RCC_PERIPHCLK_RTC
Definition: stm32f7xx_hal_rcc_ex.h:242
HSE_VALUE
#define HSE_VALUE
Adjust the value of External High Speed oscillator (HSE) used in your application....
Definition: stm32f407/stm32f407g-disc1/Inc/stm32f4xx_hal_conf.h:69
HAL_RCCEx_EnablePLLI2S
HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)
RCC_PERIPHCLK_I2C2
#define RCC_PERIPHCLK_I2C2
Definition: stm32f7xx_hal_rcc_ex.h:252
__HAL_RCC_GET_UART8_SOURCE
#define __HAL_RCC_GET_UART8_SOURCE()
macro to get the UART8 clock source.
Definition: stm32f7xx_hal_rcc_ex.h:3057
PLLI2S_TIMEOUT_VALUE
#define PLLI2S_TIMEOUT_VALUE
Definition: stm32f7xx_hal_rcc.h:1182
__HAL_RCC_SDMMC1_CONFIG
#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__)
Macro to configure the SDMMC1 clock (SDMMC1CLK).
Definition: stm32f7xx_hal_rcc_ex.h:3121
RCC_PLLI2SInitTypeDef::PLLI2SQ
uint32_t PLLI2SQ
Definition: stm32f7xx_hal_rcc_ex.h:86
HAL_IS_BIT_SET
#define HAL_IS_BIT_SET(REG, BIT)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:63
RCC_BDCR_RTCSEL
#define RCC_BDCR_RTCSEL
Definition: stm32f407xx.h:10285
RCC_SAI2CLKSOURCE_PLLI2S
#define RCC_SAI2CLKSOURCE_PLLI2S
Definition: stm32f7xx_hal_rcc_ex.h:339
RCC_PeriphCLKInitTypeDef::I2sClockSelection
uint32_t I2sClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:151
RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition.
Definition: stm32f7xx_hal_rcc_ex.h:126
__HAL_RCC_UART8_CONFIG
#define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__)
Macro to configure the UART8 clock (UART8CLK).
Definition: stm32f7xx_hal_rcc_ex.h:3047
IS_RCC_RTCCLKSOURCE
#define IS_RCC_RTCCLKSOURCE(__SOURCE__)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:1381
__HAL_RCC_GET_LPTIM1_SOURCE
#define __HAL_RCC_GET_LPTIM1_SOURCE()
macro to get the LPTIM1 clock source.
Definition: stm32f7xx_hal_rcc_ex.h:3078
__HAL_RCC_PLLI2S_DISABLE
#define __HAL_RCC_PLLI2S_DISABLE()
Definition: stm32f7xx_hal_rcc.h:932
__HAL_RCC_RTC_CONFIG
#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:994
__HAL_RCC_SAI2_CONFIG
#define __HAL_RCC_SAI2_CONFIG(__SOURCE__)
Macro to configure SAI2 clock source selection.
Definition: stm32f7xx_hal_rcc_ex.h:2767
RCC_PeriphCLKInitTypeDef::I2c2ClockSelection
uint32_t I2c2ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:190
RCC_PeriphCLKInitTypeDef::Uart4ClockSelection
uint32_t Uart4ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:172
IS_RCC_USART1CLKSOURCE
#define IS_RCC_USART1CLKSOURCE(SOURCE)
Definition: stm32f7xx_hal_rcc_ex.h:3387
__HAL_RCC_PLLSAI_GET_FLAG
#define __HAL_RCC_PLLSAI_GET_FLAG()
Check PLLSAI RDY flag is set or not.
Definition: stm32f7xx_hal_rcc_ex.h:2806
__HAL_RCC_DFSDM1_CONFIG
#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__)
Macro to configure the DFSDM1 clock.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3167
IS_RCC_SDMMC1CLKSOURCE
#define IS_RCC_SDMMC1CLKSOURCE(SOURCE)
Definition: stm32f7xx_hal_rcc_ex.h:3382
PLLSAI_TIMEOUT_VALUE
#define PLLSAI_TIMEOUT_VALUE
Definition: stm32f7xx_hal_rcc.h:1183
IS_RCC_DFSDM1CLKSOURCE
#define IS_RCC_DFSDM1CLKSOURCE(SOURCE)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4398
RCC_DCKCFGR1_PLLI2SDIVQ
#define RCC_DCKCFGR1_PLLI2SDIVQ
Definition: stm32f769xx.h:12039
HAL_RCCEx_EnablePLLSAI
HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit)
stm32f7xx_hal.h
This file contains all the functions prototypes for the HAL module driver.
HAL_RCCEx_GetPeriphCLKConfig
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
RCC_PLLSAICFGR_PLLSAIR
#define RCC_PLLSAICFGR_PLLSAIR
Definition: stm32f469xx.h:14593
RCC_PeriphCLKInitTypeDef::RTCClockSelection
uint32_t RTCClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:148
RCC_PERIPHCLK_SDMMC1
#define RCC_PERIPHCLK_SDMMC1
Definition: stm32f7xx_hal_rcc_ex.h:260

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autogenerated on Fri Apr 1 2022 02:14:53