stm32f7xx_hal_rcc.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32F7xx_HAL_RCC_H
22 #define __STM32F7xx_HAL_RCC_H
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f7xx_hal_def.h"
30 
31 /* Include RCC HAL Extended module */
32 /* (include on top of file since RCC structures are defined in extended file) */
33 #include "stm32f7xx_hal_rcc_ex.h"
34 
43 /* Exported types ------------------------------------------------------------*/
44 
52 typedef struct
53 {
54  uint32_t OscillatorType;
57  uint32_t HSEState;
60  uint32_t LSEState;
63  uint32_t HSIState;
66  uint32_t HSICalibrationValue;
69  uint32_t LSIState;
72  RCC_PLLInitTypeDef PLL;
74 }RCC_OscInitTypeDef;
75 
79 typedef struct
80 {
81  uint32_t ClockType;
84  uint32_t SYSCLKSource;
87  uint32_t AHBCLKDivider;
90  uint32_t APB1CLKDivider;
93  uint32_t APB2CLKDivider;
96 }RCC_ClkInitTypeDef;
97 
102 /* Exported constants --------------------------------------------------------*/
110 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U)
111 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U)
112 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U)
113 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U)
114 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U)
115 
122 #define RCC_HSE_OFF ((uint32_t)0x00000000U)
123 #define RCC_HSE_ON RCC_CR_HSEON
124 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
125 
132 #define RCC_LSE_OFF ((uint32_t)0x00000000U)
133 #define RCC_LSE_ON RCC_BDCR_LSEON
134 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
135 
142 #define RCC_HSI_OFF ((uint32_t)0x00000000U)
143 #define RCC_HSI_ON RCC_CR_HSION
144 
145 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */
146 
153 #define RCC_LSI_OFF ((uint32_t)0x00000000U)
154 #define RCC_LSI_ON RCC_CSR_LSION
155 
162 #define RCC_PLL_NONE ((uint32_t)0x00000000U)
163 #define RCC_PLL_OFF ((uint32_t)0x00000001U)
164 #define RCC_PLL_ON ((uint32_t)0x00000002U)
165 
172 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002U)
173 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004U)
174 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006U)
175 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008U)
176 
183 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
184 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
185 
192 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U)
193 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U)
194 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U)
195 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U)
196 
203 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
204 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
205 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
206 
214 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
215 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
216 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
224 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
225 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
226 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
227 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
228 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
229 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
230 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
231 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
232 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
233 
240 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
241 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
242 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
243 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
244 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
245 
252 #define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U)
253 #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U)
254 #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U)
255 #define RCC_RTCCLKSOURCE_HSE_DIVX ((uint32_t)0x00000300U)
256 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U)
257 #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U)
258 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U)
259 #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U)
260 #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U)
261 #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U)
262 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U)
263 #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U)
264 #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U)
265 #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U)
266 #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U)
267 #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U)
268 #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U)
269 #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U)
270 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U)
271 #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U)
272 #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U)
273 #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U)
274 #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U)
275 #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U)
276 #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U)
277 #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U)
278 #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U)
279 #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U)
280 #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U)
281 #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U)
282 #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U)
283 #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U)
284 #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U)
285 #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U)
286 
295 #define RCC_MCO1 ((uint32_t)0x00000000U)
296 #define RCC_MCO2 ((uint32_t)0x00000001U)
297 
304 #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U)
305 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
306 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
307 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
308 
315 #define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U)
316 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
317 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
318 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
319 
326 #define RCC_MCODIV_1 ((uint32_t)0x00000000U)
327 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
328 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
329 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
330 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
331 
338 #define RCC_IT_LSIRDY ((uint8_t)0x01U)
339 #define RCC_IT_LSERDY ((uint8_t)0x02U)
340 #define RCC_IT_HSIRDY ((uint8_t)0x04U)
341 #define RCC_IT_HSERDY ((uint8_t)0x08U)
342 #define RCC_IT_PLLRDY ((uint8_t)0x10U)
343 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20U)
344 #define RCC_IT_PLLSAIRDY ((uint8_t)0x40U)
345 #define RCC_IT_CSS ((uint8_t)0x80U)
346 
359 /* Flags in the CR register */
360 #define RCC_FLAG_HSIRDY ((uint8_t)0x21U)
361 #define RCC_FLAG_HSERDY ((uint8_t)0x31U)
362 #define RCC_FLAG_PLLRDY ((uint8_t)0x39U)
363 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU)
364 #define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3CU)
365 
366 /* Flags in the BDCR register */
367 #define RCC_FLAG_LSERDY ((uint8_t)0x41U)
368 
369 /* Flags in the CSR register */
370 #define RCC_FLAG_LSIRDY ((uint8_t)0x61U)
371 #define RCC_FLAG_BORRST ((uint8_t)0x79U)
372 #define RCC_FLAG_PINRST ((uint8_t)0x7AU)
373 #define RCC_FLAG_PORRST ((uint8_t)0x7BU)
374 #define RCC_FLAG_SFTRST ((uint8_t)0x7CU)
375 #define RCC_FLAG_IWDGRST ((uint8_t)0x7DU)
376 #define RCC_FLAG_WWDGRST ((uint8_t)0x7EU)
377 #define RCC_FLAG_LPWRRST ((uint8_t)0x7FU)
378 
385 #define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U)
386 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1
387 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0
388 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
389 
397 /* Exported macro ------------------------------------------------------------*/
409 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
410  __IO uint32_t tmpreg; \
411  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
412  /* Delay after an RCC peripheral clock enabling */ \
413  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
414  UNUSED(tmpreg); \
415  } while(0)
416 
417 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
418  __IO uint32_t tmpreg; \
419  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
420  /* Delay after an RCC peripheral clock enabling */ \
421  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
422  UNUSED(tmpreg); \
423  } while(0)
424 
425 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
426 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
427 
439 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
440  __IO uint32_t tmpreg; \
441  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
442  /* Delay after an RCC peripheral clock enabling */ \
443  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
444  UNUSED(tmpreg); \
445  } while(0)
446 
447 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
448  __IO uint32_t tmpreg; \
449  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
450  /* Delay after an RCC peripheral clock enabling */ \
451  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
452  UNUSED(tmpreg); \
453  } while(0)
454 
455 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
456 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
457 
468 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
469  __IO uint32_t tmpreg; \
470  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
471  /* Delay after an RCC peripheral clock enabling */ \
472  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
473  UNUSED(tmpreg); \
474  } while(0)
475 
476 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
477 
489 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
490 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET)
491 
492 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
493 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET)
494 
505 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
506 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
507 
508 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
509 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
510 
521 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
522 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
523 
531 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
532 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
533 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
534 
535 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
536 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
537 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
538 
546 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
547 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
548 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
549 
550 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
551 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
552 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
553 
561 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
562 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
563 
564 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
565 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
566 
578 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
579 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
580 
581 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
582 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
583 
590 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
591 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
592 
593 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
594 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
595 
602 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
603 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
604 
617 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET)
618 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET)
619 
620 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET)
621 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET)
622 
634 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET)
635 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET)
636 
637 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET)
638 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET)
639 
651 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET)
652 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET)
653 
675 #define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION))
676 #define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION))
677 
684 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\
685  RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_CR_HSITRIM_Pos))
686 
702 #define __HAL_RCC_LSI_ENABLE() (RCC->CSR |= (RCC_CSR_LSION))
703 #define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION))
704 
733 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
734  do { \
735  if ((__STATE__) == RCC_HSE_ON) \
736  { \
737  SET_BIT(RCC->CR, RCC_CR_HSEON); \
738  } \
739  else if ((__STATE__) == RCC_HSE_OFF) \
740  { \
741  CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
742  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
743  } \
744  else if ((__STATE__) == RCC_HSE_BYPASS) \
745  { \
746  SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
747  SET_BIT(RCC->CR, RCC_CR_HSEON); \
748  } \
749  else \
750  { \
751  CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
752  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
753  } \
754  } while(0)
755 
781 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
782  do { \
783  if((__STATE__) == RCC_LSE_ON) \
784  { \
785  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
786  } \
787  else if((__STATE__) == RCC_LSE_OFF) \
788  { \
789  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
790  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
791  } \
792  else if((__STATE__) == RCC_LSE_BYPASS) \
793  { \
794  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
795  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
796  } \
797  else \
798  { \
799  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
800  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
801  } \
802  } while(0)
803 
814 #define __HAL_RCC_RTC_ENABLE() (RCC->BDCR |= (RCC_BDCR_RTCEN))
815 #define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN))
816 
839 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
840  MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
841 
842 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
843  RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \
844  } while (0)
845 
853 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
854 
861 #define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)
862 
868 #define __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR |= (RCC_BDCR_BDRST))
869 #define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST))
870 
885 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
886 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
887 
896 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
897 
907 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
908 
924 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \
925  RCC->CFGR |= (__SOURCE__); \
926  }while(0)
927 
931 #define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON))
932 #define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON))
933 
948 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
949 
957 #define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)
958 
973 #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \
974  (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
975 
982 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
983 
1007 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1008  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
1009 
1026 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1027  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3)));
1028 
1048 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
1049 
1061 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
1062 
1075 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
1076 
1089 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
1090 
1094 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
1095 
1114 #define RCC_FLAG_MASK ((uint8_t)0x1F)
1115 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
1116 
1125 /* Include RCC HAL Extension module */
1126 #include "stm32f7xx_hal_rcc_ex.h"
1127 
1128 /* Exported functions --------------------------------------------------------*/
1136 /* Initialization and de-initialization functions ******************************/
1137 HAL_StatusTypeDef HAL_RCC_DeInit(void);
1138 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1139 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
1147 /* Peripheral Control functions ************************************************/
1148 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
1149 void HAL_RCC_EnableCSS(void);
1150 void HAL_RCC_DisableCSS(void);
1151 uint32_t HAL_RCC_GetSysClockFreq(void);
1152 uint32_t HAL_RCC_GetHCLKFreq(void);
1153 uint32_t HAL_RCC_GetPCLK1Freq(void);
1154 uint32_t HAL_RCC_GetPCLK2Freq(void);
1155 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1156 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
1157 
1158 /* CSS NMI IRQ handler */
1159 void HAL_RCC_NMI_IRQHandler(void);
1160 
1161 /* User Callbacks in non blocking mode (IT mode) */
1162 void HAL_RCC_CSSCallback(void);
1171 /* Private types -------------------------------------------------------------*/
1172 /* Private variables ---------------------------------------------------------*/
1173 /* Private constants ---------------------------------------------------------*/
1177 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
1178 #define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
1179 #define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
1180 #define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
1181 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
1182 #define PLLI2S_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */
1183 #define PLLSAI_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */
1184 
1189 /* CIR register byte 2 (Bits[15:8]) base address */
1190 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
1191 
1192 /* CIR register byte 3 (Bits[23:16]) base address */
1193 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
1194 
1195 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
1196 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
1197 
1204 /* Private macros ------------------------------------------------------------*/
1212 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
1213 
1214 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
1215  ((HSE) == RCC_HSE_BYPASS))
1216 
1217 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
1218  ((LSE) == RCC_LSE_BYPASS))
1219 
1220 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
1221 
1222 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
1223 
1224 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
1225 
1226 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
1227  ((SOURCE) == RCC_PLLSOURCE_HSE))
1228 
1229 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
1230  ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
1231  ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
1232 #define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
1233 
1234 #define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
1235 
1236 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \
1237  ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8))
1238 #define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
1239 
1240 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
1241  ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
1242  ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
1243  ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
1244  ((HCLK) == RCC_SYSCLK_DIV512))
1245 
1246 #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
1247 
1248 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
1249  ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
1250  ((PCLK) == RCC_HCLK_DIV16))
1251 
1252 #define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2))
1253 
1254 
1255 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
1256  ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
1257 
1258 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
1259  ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
1260 
1261 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
1262  ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
1263  ((DIV) == RCC_MCODIV_5))
1264 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
1265 
1266 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
1267  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
1268  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
1269  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
1270  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
1271  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
1272  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
1273  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
1274  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
1275  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
1276  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
1277  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
1278  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
1279  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
1280  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
1281  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31))
1282 
1283 
1284 #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || \
1285  ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \
1286  ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \
1287  ((DRIVE) == RCC_LSEDRIVE_HIGH))
1288 
1304 #ifdef __cplusplus
1305 }
1306 #endif
1307 
1308 #endif /* __STM32F7xx_HAL_RCC_H */
1309 
1310 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
stm32f7xx_hal_rcc_ex.h
Header file of RCC HAL Extension module.
HAL_RCC_GetOscConfig
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
HAL_RCC_CSSCallback
void HAL_RCC_CSSCallback(void)
RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:77
RCC_PLLInitTypeDef
RCC PLL configuration structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:47
RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:51
HAL_RCC_GetPCLK2Freq
uint32_t HAL_RCC_GetPCLK2Freq(void)
HAL_RCC_GetClockConfig
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
HAL_RCC_NMI_IRQHandler
void HAL_RCC_NMI_IRQHandler(void)
HAL_RCC_DeInit
HAL_StatusTypeDef HAL_RCC_DeInit(void)
HAL_RCC_ClockConfig
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
HAL_RCC_OscConfig
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
HAL_RCC_DisableCSS
void HAL_RCC_DisableCSS(void)
HAL_RCC_MCOConfig
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
HAL_RCC_GetHCLKFreq
uint32_t HAL_RCC_GetHCLKFreq(void)
HAL_RCC_GetPCLK1Freq
uint32_t HAL_RCC_GetPCLK1Freq(void)
stm32f7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_RCC_GetSysClockFreq
uint32_t HAL_RCC_GetSysClockFreq(void)
HAL_RCC_EnableCSS
void HAL_RCC_EnableCSS(void)

picovoice_driver
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autogenerated on Fri Apr 1 2022 02:14:53