Collaboration diagram for RCCEx Exported Macros:
Modules | |
| RCCEx_Peripheral_Clock_Enable_Disable | |
| Enables or disables the AHB/APB peripheral clock. | |
| Peripheral Clock Enable Disable Status | |
| Get the enable or disable status of the AHB/APB peripheral clock. | |
| RCCEx Force Release Peripheral Reset | |
| Forces or releases AHB/APB peripheral reset. | |
| RCCEx Peripheral Clock Sleep Enable Disable | |
| Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode. | |
| AHB/APB Peripheral Clock Sleep Enable Disable Status | |
| Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode. | |
| RCCEx CRS Extended Features | |
Macros | |
| #define | __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__)) |
| Macro to configure the ADC clock. More... | |
| #define | __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__)) |
| Macro to configure the ADC clock. More... | |
| #define | __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__)) |
| Macro to configure the CEC clock (CECCLK). More... | |
| #define | __HAL_RCC_CEC_CONFIG(__CECCLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__)) |
| macro to configure the CEC clock (CECCLK). More... | |
| #define | __HAL_RCC_CEC_CONFIG(__CECCLKSource__) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__)) |
| macro to configure the CEC clock (CECCLK). More... | |
| #define | __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__)) |
| Macro to configure the CLK48 source (CLK48CLK). More... | |
| #define | __HAL_RCC_CLKP_CONFIG(__CLKPSource__) MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__)) |
| Macro to configure the CLKP : Oscillator clock for peripheral. More... | |
| #define | __HAL_RCC_CLKP_CONFIG(__CLKPSource__) MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__)) |
| Macro to configure the CLKP : Oscillator clock for peripheral. More... | |
| #define | __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) |
| #define | __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) |
| #define | __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) |
| #define | __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) |
| #define | __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) |
| Disable the specified CRS interrupts. More... | |
| #define | __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) |
| Disable the specified CRS interrupts. More... | |
| #define | __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) |
| Enable the specified CRS interrupts. More... | |
| #define | __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) |
| Enable the specified CRS interrupts. More... | |
| #define | __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) |
| Check whether the specified CRS flag is set or not. More... | |
| #define | __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) |
| Check whether the specified CRS flag is set or not. More... | |
| #define | __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) |
| Check whether the CRS interrupt has occurred or not. More... | |
| #define | __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) |
| Check whether the CRS interrupt has occurred or not. More... | |
| #define | __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__)) |
| Macro to configure the DFSDM1 clock. More... | |
| #define | __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__)) |
| Macro to configure the DFSDM1 clock. More... | |
| #define | __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__)) |
| macro to configure the FMC clock source. More... | |
| #define | __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__)) |
| macro to configure the FMC clock source. More... | |
| #define | __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL))) |
| Macro to get the ADC clock source. More... | |
| #define | __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL))) |
| Macro to get the ADC clock source. More... | |
| #define | __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))) |
| macro to get the CEC clock source. More... | |
| #define | __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL))) |
| macro to get the CEC clock source. More... | |
| #define | __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL))) |
| macro to get the CEC clock source. More... | |
| #define | __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))) |
| macro to get the CLK48 source. More... | |
| #define | __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL))) |
| Macro to get the Oscillator clock for peripheral source. More... | |
| #define | __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL))) |
| Macro to get the Oscillator clock for peripheral source. More... | |
| #define | __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL))) |
| Macro to get the DFSDM1 clock source. More... | |
| #define | __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL))) |
| Macro to get the DFSDM1 clock source. More... | |
| #define | __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL))) |
| macro to get the FMC clock source. More... | |
| #define | __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL))) |
| macro to get the FMC clock source. More... | |
| #define | __HAL_RCC_GET_I2C1235_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL))) |
| macro to get the I2C1/2/3/5* clock source. More... | |
| #define | __HAL_RCC_GET_I2C1235_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL))) |
| macro to get the I2C1/2/3/5* clock source. More... | |
| #define | __HAL_RCC_GET_I2C123_SOURCE __HAL_RCC_GET_I2C1235_SOURCE |
| #define | __HAL_RCC_GET_I2C123_SOURCE __HAL_RCC_GET_I2C1235_SOURCE |
| #define | __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL))) |
| Macro to get the I2C1 clock source. More... | |
| #define | __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE |
| macro to get the I2C1 clock source. More... | |
| #define | __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE |
| macro to get the I2C1 clock source. More... | |
| #define | __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL))) |
| Macro to get the I2C2 clock source. More... | |
| #define | __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE |
| macro to get the I2C2 clock source. More... | |
| #define | __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE |
| macro to get the I2C2 clock source. More... | |
| #define | __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL))) |
| macro to get the I2C3 clock source. More... | |
| #define | __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE |
| macro to get the I2C3 clock source. More... | |
| #define | __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE |
| macro to get the I2C3 clock source. More... | |
| #define | __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL))) |
| macro to get the I2C4 clock source. More... | |
| #define | __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL))) |
| macro to get the I2C4 clock source. More... | |
| #define | __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL))) |
| macro to get the I2C4 clock source. More... | |
| #define | __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)) |
| Macro to Get I2S clock source selection. More... | |
| #define | __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL))) |
| macro to get the LPTIM1 clock source. More... | |
| #define | __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL))) |
| macro to get the LPTIM1 clock source. More... | |
| #define | __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))) |
| macro to get the LPTIM1 clock source. More... | |
| #define | __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL))) |
| macro to get the LPTIM2 clock source. More... | |
| #define | __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL))) |
| macro to get the LPTIM2 clock source. More... | |
| #define | __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL))) |
| macro to get the LPTIM3/4/5 clock source. More... | |
| #define | __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL))) |
| macro to get the LPTIM3/4/5 clock source. More... | |
| #define | __HAL_RCC_GET_LPTIM3_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE |
| macro to get the LPTIM3 clock source. More... | |
| #define | __HAL_RCC_GET_LPTIM3_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE |
| macro to get the LPTIM3 clock source. More... | |
| #define | __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL))) |
| macro to get the LPUART1 clock source. More... | |
| #define | __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL))) |
| macro to get the LPUART1 clock source. More... | |
| #define | __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL))) |
| macro to get the RNG clock source. More... | |
| #define | __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL))) |
| macro to get the RNG clock source. More... | |
| #define | __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL))) |
| Macro to get the SAI1 clock source. More... | |
| #define | __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL))) |
| Macro to get the SAI1 clock source. More... | |
| #define | __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL))) |
| Macro to get the SAI1 clock source. More... | |
| #define | __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL))) |
| Macro to get the SAI2 clock source. More... | |
| #define | __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL))) |
| macro to get the SDMMC1 clock source. More... | |
| #define | __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL))) |
| Macro to get the SDMMC clock. More... | |
| #define | __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL))) |
| Macro to get the SDMMC clock. More... | |
| #define | __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL))) |
| Macro to get the SPDIFRX clock source. More... | |
| #define | __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL))) |
| Macro to get the SPDIFRX clock source. More... | |
| #define | __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL))) |
| Macro to get the SPI1/2/3 clock source. More... | |
| #define | __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL))) |
| Macro to get the SPI1/2/3 clock source. More... | |
| #define | __HAL_RCC_GET_SPI1_SOURCE __HAL_RCC_GET_SPI123_SOURCE |
| Macro to get the SPI1 clock source. More... | |
| #define | __HAL_RCC_GET_SPI1_SOURCE __HAL_RCC_GET_SPI123_SOURCE |
| Macro to get the SPI1 clock source. More... | |
| #define | __HAL_RCC_GET_SPI2_SOURCE __HAL_RCC_GET_SPI123_SOURCE |
| Macro to get the SPI2 clock source. More... | |
| #define | __HAL_RCC_GET_SPI2_SOURCE __HAL_RCC_GET_SPI123_SOURCE |
| Macro to get the SPI2 clock source. More... | |
| #define | __HAL_RCC_GET_SPI3_SOURCE __HAL_RCC_GET_SPI123_SOURCE |
| Macro to get the SPI3 clock source. More... | |
| #define | __HAL_RCC_GET_SPI3_SOURCE __HAL_RCC_GET_SPI123_SOURCE |
| Macro to get the SPI3 clock source. More... | |
| #define | __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL))) |
| Macro to get the SPI4/5 clock source. More... | |
| #define | __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL))) |
| Macro to get the SPI4/5 clock source. More... | |
| #define | __HAL_RCC_GET_SPI4_SOURCE __HAL_RCC_GET_SPI45_SOURCE |
| Macro to get the SPI4 clock source. More... | |
| #define | __HAL_RCC_GET_SPI4_SOURCE __HAL_RCC_GET_SPI45_SOURCE |
| Macro to get the SPI4 clock source. More... | |
| #define | __HAL_RCC_GET_SPI5_SOURCE __HAL_RCC_GET_SPI45_SOURCE |
| Macro to get the SPI5 clock source. More... | |
| #define | __HAL_RCC_GET_SPI5_SOURCE __HAL_RCC_GET_SPI45_SOURCE |
| Macro to get the SPI5 clock source. More... | |
| #define | __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL))) |
| Macro to get the SPI6 clock source. More... | |
| #define | __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL))) |
| Macro to get the SPI6 clock source. More... | |
| #define | __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL))) |
| Macro to get the SWPMI1 clock source. More... | |
| #define | __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL))) |
| Macro to get the SWPMI1 clock source. More... | |
| #define | __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL))) |
| macro to get the UART4 clock source. More... | |
| #define | __HAL_RCC_GET_UART4_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
| macro to get the UART4 clock source. More... | |
| #define | __HAL_RCC_GET_UART4_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
| macro to get the UART4 clock source. More... | |
| #define | __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL))) |
| macro to get the UART5 clock source. More... | |
| #define | __HAL_RCC_GET_UART5_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
| macro to get the UART5 clock source. More... | |
| #define | __HAL_RCC_GET_UART5_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
| macro to get the UART5 clock source. More... | |
| #define | __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL))) |
| macro to get the UART7 clock source. More... | |
| #define | __HAL_RCC_GET_UART7_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
| macro to get the UART7 clock source. More... | |
| #define | __HAL_RCC_GET_UART7_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
| macro to get the UART7 clock source. More... | |
| #define | __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL))) |
| macro to get the UART8 clock source. More... | |
| #define | __HAL_RCC_GET_UART8_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
| macro to get the UART8 clock source. More... | |
| #define | __HAL_RCC_GET_UART8_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
| macro to get the UART8 clock source. More... | |
| #define | __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL))) |
| macro to get the USART1/6/9* /10* clock source. More... | |
| #define | __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL))) |
| macro to get the USART1/6/9* /10* clock source. More... | |
| #define | __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE |
| #define | __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE |
| #define | __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL))) |
| macro to get the USART1 clock source. More... | |
| #define | __HAL_RCC_GET_USART1_SOURCE __HAL_RCC_GET_USART16_SOURCE |
| macro to get the USART1 clock source. More... | |
| #define | __HAL_RCC_GET_USART1_SOURCE __HAL_RCC_GET_USART16_SOURCE |
| macro to get the USART1 clock source. More... | |
| #define | __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL))) |
| macro to get the USART2/3/4/5/7/8 clock source. More... | |
| #define | __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL))) |
| macro to get the USART2/3/4/5/7/8 clock source. More... | |
| #define | __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL))) |
| macro to get the USART2 clock source. More... | |
| #define | __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
| macro to get the USART2 clock source. More... | |
| #define | __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
| macro to get the USART2 clock source. More... | |
| #define | __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL))) |
| macro to get the USART3 clock source. More... | |
| #define | __HAL_RCC_GET_USART3_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
| macro to get the USART3 clock source. More... | |
| #define | __HAL_RCC_GET_USART3_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
| macro to get the USART3 clock source. More... | |
| #define | __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL))) |
| macro to get the USART6 clock source. More... | |
| #define | __HAL_RCC_GET_USART6_SOURCE __HAL_RCC_GET_USART16_SOURCE |
| macro to get the USART6 clock source. More... | |
| #define | __HAL_RCC_GET_USART6_SOURCE __HAL_RCC_GET_USART16_SOURCE |
| macro to get the USART6 clock source. More... | |
| #define | __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL))) |
| Macro to get the USB clock source. More... | |
| #define | __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL))) |
| Macro to get the USB clock source. More... | |
| #define | __HAL_RCC_I2C1235_CONFIG(__I2C1235CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL, (uint32_t)(__I2C1235CLKSource__)) |
| macro to configure the I2C1/2/3/5* clock (I2C123CLK). More... | |
| #define | __HAL_RCC_I2C1235_CONFIG(__I2C1235CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL, (uint32_t)(__I2C1235CLKSource__)) |
| macro to configure the I2C1/2/3/5* clock (I2C123CLK). More... | |
| #define | __HAL_RCC_I2C123_CONFIG __HAL_RCC_I2C1235_CONFIG |
| #define | __HAL_RCC_I2C123_CONFIG __HAL_RCC_I2C1235_CONFIG |
| #define | __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) |
| Macro to configure the I2C1 clock (I2C1CLK). More... | |
| #define | __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C123_CONFIG |
| macro to configure the I2C1 clock (I2C1CLK). More... | |
| #define | __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C123_CONFIG |
| macro to configure the I2C1 clock (I2C1CLK). More... | |
| #define | __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) |
| Macro to configure the I2C2 clock (I2C2CLK). More... | |
| #define | __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG |
| macro to configure the I2C2 clock (I2C2CLK). More... | |
| #define | __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG |
| macro to configure the I2C2 clock (I2C2CLK). More... | |
| #define | __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) |
| Macro to configure the I2C3 clock (I2C3CLK). More... | |
| #define | __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG |
| macro to configure the I2C3 clock (I2C3CLK). More... | |
| #define | __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG |
| macro to configure the I2C3 clock (I2C3CLK). More... | |
| #define | __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) |
| Macro to configure the I2C4 clock (I2C4CLK). More... | |
| #define | __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__)) |
| macro to configure the I2C4 clock (I2C4CLK). More... | |
| #define | __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__)) |
| macro to configure the I2C4 clock (I2C4CLK). More... | |
| #define | __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) |
| Macro to configure the LPTIM1 clock (LPTIM1CLK). More... | |
| #define | __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__)) |
| macro to configure the LPTIM1 clock source. More... | |
| #define | __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__)) |
| macro to configure the LPTIM1 clock source. More... | |
| #define | __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__)) |
| macro to configure the LPTIM2 clock source. More... | |
| #define | __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__)) |
| macro to configure the LPTIM2 clock source. More... | |
| #define | __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM345CLKSource__)) |
| macro to configure the LPTIM3/4/5 clock source. More... | |
| #define | __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM345CLKSource__)) |
| macro to configure the LPTIM3/4/5 clock source. More... | |
| #define | __HAL_RCC_LPTIM3_CONFIG __HAL_RCC_LPTIM345_CONFIG |
| macro to configure the LPTIM3 clock source. More... | |
| #define | __HAL_RCC_LPTIM3_CONFIG __HAL_RCC_LPTIM345_CONFIG |
| macro to configure the LPTIM3 clock source. More... | |
| #define | __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__)) |
| macro to configure the LPUART1 clock (LPUART1CLK). More... | |
| #define | __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__)) |
| macro to configure the LPUART1 clock (LPUART1CLK). More... | |
| #define | __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) |
| Clear the RCC LSE CSS EXTI flag. More... | |
| #define | __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) |
| Clear the RCC LSE CSS EXTI flag. More... | |
| #define | __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) |
| Disable the RCC LSE CSS Event Line. More... | |
| #define | __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) |
| Disable the RCC LSE CSS Event Line. More... | |
| #define | __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) |
| Disable the RCC LSE CSS Extended Interrupt Falling Trigger. More... | |
| #define | __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) |
| Disable the RCC LSE CSS Extended Interrupt Falling Trigger. More... | |
| #define | __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) |
| Disable the RCC LSE CSS Extended Interrupt Line. More... | |
| #define | __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) |
| Disable the RCC LSE CSS Extended Interrupt Line. More... | |
| #define | __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) |
| Disable the RCC LSE CSS Extended Interrupt Rising Trigger. More... | |
| #define | __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) |
| Disable the RCC LSE CSS Extended Interrupt Rising Trigger. More... | |
| #define | __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() |
| Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. More... | |
| #define | __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() |
| Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. More... | |
| #define | __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) |
| Enable the RCC LSE CSS Event Line. More... | |
| #define | __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) |
| Enable the RCC LSE CSS Event Line. More... | |
| #define | __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) |
| Enable the RCC LSE CSS Extended Interrupt Falling Trigger. More... | |
| #define | __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) |
| Enable the RCC LSE CSS Extended Interrupt Falling Trigger. More... | |
| #define | __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) |
| Enable the RCC LSE CSS Extended Interrupt Line. More... | |
| #define | __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) |
| Enable the RCC LSE CSS Extended Interrupt Line. More... | |
| #define | __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) |
| Enable the RCC LSE CSS Extended Interrupt Rising Trigger. More... | |
| #define | __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) |
| Enable the RCC LSE CSS Extended Interrupt Rising Trigger. More... | |
| #define | __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() |
| Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. More... | |
| #define | __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() |
| Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. More... | |
| #define | __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) |
| Generate a Software interrupt on the RCC LSE CSS EXTI line. More... | |
| #define | __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) |
| Generate a Software interrupt on the RCC LSE CSS EXTI line. More... | |
| #define | __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) |
| Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. More... | |
| #define | __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) |
| Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. More... | |
| #define | __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__, __PLL2R__) |
| Macro to configures the PLL2 multiplication and division factors. More... | |
| #define | __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__, __PLL2R__) |
| Macro to configures the PLL2 multiplication and division factors. More... | |
| #define | __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON) |
| #define | __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON) |
| #define | __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON) |
| Macros to enable or disable PLL2. More... | |
| #define | __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON) |
| Macros to enable or disable PLL2. More... | |
| #define | __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__)) |
| Macro to select the PLL2 reference frequency range. More... | |
| #define | __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__)) |
| Macro to select the PLL2 reference frequency range. More... | |
| #define | __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__)) |
| Macro to select the PLL2 reference frequency range. More... | |
| #define | __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__)) |
| Macro to select the PLL2 reference frequency range. More... | |
| #define | __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) |
| #define | __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) |
| #define | __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) |
| Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK) More... | |
| #define | __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) |
| Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK) More... | |
| #define | __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos)) |
| Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor. More... | |
| #define | __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos)) |
| Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor. More... | |
| #define | __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) |
| #define | __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) |
| #define | __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) |
| Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO. More... | |
| #define | __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) |
| Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO. More... | |
| #define | __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__, __PLL3R__) |
| Macro to configures the PLL3 multiplication and division factors. More... | |
| #define | __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__, __PLL3R__) |
| Macro to configures the PLL3 multiplication and division factors. More... | |
| #define | __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON) |
| #define | __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON) |
| #define | __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON) |
| Macros to enable or disable the main PLL3. More... | |
| #define | __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON) |
| Macros to enable or disable the main PLL3. More... | |
| #define | __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__)) |
| Macro to select the PLL3 reference frequency range. More... | |
| #define | __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__)) |
| Macro to select the PLL3 reference frequency range. More... | |
| #define | __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__)) |
| Macro to select the PLL3 reference frequency range. More... | |
| #define | __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__)) |
| Macro to select the PLL3 reference frequency range. More... | |
| #define | __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) |
| #define | __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) |
| #define | __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) |
| Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK) More... | |
| #define | __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) |
| Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK) More... | |
| #define | __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos) |
| Macro to configures PLL3 clock Fractional Part of The Multiplication Factor. More... | |
| #define | __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos) |
| Macro to configures PLL3 clock Fractional Part of The Multiplication Factor. More... | |
| #define | __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) |
| #define | __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) |
| #define | __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) |
| Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO. More... | |
| #define | __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) |
| Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO. More... | |
| #define | __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) |
| Macro to configure the main PLL clock source, multiplication and division factors. More... | |
| #define | __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) |
| Macro to configure the main PLL clock source, multiplication and division factors. More... | |
| #define | __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) |
| Macro to configure the main PLL clock source, multiplication and division factors. More... | |
| #define | __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) |
| Macro to configure the main PLL clock source, multiplication and division factors. More... | |
| #define | __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) |
| Macro to configure the PLLI2S clock multiplication and division factors. More... | |
| #define | __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) |
| Macro to configure the PLLI2S clock multiplication and division factors . More... | |
| #define | __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) |
| Macro to configure the PLLI2S clock multiplication and division factors . More... | |
| #define | __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) |
| Macro to configure the PLLI2S clock multiplication and division factors . More... | |
| #define | __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1)) |
| Macro to configure the SAI clock Divider coming from PLLI2S. More... | |
| #define | __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF)) |
| Clear the PLLSAI RDY interrupt pending bits. More... | |
| #define | __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) |
| Macro to configure the PLLSAI clock multiplication and division factors. More... | |
| #define | __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION)) |
| #define | __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE)) |
| Disable PLLSAI_RDY interrupt. More... | |
| #define | __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION)) |
| Macros to Enable or Disable the PLLISAI. More... | |
| #define | __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE)) |
| Enable PLLSAI_RDY interrupt. More... | |
| #define | __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY)) |
| Check PLLSAI RDY flag is set or not. More... | |
| #define | __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE)) |
| Check the PLLSAI RDY interrupt has occurred or not. More... | |
| #define | __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8)) |
| Macro to configure the SAI clock Divider coming from PLLSAI. More... | |
| #define | __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__)) |
| macro to configure the RNG clock (RNGCLK). More... | |
| #define | __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__)) |
| macro to configure the RNG clock (RNGCLK). More... | |
| #define | __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__)) |
| Macro to Configure the SAI1 clock source. More... | |
| #define | __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__)) |
| Macro to Configure the SAI1 clock source. More... | |
| #define | __HAL_RCC_SAI1_CONFIG(__SOURCE__) MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__)) |
| Macro to configure SAI1 clock source selection. More... | |
| #define | __HAL_RCC_SAI2_CONFIG(__SOURCE__) MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__)) |
| Macro to configure SAI2 clock source selection. More... | |
| #define | __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)) |
| Macro to configure the SDMMC1 clock (SDMMC1CLK). More... | |
| #define | __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__)) |
| Macro to configure the SDMMC clock. More... | |
| #define | __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__)) |
| Macro to configure the SDMMC clock. More... | |
| #define | __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__)) |
| Macro to Configure the SPDIFRX clock source. More... | |
| #define | __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__)) |
| Macro to Configure the SPDIFRX clock source. More... | |
| #define | __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__)) |
| Macro to Configure the SPI1/2/3 clock source. More... | |
| #define | __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__)) |
| Macro to Configure the SPI1/2/3 clock source. More... | |
| #define | __HAL_RCC_SPI1_CONFIG __HAL_RCC_SPI123_CONFIG |
| Macro to Configure the SPI1 clock source. More... | |
| #define | __HAL_RCC_SPI1_CONFIG __HAL_RCC_SPI123_CONFIG |
| Macro to Configure the SPI1 clock source. More... | |
| #define | __HAL_RCC_SPI2_CONFIG __HAL_RCC_SPI123_CONFIG |
| Macro to Configure the SPI2 clock source. More... | |
| #define | __HAL_RCC_SPI2_CONFIG __HAL_RCC_SPI123_CONFIG |
| Macro to Configure the SPI2 clock source. More... | |
| #define | __HAL_RCC_SPI3_CONFIG __HAL_RCC_SPI123_CONFIG |
| Macro to Configure the SPI3 clock source. More... | |
| #define | __HAL_RCC_SPI3_CONFIG __HAL_RCC_SPI123_CONFIG |
| Macro to Configure the SPI3 clock source. More... | |
| #define | __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__)) |
| Macro to Configure the SPI4/5 clock source. More... | |
| #define | __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__)) |
| Macro to Configure the SPI4/5 clock source. More... | |
| #define | __HAL_RCC_SPI4_CONFIG __HAL_RCC_SPI45_CONFIG |
| Macro to Configure the SPI4 clock source. More... | |
| #define | __HAL_RCC_SPI4_CONFIG __HAL_RCC_SPI45_CONFIG |
| Macro to Configure the SPI4 clock source. More... | |
| #define | __HAL_RCC_SPI5_CONFIG __HAL_RCC_SPI45_CONFIG |
| Macro to Configure the SPI5 clock source. More... | |
| #define | __HAL_RCC_SPI5_CONFIG __HAL_RCC_SPI45_CONFIG |
| Macro to Configure the SPI5 clock source. More... | |
| #define | __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__)) |
| Macro to Configure the SPI6 clock source. More... | |
| #define | __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__) MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__)) |
| Macro to Configure the SPI6 clock source. More... | |
| #define | __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__)) |
| Macro to configure the SWPMI1 clock. More... | |
| #define | __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__)) |
| Macro to configure the SWPMI1 clock. More... | |
| #define | __HAL_RCC_TIMCLKPRESCALER(__PRESC__) |
| Macro to configure the Timers clocks prescalers. More... | |
| #define | __HAL_RCC_TIMCLKPRESCALER(__PRESC__) |
| Macro to configure the Timers clocks prescalers. More... | |
| #define | __HAL_RCC_TIMCLKPRESCALER(__PRESC__) |
| Macro to configure the Timers clocks prescalers. More... | |
| #define | __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) |
| Macro to configure the UART4 clock (UART4CLK). More... | |
| #define | __HAL_RCC_UART4_CONFIG __HAL_RCC_USART234578_CONFIG |
| macro to configure the UART4 clock (UART4CLK). More... | |
| #define | __HAL_RCC_UART4_CONFIG __HAL_RCC_USART234578_CONFIG |
| macro to configure the UART4 clock (UART4CLK). More... | |
| #define | __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) |
| Macro to configure the UART5 clock (UART5CLK). More... | |
| #define | __HAL_RCC_UART5_CONFIG __HAL_RCC_USART234578_CONFIG |
| macro to configure the UART5 clock (UART5CLK). More... | |
| #define | __HAL_RCC_UART5_CONFIG __HAL_RCC_USART234578_CONFIG |
| macro to configure the UART5 clock (UART5CLK). More... | |
| #define | __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__)) |
| Macro to configure the UART7 clock (UART7CLK). More... | |
| #define | __HAL_RCC_UART7_CONFIG __HAL_RCC_USART234578_CONFIG |
| macro to configure the UART5 clock (UART7CLK). More... | |
| #define | __HAL_RCC_UART7_CONFIG __HAL_RCC_USART234578_CONFIG |
| macro to configure the UART5 clock (UART7CLK). More... | |
| #define | __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__)) |
| Macro to configure the UART8 clock (UART8CLK). More... | |
| #define | __HAL_RCC_UART8_CONFIG __HAL_RCC_USART234578_CONFIG |
| macro to configure the UART8 clock (UART8CLK). More... | |
| #define | __HAL_RCC_UART8_CONFIG __HAL_RCC_USART234578_CONFIG |
| macro to configure the UART8 clock (UART8CLK). More... | |
| #define | __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__)) |
| macro to configure the USART1/6/9* /10* clock (USART16CLK). More... | |
| #define | __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__)) |
| macro to configure the USART1/6/9* /10* clock (USART16CLK). More... | |
| #define | __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG |
| #define | __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG |
| #define | __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) |
| Macro to configure the USART1 clock (USART1CLK). More... | |
| #define | __HAL_RCC_USART1_CONFIG __HAL_RCC_USART16_CONFIG |
| macro to configure the USART1 clock (USART1CLK). More... | |
| #define | __HAL_RCC_USART1_CONFIG __HAL_RCC_USART16_CONFIG |
| macro to configure the USART1 clock (USART1CLK). More... | |
| #define | __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__)) |
| macro to configure the USART234578 clock (USART234578CLK). More... | |
| #define | __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__)) |
| macro to configure the USART234578 clock (USART234578CLK). More... | |
| #define | __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) |
| Macro to configure the USART2 clock (USART2CLK). More... | |
| #define | __HAL_RCC_USART2_CONFIG __HAL_RCC_USART234578_CONFIG |
| macro to configure the USART2 clock (USART2CLK). More... | |
| #define | __HAL_RCC_USART2_CONFIG __HAL_RCC_USART234578_CONFIG |
| macro to configure the USART2 clock (USART2CLK). More... | |
| #define | __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) |
| Macro to configure the USART3 clock (USART3CLK). More... | |
| #define | __HAL_RCC_USART3_CONFIG __HAL_RCC_USART234578_CONFIG |
| macro to configure the USART3 clock (USART3CLK). More... | |
| #define | __HAL_RCC_USART3_CONFIG __HAL_RCC_USART234578_CONFIG |
| macro to configure the USART3 clock (USART3CLK). More... | |
| #define | __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__)) |
| Macro to configure the USART6 clock (USART6CLK). More... | |
| #define | __HAL_RCC_USART6_CONFIG __HAL_RCC_USART16_CONFIG |
| macro to configure the USART6 clock (USART6CLK). More... | |
| #define | __HAL_RCC_USART6_CONFIG __HAL_RCC_USART16_CONFIG |
| macro to configure the USART6 clock (USART6CLK). More... | |
| #define | __HAL_RCC_USB_CONFIG(__USBCLKSource__) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__)) |
| Macro to configure the USB clock (USBCLK). More... | |
| #define | __HAL_RCC_USB_CONFIG(__USBCLKSource__) MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__)) |
| Macro to configure the USB clock (USBCLK). More... | |
| #define | RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) |
| Clear the CRS specified FLAG. More... | |
| #define | RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) |
| Clear the CRS specified FLAG. More... | |
| #define | RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) |
| Clear the CRS interrupt pending bits. More... | |
| #define | RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) |
| Clear the CRS interrupt pending bits. More... | |
Detailed Description
Macro Definition Documentation
◆ __HAL_RCC_ADC_CONFIG [1/2]
| #define __HAL_RCC_ADC_CONFIG | ( | __ADCCLKSource__ | ) | MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__)) |
Macro to configure the ADC clock.
- Parameters
-
<strong>ADCCLKSource</strong> specifies the ADC digital interface clock source. This parameter can be one of the following values: - RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
- RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
- RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock
Definition at line 3112 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_ADC_CONFIG [2/2]
| #define __HAL_RCC_ADC_CONFIG | ( | __ADCCLKSource__ | ) | MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__)) |
Macro to configure the ADC clock.
- Parameters
-
<strong>ADCCLKSource</strong> specifies the ADC digital interface clock source. This parameter can be one of the following values: - RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
- RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
- RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock
Definition at line 3116 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_CEC_CONFIG [1/3]
| #define __HAL_RCC_CEC_CONFIG | ( | __CEC_CLKSOURCE__ | ) | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__)) |
Macro to configure the CEC clock (CECCLK).
- Parameters
-
<strong>CEC_CLKSOURCE</strong> specifies the CEC clock source. This parameter can be one of the following values: - RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
- RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock
Definition at line 3087 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_CEC_CONFIG [2/3]
| #define __HAL_RCC_CEC_CONFIG | ( | __CECCLKSource__ | ) | MODIFY_REG(RCC->D2CCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__)) |
macro to configure the CEC clock (CECCLK).
- Parameters
-
<strong>CECCLKSource</strong> specifies the CEC clock source. This parameter can be one of the following values: - RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
- RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
- RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock
Definition at line 3208 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_CEC_CONFIG [3/3]
| #define __HAL_RCC_CEC_CONFIG | ( | __CECCLKSource__ | ) | MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__)) |
macro to configure the CEC clock (CECCLK).
- Parameters
-
<strong>CECCLKSource</strong> specifies the CEC clock source. This parameter can be one of the following values: - RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
- RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
- RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock
Definition at line 3212 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_CLK48_CONFIG
| #define __HAL_RCC_CLK48_CONFIG | ( | __CLK48_SOURCE__ | ) | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__)) |
Macro to configure the CLK48 source (CLK48CLK).
- Parameters
-
<strong>CLK48_SOURCE</strong> specifies the CLK48 clock source. This parameter can be one of the following values: - RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source
- RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source
Definition at line 3104 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_CLKP_CONFIG [1/2]
| #define __HAL_RCC_CLKP_CONFIG | ( | __CLKPSource__ | ) | MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__)) |
Macro to configure the CLKP : Oscillator clock for peripheral.
- Parameters
-
<strong>CLKPSource</strong> specifies Oscillator clock for peripheral This parameter can be one of the following values: - RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
- RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
- RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral
Definition at line 3235 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_CLKP_CONFIG [2/2]
| #define __HAL_RCC_CLKP_CONFIG | ( | __CLKPSource__ | ) | MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__)) |
Macro to configure the CLKP : Oscillator clock for peripheral.
- Parameters
-
<strong>CLKPSource</strong> specifies Oscillator clock for peripheral This parameter can be one of the following values: - RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
- RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
- RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral
Definition at line 3239 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_CRS_CLEAR_FLAG [1/2]
| #define __HAL_RCC_CRS_CLEAR_FLAG | ( | __FLAG__ | ) |
Value:
do { \
if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
{ \
} \
else \
{ \
WRITE_REG(CRS->ICR, (__FLAG__)); \
} \
} while(0)
Definition at line 3821 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_CRS_CLEAR_FLAG [2/2]
| #define __HAL_RCC_CRS_CLEAR_FLAG | ( | __FLAG__ | ) |
Value:
do { \
if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
{ \
} \
else \
{ \
WRITE_REG(CRS->ICR, (__FLAG__)); \
} \
} while(0)
Definition at line 3825 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_CRS_CLEAR_IT [1/2]
| #define __HAL_RCC_CRS_CLEAR_IT | ( | __INTERRUPT__ | ) |
Value:
do { \
if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
{ \
} \
else \
{ \
WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
} \
} while(0)
Definition at line 3777 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_CRS_CLEAR_IT [2/2]
| #define __HAL_RCC_CRS_CLEAR_IT | ( | __INTERRUPT__ | ) |
Value:
do { \
if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
{ \
} \
else \
{ \
WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
} \
} while(0)
Definition at line 3781 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_CRS_DISABLE_IT [1/2]
Disable the specified CRS interrupts.
- Parameters
-
<strong>INTERRUPT</strong> specifies the CRS interrupt sources to be disabled. This parameter can be any combination of the following values: - RCC_CRS_IT_SYNCOK SYNC event OK interrupt
- RCC_CRS_IT_SYNCWARN SYNC warning interrupt
- RCC_CRS_IT_ERR Synchronization or trimming error interrupt
- RCC_CRS_IT_ESYNC Expected SYNC interrupt
- Return values
-
None
Definition at line 3750 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_CRS_DISABLE_IT [2/2]
Disable the specified CRS interrupts.
- Parameters
-
<strong>INTERRUPT</strong> specifies the CRS interrupt sources to be disabled. This parameter can be any combination of the following values: - RCC_CRS_IT_SYNCOK SYNC event OK interrupt
- RCC_CRS_IT_SYNCWARN SYNC warning interrupt
- RCC_CRS_IT_ERR Synchronization or trimming error interrupt
- RCC_CRS_IT_ESYNC Expected SYNC interrupt
- Return values
-
None
Definition at line 3754 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_CRS_ENABLE_IT [1/2]
Enable the specified CRS interrupts.
- Parameters
-
<strong>INTERRUPT</strong> specifies the CRS interrupt sources to be enabled. This parameter can be any combination of the following values: - RCC_CRS_IT_SYNCOK SYNC event OK interrupt
- RCC_CRS_IT_SYNCWARN SYNC warning interrupt
- RCC_CRS_IT_ERR Synchronization or trimming error interrupt
- RCC_CRS_IT_ESYNC Expected SYNC interrupt
- Return values
-
None
Definition at line 3738 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_CRS_ENABLE_IT [2/2]
Enable the specified CRS interrupts.
- Parameters
-
<strong>INTERRUPT</strong> specifies the CRS interrupt sources to be enabled. This parameter can be any combination of the following values: - RCC_CRS_IT_SYNCOK SYNC event OK interrupt
- RCC_CRS_IT_SYNCWARN SYNC warning interrupt
- RCC_CRS_IT_ERR Synchronization or trimming error interrupt
- RCC_CRS_IT_ESYNC Expected SYNC interrupt
- Return values
-
None
Definition at line 3742 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_CRS_GET_FLAG [1/2]
Check whether the specified CRS flag is set or not.
- Parameters
-
<strong>FLAG</strong> specifies the flag to check. This parameter can be one of the following values: - RCC_CRS_FLAG_SYNCOK SYNC event OK
- RCC_CRS_FLAG_SYNCWARN SYNC warning
- RCC_CRS_FLAG_ERR Error
- RCC_CRS_FLAG_ESYNC Expected SYNC
- RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
- RCC_CRS_FLAG_SYNCERR SYNC error
- RCC_CRS_FLAG_SYNCMISS SYNC missed
- Return values
-
The new state of FLAG (TRUE or FALSE).
Definition at line 3801 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_CRS_GET_FLAG [2/2]
Check whether the specified CRS flag is set or not.
- Parameters
-
<strong>FLAG</strong> specifies the flag to check. This parameter can be one of the following values: - RCC_CRS_FLAG_SYNCOK SYNC event OK
- RCC_CRS_FLAG_SYNCWARN SYNC warning
- RCC_CRS_FLAG_ERR Error
- RCC_CRS_FLAG_ESYNC Expected SYNC
- RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
- RCC_CRS_FLAG_SYNCERR SYNC error
- RCC_CRS_FLAG_SYNCMISS SYNC missed
- Return values
-
The new state of FLAG (TRUE or FALSE).
Definition at line 3805 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_CRS_GET_IT_SOURCE [1/2]
| #define __HAL_RCC_CRS_GET_IT_SOURCE | ( | __INTERRUPT__ | ) | ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) |
Check whether the CRS interrupt has occurred or not.
- Parameters
-
<strong>INTERRUPT</strong> specifies the CRS interrupt source to check. This parameter can be one of the following values: - RCC_CRS_IT_SYNCOK SYNC event OK interrupt
- RCC_CRS_IT_SYNCWARN SYNC warning interrupt
- RCC_CRS_IT_ERR Synchronization or trimming error interrupt
- RCC_CRS_IT_ESYNC Expected SYNC interrupt
- Return values
-
The new state of INTERRUPT (SET or RESET).
Definition at line 3761 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_CRS_GET_IT_SOURCE [2/2]
| #define __HAL_RCC_CRS_GET_IT_SOURCE | ( | __INTERRUPT__ | ) | ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) |
Check whether the CRS interrupt has occurred or not.
- Parameters
-
<strong>INTERRUPT</strong> specifies the CRS interrupt source to check. This parameter can be one of the following values: - RCC_CRS_IT_SYNCOK SYNC event OK interrupt
- RCC_CRS_IT_SYNCWARN SYNC warning interrupt
- RCC_CRS_IT_ERR Synchronization or trimming error interrupt
- RCC_CRS_IT_ESYNC Expected SYNC interrupt
- Return values
-
The new state of INTERRUPT (SET or RESET).
Definition at line 3765 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_DFSDM1_CONFIG [1/2]
| #define __HAL_RCC_DFSDM1_CONFIG | ( | __DFSDM1CLKSource__ | ) | MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__)) |
Macro to configure the DFSDM1 clock.
- Parameters
-
<strong>DFSDM1CLKSource</strong> specifies the DFSDM1 clock source. This parameter can be one of the following values: - RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock
- RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock
Definition at line 3163 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_DFSDM1_CONFIG [2/2]
| #define __HAL_RCC_DFSDM1_CONFIG | ( | __DFSDM1CLKSource__ | ) | MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__)) |
Macro to configure the DFSDM1 clock.
- Parameters
-
<strong>DFSDM1CLKSource</strong> specifies the DFSDM1 clock source. This parameter can be one of the following values: - RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock
- RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock
Definition at line 3167 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_FMC_CONFIG [1/2]
| #define __HAL_RCC_FMC_CONFIG | ( | __FMCCLKSource__ | ) | MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__)) |
macro to configure the FMC clock source.
- Parameters
-
<strong>FMCCLKSource</strong> specifies the FMC clock source. - RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
- RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock
- RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock
- RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock
Definition at line 3057 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_FMC_CONFIG [2/2]
| #define __HAL_RCC_FMC_CONFIG | ( | __FMCCLKSource__ | ) | MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__)) |
macro to configure the FMC clock source.
- Parameters
-
<strong>FMCCLKSource</strong> specifies the FMC clock source. - RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
- RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock
- RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock
- RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock
Definition at line 3061 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_ADC_SOURCE [1/2]
Macro to get the ADC clock source.
- Return values
-
The clock source can be one of the following values: - RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
- RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
- RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock
Definition at line 3125 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_ADC_SOURCE [2/2]
Macro to get the ADC clock source.
- Return values
-
The clock source can be one of the following values: - RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
- RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
- RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock
Definition at line 3129 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_CEC_SOURCE [1/3]
| #define __HAL_RCC_GET_CEC_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))) |
macro to get the CEC clock source.
- Return values
-
The clock source can be one of the following values: - RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
- RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Definition at line 3095 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_CEC_SOURCE [2/3]
macro to get the CEC clock source.
- Return values
-
The clock source can be one of the following values: - RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
- RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
- RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock
Definition at line 3221 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_CEC_SOURCE [3/3]
macro to get the CEC clock source.
- Return values
-
The clock source can be one of the following values: - RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
- RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
- RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock
Definition at line 3225 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_CLK48_SOURCE
| #define __HAL_RCC_GET_CLK48_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))) |
macro to get the CLK48 source.
- Return values
-
The clock source can be one of the following values: - RCC_CLK48SOURCE_PLL: PLL used as CLK48 source
- RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source
Definition at line 3112 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_CLKP_SOURCE [1/2]
Macro to get the Oscillator clock for peripheral source.
- Return values
-
The clock source can be one of the following values: - RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
- RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
- RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral
Definition at line 3248 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_CLKP_SOURCE [2/2]
Macro to get the Oscillator clock for peripheral source.
- Return values
-
The clock source can be one of the following values: - RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
- RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
- RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral
Definition at line 3252 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_DFSDM1_SOURCE [1/2]
| #define __HAL_RCC_GET_DFSDM1_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL))) |
Macro to get the DFSDM1 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock
- RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock
Definition at line 3175 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_DFSDM1_SOURCE [2/2]
| #define __HAL_RCC_GET_DFSDM1_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL))) |
Macro to get the DFSDM1 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock
- RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock
Definition at line 3179 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_FMC_SOURCE [1/2]
macro to get the FMC clock source.
- Return values
-
The clock source can be one of the following values: - RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
- RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock
- RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock
- RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock
Definition at line 3071 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_FMC_SOURCE [2/2]
macro to get the FMC clock source.
- Return values
-
The clock source can be one of the following values: - RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
- RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock
- RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock
- RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock
Definition at line 3075 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_I2C1235_SOURCE [1/2]
| #define __HAL_RCC_GET_I2C1235_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL))) |
macro to get the I2C1/2/3/5* clock source.
- Return values
-
The clock source can be one of the following values: - RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock
- RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock
- RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock
- RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock
Definition at line 2293 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_I2C1235_SOURCE [2/2]
| #define __HAL_RCC_GET_I2C1235_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL))) |
macro to get the I2C1/2/3/5* clock source.
- Return values
-
The clock source can be one of the following values: - RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock
- RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock
- RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock
- RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock
Definition at line 2293 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_I2C123_SOURCE [1/2]
| #define __HAL_RCC_GET_I2C123_SOURCE __HAL_RCC_GET_I2C1235_SOURCE |
Definition at line 2295 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_I2C123_SOURCE [2/2]
| #define __HAL_RCC_GET_I2C123_SOURCE __HAL_RCC_GET_I2C1235_SOURCE |
Definition at line 2295 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_I2C1_SOURCE [1/3]
| #define __HAL_RCC_GET_I2C1_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL))) |
Macro to get the I2C1 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
- RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
- RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
Definition at line 2832 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_I2C1_SOURCE [2/3]
| #define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE |
macro to get the I2C1 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
- RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
- RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
- RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock
Definition at line 2323 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_I2C1_SOURCE [3/3]
| #define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE |
macro to get the I2C1 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
- RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
- RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
- RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock
Definition at line 2323 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_I2C2_SOURCE [1/3]
| #define __HAL_RCC_GET_I2C2_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL))) |
Macro to get the I2C2 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
- RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
- RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Definition at line 2851 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_I2C2_SOURCE [2/3]
| #define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE |
macro to get the I2C2 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
- RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
- RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
- RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock
Definition at line 2351 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_I2C2_SOURCE [3/3]
| #define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE |
macro to get the I2C2 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
- RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
- RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
- RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock
Definition at line 2351 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_I2C3_SOURCE [1/3]
| #define __HAL_RCC_GET_I2C3_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL))) |
macro to get the I2C3 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
- RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
- RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Definition at line 2870 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_I2C3_SOURCE [2/3]
| #define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE |
macro to get the I2C3 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
- RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
- RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
- RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock
Definition at line 2379 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_I2C3_SOURCE [3/3]
| #define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE |
macro to get the I2C3 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
- RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
- RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
- RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock
Definition at line 2379 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_I2C4_SOURCE [1/3]
| #define __HAL_RCC_GET_I2C4_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL))) |
macro to get the I2C4 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
- RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
- RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
- RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock
Definition at line 2406 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_I2C4_SOURCE [2/3]
macro to get the I2C4 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
- RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
- RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
- RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock
Definition at line 2409 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_I2C4_SOURCE [3/3]
| #define __HAL_RCC_GET_I2C4_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL))) |
macro to get the I2C4 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
- RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
- RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
Definition at line 2889 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_I2SCLKSOURCE
| #define __HAL_RCC_GET_I2SCLKSOURCE | ( | ) | (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)) |
Macro to Get I2S clock source selection.
- Return values
-
The clock source can be one of the following values: - RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
- RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source
Definition at line 2813 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_LPTIM1_SOURCE [1/3]
| #define __HAL_RCC_GET_LPTIM1_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL))) |
macro to get the LPTIM1 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock
Definition at line 2826 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_LPTIM1_SOURCE [2/3]
| #define __HAL_RCC_GET_LPTIM1_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL))) |
macro to get the LPTIM1 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock
Definition at line 2830 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_LPTIM1_SOURCE [3/3]
| #define __HAL_RCC_GET_LPTIM1_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))) |
macro to get the LPTIM1 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
Definition at line 3078 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_LPTIM2_SOURCE [1/2]
| #define __HAL_RCC_GET_LPTIM2_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL))) |
macro to get the LPTIM2 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
- RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
- RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
- RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
- RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
- RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock
Definition at line 2860 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_LPTIM2_SOURCE [2/2]
| #define __HAL_RCC_GET_LPTIM2_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL))) |
macro to get the LPTIM2 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
- RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
- RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
- RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
- RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
- RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock
Definition at line 2864 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_LPTIM345_SOURCE [1/2]
| #define __HAL_RCC_GET_LPTIM345_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL))) |
macro to get the LPTIM3/4/5 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
- RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
- RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
- RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
- RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
- RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock
Definition at line 2893 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_LPTIM345_SOURCE [2/2]
| #define __HAL_RCC_GET_LPTIM345_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL))) |
macro to get the LPTIM3/4/5 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
- RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
- RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
- RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
- RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
- RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock
Definition at line 2897 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_LPTIM3_SOURCE [1/2]
| #define __HAL_RCC_GET_LPTIM3_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE |
macro to get the LPTIM3 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
- RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
- RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
- RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
- RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
- RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock
Definition at line 2917 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_LPTIM3_SOURCE [2/2]
| #define __HAL_RCC_GET_LPTIM3_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE |
macro to get the LPTIM3 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
- RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
- RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
- RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
- RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
- RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock
Definition at line 2921 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_LPUART1_SOURCE [1/2]
| #define __HAL_RCC_GET_LPUART1_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL))) |
macro to get the LPUART1 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
- RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
- RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
- RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
- RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
- RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
Definition at line 2792 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_LPUART1_SOURCE [2/2]
| #define __HAL_RCC_GET_LPUART1_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL))) |
macro to get the LPUART1 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
- RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
- RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
- RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
- RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
- RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
Definition at line 2796 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_RNG_SOURCE [1/2]
macro to get the RNG clock source.
- Return values
-
The clock source can be one of the following values: - RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
- RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
- RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
- RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock
Definition at line 3566 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_RNG_SOURCE [2/2]
macro to get the RNG clock source.
- Return values
-
The clock source can be one of the following values: - RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
- RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
- RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
- RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock
Definition at line 3570 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SAI1_SOURCE [1/3]
Macro to get the SAI1 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
- RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2
- RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3
- RCC_SAI1CLKSOURCE_CLKP: SAI1 clock = CLKP
- RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock
Definition at line 2035 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SAI1_SOURCE [2/3]
Macro to get the SAI1 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
- RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2
- RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3
- RCC_SAI1CLKSOURCE_CLKP: SAI1 clock = CLKP
- RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock
Definition at line 2035 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SAI1_SOURCE [3/3]
| #define __HAL_RCC_GET_SAI1_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL))) |
Macro to get the SAI1 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
- RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
- RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
- RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI1 clock.
- Note
- The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
Definition at line 2750 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SAI2_SOURCE
| #define __HAL_RCC_GET_SAI2_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL))) |
Macro to get the SAI2 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
- RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
- RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin used as SAI2 clock.
- RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
- Note
- The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
Definition at line 2783 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SDMMC1_SOURCE
| #define __HAL_RCC_GET_SDMMC1_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL))) |
macro to get the SDMMC1 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock
- RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock
Definition at line 3129 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SDMMC_SOURCE [1/2]
Macro to get the SDMMC clock.
Definition at line 3536 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SDMMC_SOURCE [2/2]
Macro to get the SDMMC clock.
Definition at line 3540 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SPDIFRX_SOURCE [1/2]
| #define __HAL_RCC_GET_SPDIFRX_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL))) |
Macro to get the SPDIFRX clock source.
- Return values
-
None
Definition at line 2064 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SPDIFRX_SOURCE [2/2]
| #define __HAL_RCC_GET_SPDIFRX_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL))) |
Macro to get the SPDIFRX clock source.
- Return values
-
None
Definition at line 2064 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SPI123_SOURCE [1/2]
| #define __HAL_RCC_GET_SPI123_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL))) |
Macro to get the SPI1/2/3 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
- RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
- RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
- RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP
- RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock
Definition at line 3312 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SPI123_SOURCE [2/2]
| #define __HAL_RCC_GET_SPI123_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL))) |
Macro to get the SPI1/2/3 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
- RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
- RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
- RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP
- RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock
Definition at line 3316 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SPI1_SOURCE [1/2]
| #define __HAL_RCC_GET_SPI1_SOURCE __HAL_RCC_GET_SPI123_SOURCE |
Macro to get the SPI1 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
- RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2
- RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3
- RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP
- RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock
Definition at line 3337 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SPI1_SOURCE [2/2]
| #define __HAL_RCC_GET_SPI1_SOURCE __HAL_RCC_GET_SPI123_SOURCE |
Macro to get the SPI1 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
- RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2
- RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3
- RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP
- RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock
Definition at line 3341 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SPI2_SOURCE [1/2]
| #define __HAL_RCC_GET_SPI2_SOURCE __HAL_RCC_GET_SPI123_SOURCE |
Macro to get the SPI2 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
- RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2
- RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3
- RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP
- RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock
Definition at line 3361 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SPI2_SOURCE [2/2]
| #define __HAL_RCC_GET_SPI2_SOURCE __HAL_RCC_GET_SPI123_SOURCE |
Macro to get the SPI2 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
- RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2
- RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3
- RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP
- RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock
Definition at line 3365 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SPI3_SOURCE [1/2]
| #define __HAL_RCC_GET_SPI3_SOURCE __HAL_RCC_GET_SPI123_SOURCE |
Macro to get the SPI3 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
- RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2
- RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3
- RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP
- RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock
Definition at line 3385 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SPI3_SOURCE [2/2]
| #define __HAL_RCC_GET_SPI3_SOURCE __HAL_RCC_GET_SPI123_SOURCE |
Macro to get the SPI3 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
- RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2
- RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3
- RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP
- RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock
Definition at line 3389 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SPI45_SOURCE [1/2]
Macro to get the SPI4/5 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
- RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2
- RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3
- RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI
- RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI
- RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE
Definition at line 3420 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SPI45_SOURCE [2/2]
Macro to get the SPI4/5 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
- RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2
- RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3
- RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI
- RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI
- RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE
Definition at line 3424 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SPI4_SOURCE [1/2]
| #define __HAL_RCC_GET_SPI4_SOURCE __HAL_RCC_GET_SPI45_SOURCE |
Macro to get the SPI4 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
- RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2
- RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3
- RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI
- RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI
- RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE
Definition at line 3447 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SPI4_SOURCE [2/2]
| #define __HAL_RCC_GET_SPI4_SOURCE __HAL_RCC_GET_SPI45_SOURCE |
Macro to get the SPI4 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
- RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2
- RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3
- RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI
- RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI
- RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE
Definition at line 3451 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SPI5_SOURCE [1/2]
| #define __HAL_RCC_GET_SPI5_SOURCE __HAL_RCC_GET_SPI45_SOURCE |
Macro to get the SPI5 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
- RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2
- RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3
- RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI
- RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI
- RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE
Definition at line 3473 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SPI5_SOURCE [2/2]
| #define __HAL_RCC_GET_SPI5_SOURCE __HAL_RCC_GET_SPI45_SOURCE |
Macro to get the SPI5 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
- RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2
- RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3
- RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI
- RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI
- RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE
Definition at line 3477 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SPI6_SOURCE [1/2]
Macro to get the SPI6 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
- RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2
- RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3
- RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI
- RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI
- RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE
- RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN
Definition at line 3514 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SPI6_SOURCE [2/2]
Macro to get the SPI6 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
- RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2
- RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3
- RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI
- RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI
- RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE
- RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN
Definition at line 3518 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SWPMI1_SOURCE [1/2]
Macro to get the SWPMI1 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock
- RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
Definition at line 3150 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_SWPMI1_SOURCE [2/2]
Macro to get the SWPMI1 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock
- RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
Definition at line 3154 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_UART4_SOURCE [1/3]
| #define __HAL_RCC_GET_UART4_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL))) |
macro to get the UART4 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
- RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
- RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
- RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
Definition at line 2973 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_UART4_SOURCE [2/3]
| #define __HAL_RCC_GET_UART4_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
macro to get the UART4 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
- RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
- RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
- RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
- RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
- RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
Definition at line 2611 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_UART4_SOURCE [3/3]
| #define __HAL_RCC_GET_UART4_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
macro to get the UART4 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
- RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
- RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
- RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
- RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
- RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
Definition at line 2615 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_UART5_SOURCE [1/3]
| #define __HAL_RCC_GET_UART5_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL))) |
macro to get the UART5 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
- RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
- RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
- RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
Definition at line 2994 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_UART5_SOURCE [2/3]
| #define __HAL_RCC_GET_UART5_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
macro to get the UART5 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
- RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
- RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
- RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
- RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
- RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
Definition at line 2635 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_UART5_SOURCE [3/3]
| #define __HAL_RCC_GET_UART5_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
macro to get the UART5 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
- RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
- RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
- RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
- RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
- RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
Definition at line 2639 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_UART7_SOURCE [1/3]
| #define __HAL_RCC_GET_UART7_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL))) |
macro to get the UART7 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
- RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
- RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
- RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
Definition at line 3036 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_UART7_SOURCE [2/3]
| #define __HAL_RCC_GET_UART7_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
macro to get the UART7 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
- RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
- RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
- RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
- RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
- RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
Definition at line 2683 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_UART7_SOURCE [3/3]
| #define __HAL_RCC_GET_UART7_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
macro to get the UART7 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
- RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
- RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
- RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
- RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
- RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
Definition at line 2687 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_UART8_SOURCE [1/3]
| #define __HAL_RCC_GET_UART8_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL))) |
macro to get the UART8 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
- RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
- RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
- RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
Definition at line 3057 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_UART8_SOURCE [2/3]
| #define __HAL_RCC_GET_UART8_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
macro to get the UART8 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
- RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
- RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
- RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
- RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
- RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
Definition at line 2707 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_UART8_SOURCE [3/3]
| #define __HAL_RCC_GET_UART8_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
macro to get the UART8 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
- RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
- RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
- RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
- RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
- RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
Definition at line 2711 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_USART16910_SOURCE [1/2]
| #define __HAL_RCC_GET_USART16910_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL))) |
macro to get the USART1/6/9* /10* clock source.
- Return values
-
The clock source can be one of the following values: - RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock
- RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock
- RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock
- RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock
- RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock
- RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock
Definition at line 2478 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_USART16910_SOURCE [2/2]
| #define __HAL_RCC_GET_USART16910_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL))) |
macro to get the USART1/6/9* /10* clock source.
- Return values
-
The clock source can be one of the following values: - RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock
- RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock
- RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock
- RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock
- RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock
- RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock
Definition at line 2482 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_USART16_SOURCE [1/2]
| #define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE |
Definition at line 2480 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_USART16_SOURCE [2/2]
| #define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE |
Definition at line 2484 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_USART1_SOURCE [1/3]
| #define __HAL_RCC_GET_USART1_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL))) |
macro to get the USART1 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
- RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
- RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
- RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Definition at line 2910 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_USART1_SOURCE [2/3]
| #define __HAL_RCC_GET_USART1_SOURCE __HAL_RCC_GET_USART16_SOURCE |
macro to get the USART1 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
- RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
- RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
- RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
- RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
- RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Definition at line 2539 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_USART1_SOURCE [3/3]
| #define __HAL_RCC_GET_USART1_SOURCE __HAL_RCC_GET_USART16_SOURCE |
macro to get the USART1 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
- RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
- RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
- RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
- RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
- RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Definition at line 2543 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_USART234578_SOURCE [1/2]
| #define __HAL_RCC_GET_USART234578_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL))) |
macro to get the USART2/3/4/5/7/8 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
- RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
- RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock
- RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock
- RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock
- RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock
Definition at line 2514 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_USART234578_SOURCE [2/2]
| #define __HAL_RCC_GET_USART234578_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL))) |
macro to get the USART2/3/4/5/7/8 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
- RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
- RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock
- RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock
- RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock
- RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock
Definition at line 2518 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_USART2_SOURCE [1/3]
| #define __HAL_RCC_GET_USART2_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL))) |
macro to get the USART2 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
- RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
- RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
- RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Definition at line 2931 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_USART2_SOURCE [2/3]
| #define __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
macro to get the USART2 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
- RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
- RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
- RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
- RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
- RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Definition at line 2563 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_USART2_SOURCE [3/3]
| #define __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
macro to get the USART2 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
- RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
- RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
- RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
- RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
- RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Definition at line 2567 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_USART3_SOURCE [1/3]
| #define __HAL_RCC_GET_USART3_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL))) |
macro to get the USART3 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
- RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
- RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
- RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Definition at line 2952 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_USART3_SOURCE [2/3]
| #define __HAL_RCC_GET_USART3_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
macro to get the USART3 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
- RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
- RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
- RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
- RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
- RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Definition at line 2587 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_USART3_SOURCE [3/3]
| #define __HAL_RCC_GET_USART3_SOURCE __HAL_RCC_GET_USART234578_SOURCE |
macro to get the USART3 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
- RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
- RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
- RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
- RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
- RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Definition at line 2591 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_USART6_SOURCE [1/3]
| #define __HAL_RCC_GET_USART6_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL))) |
macro to get the USART6 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
- RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
- RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
- RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
Definition at line 3015 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_USART6_SOURCE [2/3]
| #define __HAL_RCC_GET_USART6_SOURCE __HAL_RCC_GET_USART16_SOURCE |
macro to get the USART6 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
- RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
- RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
- RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
- RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
- RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
Definition at line 2659 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_USART6_SOURCE [3/3]
| #define __HAL_RCC_GET_USART6_SOURCE __HAL_RCC_GET_USART16_SOURCE |
macro to get the USART6 clock source.
- Return values
-
The clock source can be one of the following values: - RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
- RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
- RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
- RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
- RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
- RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
Definition at line 2663 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_USB_SOURCE [1/2]
Macro to get the USB clock source.
- Return values
-
The clock source can be one of the following values: - RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock
- RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock
- RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock
Definition at line 3098 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_GET_USB_SOURCE [2/2]
Macro to get the USB clock source.
- Return values
-
The clock source can be one of the following values: - RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock
- RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock
- RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock
Definition at line 3102 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_I2C1235_CONFIG [1/2]
| #define __HAL_RCC_I2C1235_CONFIG | ( | __I2C1235CLKSource__ | ) | MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL, (uint32_t)(__I2C1235CLKSource__)) |
macro to configure the I2C1/2/3/5* clock (I2C123CLK).
- Parameters
-
<strong>I2C1235CLKSource</strong> specifies the I2C1/2/3/5* clock source. This parameter can be one of the following values: - RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock
- RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock
- RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock
- RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock
Definition at line 2273 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_I2C1235_CONFIG [2/2]
| #define __HAL_RCC_I2C1235_CONFIG | ( | __I2C1235CLKSource__ | ) | MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL, (uint32_t)(__I2C1235CLKSource__)) |
macro to configure the I2C1/2/3/5* clock (I2C123CLK).
- Parameters
-
<strong>I2C1235CLKSource</strong> specifies the I2C1/2/3/5* clock source. This parameter can be one of the following values: - RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock
- RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock
- RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock
- RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock
Definition at line 2273 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_I2C123_CONFIG [1/2]
| #define __HAL_RCC_I2C123_CONFIG __HAL_RCC_I2C1235_CONFIG |
Definition at line 2276 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_I2C123_CONFIG [2/2]
| #define __HAL_RCC_I2C123_CONFIG __HAL_RCC_I2C1235_CONFIG |
Definition at line 2276 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_I2C1_CONFIG [1/3]
| #define __HAL_RCC_I2C1_CONFIG | ( | __I2C1_CLKSOURCE__ | ) | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) |
Macro to configure the I2C1 clock (I2C1CLK).
- Parameters
-
<strong>I2C1_CLKSOURCE</strong> specifies the I2C1 clock source. This parameter can be one of the following values: - RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
- RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
- RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
Definition at line 2823 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_I2C1_CONFIG [2/3]
| #define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C123_CONFIG |
macro to configure the I2C1 clock (I2C1CLK).
- Parameters
-
<strong>I2C1CLKSource</strong> specifies the I2C1 clock source. This parameter can be one of the following values: - RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
- RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
- RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
- RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock
Definition at line 2310 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_I2C1_CONFIG [3/3]
| #define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C123_CONFIG |
macro to configure the I2C1 clock (I2C1CLK).
- Parameters
-
<strong>I2C1CLKSource</strong> specifies the I2C1 clock source. This parameter can be one of the following values: - RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
- RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
- RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
- RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock
Definition at line 2310 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_I2C2_CONFIG [1/3]
| #define __HAL_RCC_I2C2_CONFIG | ( | __I2C2_CLKSOURCE__ | ) | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) |
Macro to configure the I2C2 clock (I2C2CLK).
- Parameters
-
<strong>I2C2_CLKSOURCE</strong> specifies the I2C2 clock source. This parameter can be one of the following values: - RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
- RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
- RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Definition at line 2842 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_I2C2_CONFIG [2/3]
| #define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG |
macro to configure the I2C2 clock (I2C2CLK).
- Parameters
-
<strong>I2C2CLKSource</strong> specifies the I2C2 clock source. This parameter can be one of the following values: - RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
- RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
- RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
- RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock
Definition at line 2338 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_I2C2_CONFIG [3/3]
| #define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG |
macro to configure the I2C2 clock (I2C2CLK).
- Parameters
-
<strong>I2C2CLKSource</strong> specifies the I2C2 clock source. This parameter can be one of the following values: - RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
- RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
- RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
- RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock
Definition at line 2338 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_I2C3_CONFIG [1/3]
| #define __HAL_RCC_I2C3_CONFIG | ( | __I2C3_CLKSOURCE__ | ) | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) |
Macro to configure the I2C3 clock (I2C3CLK).
- Parameters
-
<strong>I2C3_CLKSOURCE</strong> specifies the I2C3 clock source. This parameter can be one of the following values: - RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
- RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
- RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Definition at line 2861 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_I2C3_CONFIG [2/3]
| #define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG |
macro to configure the I2C3 clock (I2C3CLK).
- Parameters
-
<strong>I2C3CLKSource</strong> specifies the I2C3 clock source. This parameter can be one of the following values: - RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
- RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
- RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
- RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock
Definition at line 2366 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_I2C3_CONFIG [3/3]
| #define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG |
macro to configure the I2C3 clock (I2C3CLK).
- Parameters
-
<strong>I2C3CLKSource</strong> specifies the I2C3 clock source. This parameter can be one of the following values: - RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
- RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
- RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
- RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock
Definition at line 2366 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_I2C4_CONFIG [1/3]
| #define __HAL_RCC_I2C4_CONFIG | ( | __I2C4_CLKSOURCE__ | ) | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) |
Macro to configure the I2C4 clock (I2C4CLK).
- Parameters
-
<strong>I2C4_CLKSOURCE</strong> specifies the I2C4 clock source. This parameter can be one of the following values: - RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
- RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
- RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
Definition at line 2880 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_I2C4_CONFIG [2/3]
| #define __HAL_RCC_I2C4_CONFIG | ( | __I2C4CLKSource__ | ) | MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__)) |
macro to configure the I2C4 clock (I2C4CLK).
- Parameters
-
<strong>I2C4CLKSource</strong> specifies the I2C4 clock source. This parameter can be one of the following values: - RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
- RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
- RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
- RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock
Definition at line 2395 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_I2C4_CONFIG [3/3]
| #define __HAL_RCC_I2C4_CONFIG | ( | __I2C4CLKSource__ | ) | MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__)) |
macro to configure the I2C4 clock (I2C4CLK).
- Parameters
-
<strong>I2C4CLKSource</strong> specifies the I2C4 clock source. This parameter can be one of the following values: - RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
- RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
- RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
- RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock
Definition at line 2395 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LPTIM1_CONFIG [1/3]
| #define __HAL_RCC_LPTIM1_CONFIG | ( | __LPTIM1_CLKSOURCE__ | ) | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) |
Macro to configure the LPTIM1 clock (LPTIM1CLK).
- Parameters
-
<strong>LPTIM1_CLKSOURCE</strong> specifies the LPTIM1 clock source. This parameter can be one of the following values: - RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
Definition at line 3068 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LPTIM1_CONFIG [2/3]
| #define __HAL_RCC_LPTIM1_CONFIG | ( | __LPTIM1CLKSource__ | ) | MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__)) |
macro to configure the LPTIM1 clock source.
- Parameters
-
<strong>LPTIM1CLKSource</strong> specifies the LPTIM1 clock source. This parameter can be one of the following values: - RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock
Definition at line 2810 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LPTIM1_CONFIG [3/3]
| #define __HAL_RCC_LPTIM1_CONFIG | ( | __LPTIM1CLKSource__ | ) | MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__)) |
macro to configure the LPTIM1 clock source.
- Parameters
-
<strong>LPTIM1CLKSource</strong> specifies the LPTIM1 clock source. This parameter can be one of the following values: - RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
- RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock
Definition at line 2814 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LPTIM2_CONFIG [1/2]
| #define __HAL_RCC_LPTIM2_CONFIG | ( | __LPTIM2CLKSource__ | ) | MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__)) |
macro to configure the LPTIM2 clock source.
- Parameters
-
<strong>LPTIM2CLKSource</strong> specifies the LPTIM2 clock source. This parameter can be one of the following values: - RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
- RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
- RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
- RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
- RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
- RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock
Definition at line 2844 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LPTIM2_CONFIG [2/2]
| #define __HAL_RCC_LPTIM2_CONFIG | ( | __LPTIM2CLKSource__ | ) | MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__)) |
macro to configure the LPTIM2 clock source.
- Parameters
-
<strong>LPTIM2CLKSource</strong> specifies the LPTIM2 clock source. This parameter can be one of the following values: - RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
- RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
- RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
- RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
- RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
- RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock
Definition at line 2848 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LPTIM345_CONFIG [1/2]
| #define __HAL_RCC_LPTIM345_CONFIG | ( | __LPTIM345CLKSource__ | ) | MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM345CLKSource__)) |
macro to configure the LPTIM3/4/5 clock source.
- Parameters
-
<strong>LPTIM345CLKSource</strong> specifies the LPTIM3/4/5 clock source. - RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
- RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
- RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
- RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
- RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
- RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock
Definition at line 2877 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LPTIM345_CONFIG [2/2]
| #define __HAL_RCC_LPTIM345_CONFIG | ( | __LPTIM345CLKSource__ | ) | MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM345CLKSource__)) |
macro to configure the LPTIM3/4/5 clock source.
- Parameters
-
<strong>LPTIM345CLKSource</strong> specifies the LPTIM3/4/5 clock source. - RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
- RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
- RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
- RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
- RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
- RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock
Definition at line 2881 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LPTIM3_CONFIG [1/2]
| #define __HAL_RCC_LPTIM3_CONFIG __HAL_RCC_LPTIM345_CONFIG |
macro to configure the LPTIM3 clock source.
- Parameters
-
<strong>LPTIM3CLKSource</strong> specifies the LPTIM3 clock source. - RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
- RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
- RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
- RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
- RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
- RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock
Definition at line 2906 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LPTIM3_CONFIG [2/2]
| #define __HAL_RCC_LPTIM3_CONFIG __HAL_RCC_LPTIM345_CONFIG |
macro to configure the LPTIM3 clock source.
- Parameters
-
<strong>LPTIM3CLKSource</strong> specifies the LPTIM3 clock source. - RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
- RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
- RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
- RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
- RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
- RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock
Definition at line 2910 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LPUART1_CONFIG [1/2]
| #define __HAL_RCC_LPUART1_CONFIG | ( | __LPUART1CLKSource__ | ) | MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__)) |
macro to configure the LPUART1 clock (LPUART1CLK).
- Parameters
-
<strong>LPUART1CLKSource</strong> specifies the LPUART1 clock source. This parameter can be one of the following values: - RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
- RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
- RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
- RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
- RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
- RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
Definition at line 2776 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LPUART1_CONFIG [2/2]
| #define __HAL_RCC_LPUART1_CONFIG | ( | __LPUART1CLKSource__ | ) | MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__)) |
macro to configure the LPUART1 clock (LPUART1CLK).
- Parameters
-
<strong>LPUART1CLKSource</strong> specifies the LPUART1 clock source. This parameter can be one of the following values: - RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
- RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
- RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
- RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
- RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
- RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
Definition at line 2780 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG [1/2]
| #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG | ( | ) | WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) |
Clear the RCC LSE CSS EXTI flag.
- Return values
-
None.
Definition at line 3707 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG [2/2]
| #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG | ( | ) | WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) |
Clear the RCC LSE CSS EXTI flag.
- Return values
-
None.
Definition at line 3711 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT [1/2]
| #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT | ( | ) | CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) |
Disable the RCC LSE CSS Event Line.
- Return values
-
None.
Definition at line 3623 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT [2/2]
| #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT | ( | ) | CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) |
Disable the RCC LSE CSS Event Line.
- Return values
-
None.
Definition at line 3627 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE [1/2]
| #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE | ( | ) | CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) |
Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
- Return values
-
None.
Definition at line 3662 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE [2/2]
| #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE | ( | ) | CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) |
Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
- Return values
-
None.
Definition at line 3666 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_DISABLE_IT [1/2]
| #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT | ( | ) | CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) |
Disable the RCC LSE CSS Extended Interrupt Line.
- Return values
-
None
Definition at line 3611 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_DISABLE_IT [2/2]
| #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT | ( | ) | CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) |
Disable the RCC LSE CSS Extended Interrupt Line.
- Return values
-
None
Definition at line 3615 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE [1/2]
| #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE | ( | ) | CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) |
Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
- Return values
-
None.
Definition at line 3675 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE [2/2]
| #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE | ( | ) | CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) |
Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
- Return values
-
None.
Definition at line 3679 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE [1/2]
| #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE | ( | ) |
Value:
do { \
__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
__HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
- Return values
-
None.
Definition at line 3691 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE [2/2]
| #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE | ( | ) |
Value:
do { \
__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
__HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
- Return values
-
None.
Definition at line 3695 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT [1/2]
| #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT | ( | ) | SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) |
Enable the RCC LSE CSS Event Line.
- Return values
-
None.
Definition at line 3617 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT [2/2]
| #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT | ( | ) | SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) |
Enable the RCC LSE CSS Event Line.
- Return values
-
None.
Definition at line 3621 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE [1/2]
| #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE | ( | ) | SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) |
Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
- Return values
-
None.
Definition at line 3655 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE [2/2]
| #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE | ( | ) | SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) |
Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
- Return values
-
None.
Definition at line 3659 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_ENABLE_IT [1/2]
| #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT | ( | ) | SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) |
Enable the RCC LSE CSS Extended Interrupt Line.
- Return values
-
None
Definition at line 3605 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_ENABLE_IT [2/2]
| #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT | ( | ) | SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) |
Enable the RCC LSE CSS Extended Interrupt Line.
- Return values
-
None
Definition at line 3609 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE [1/2]
| #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE | ( | ) | SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) |
Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
- Return values
-
None.
Definition at line 3669 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE [2/2]
| #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE | ( | ) | SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) |
Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
- Return values
-
None.
Definition at line 3673 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE [1/2]
| #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE | ( | ) |
Value:
do { \
__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
__HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
- Return values
-
None.
Definition at line 3681 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE [2/2]
| #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE | ( | ) |
Value:
do { \
__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
__HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
- Return values
-
None.
Definition at line 3685 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT [1/2]
| #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT | ( | ) | SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) |
Generate a Software interrupt on the RCC LSE CSS EXTI line.
- Return values
-
None.
Definition at line 3726 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT [2/2]
| #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT | ( | ) | SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) |
Generate a Software interrupt on the RCC LSE CSS EXTI line.
- Return values
-
None.
Definition at line 3730 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_GET_FLAG [1/2]
| #define __HAL_RCC_LSECSS_EXTI_GET_FLAG | ( | ) | (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) |
Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
- Return values
-
EXTI RCC LSE CSS Line Status.
Definition at line 3701 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_LSECSS_EXTI_GET_FLAG [2/2]
| #define __HAL_RCC_LSECSS_EXTI_GET_FLAG | ( | ) | (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) |
Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
- Return values
-
EXTI RCC LSE CSS Line Status.
Definition at line 3705 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL2_CONFIG [1/2]
| #define __HAL_RCC_PLL2_CONFIG | ( | __PLL2M__, | |
| __PLL2N__, | |||
| __PLL2P__, | |||
| __PLL2Q__, | |||
| __PLL2R__ | |||
| ) |
Value:
do{ \
MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U)); \
WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \
((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \
} while(0)
Macro to configures the PLL2 multiplication and division factors.
- Note
- This function must be used only when PLL2 is disabled.
- Parameters
-
<strong>PLL2M</strong> specifies the division factor for PLL2 VCO input clock This parameter must be a number between 1 and 63.
- Note
- You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 16 MHz.
- Parameters
-
<strong>PLL2N</strong> specifies the multiplication factor for PLL2 VCO output clock This parameter must be a number between 4 and 512 or between 8 and 420(*).
- Note
- You have to set the PLL2N parameter correctly to ensure that the VCO output frequency is between 150 and 420 MHz (when in medium VCO range) or between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
- Parameters
-
<strong>PLL2P</strong> specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128. <strong>PLL2Q</strong> specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128. <strong>PLL2R</strong> specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128.
- Note
- To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible value to PLL2P, PLL2Q or PLL2R parameters.
- Return values
-
None (*) : For stm32h7a3xx and stm32h7b3xx family lines.
Definition at line 1831 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL2_CONFIG [2/2]
| #define __HAL_RCC_PLL2_CONFIG | ( | __PLL2M__, | |
| __PLL2N__, | |||
| __PLL2P__, | |||
| __PLL2Q__, | |||
| __PLL2R__ | |||
| ) |
Value:
do{ \
MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U)); \
WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \
((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \
} while(0)
Macro to configures the PLL2 multiplication and division factors.
- Note
- This function must be used only when PLL2 is disabled.
- Parameters
-
<strong>PLL2M</strong> specifies the division factor for PLL2 VCO input clock This parameter must be a number between 1 and 63.
- Note
- You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 16 MHz.
- Parameters
-
<strong>PLL2N</strong> specifies the multiplication factor for PLL2 VCO output clock This parameter must be a number between 4 and 512 or between 8 and 420(*).
- Note
- You have to set the PLL2N parameter correctly to ensure that the VCO output frequency is between 150 and 420 MHz (when in medium VCO range) or between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
- Parameters
-
<strong>PLL2P</strong> specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128. <strong>PLL2Q</strong> specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128. <strong>PLL2R</strong> specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128.
- Note
- To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible value to PLL2P, PLL2Q or PLL2R parameters.
- Return values
-
None (*) : For stm32h7a3xx and stm32h7b3xx family lines.
Definition at line 1831 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL2_DISABLE [1/2]
| #define __HAL_RCC_PLL2_DISABLE | ( | ) | CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON) |
Definition at line 1768 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL2_DISABLE [2/2]
| #define __HAL_RCC_PLL2_DISABLE | ( | ) | CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON) |
Definition at line 1768 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL2_ENABLE [1/2]
| #define __HAL_RCC_PLL2_ENABLE | ( | ) | SET_BIT(RCC->CR, RCC_CR_PLL2ON) |
Macros to enable or disable PLL2.
- Note
- After enabling PLL2, the application software should wait on PLL2RDY flag to be set indicating that PLL2 clock is stable and can be used as kernel clock source.
- PLL2 is disabled by hardware when entering STOP and STANDBY modes.
Definition at line 1767 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL2_ENABLE [2/2]
| #define __HAL_RCC_PLL2_ENABLE | ( | ) | SET_BIT(RCC->CR, RCC_CR_PLL2ON) |
Macros to enable or disable PLL2.
- Note
- After enabling PLL2, the application software should wait on PLL2RDY flag to be set indicating that PLL2 clock is stable and can be used as kernel clock source.
- PLL2 is disabled by hardware when entering STOP and STANDBY modes.
Definition at line 1767 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL2_VCIRANGE [1/2]
| #define __HAL_RCC_PLL2_VCIRANGE | ( | __RCC_PLL2VCIRange__ | ) | MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__)) |
Macro to select the PLL2 reference frequency range.
- Parameters
-
<strong>RCC_PLL2VCIRange</strong> specifies the PLL2 input frequency range This parameter can be one of the following values: - RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz
- RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz
- RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz
- RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz
- Return values
-
None
Definition at line 1866 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL2_VCIRANGE [2/2]
| #define __HAL_RCC_PLL2_VCIRANGE | ( | __RCC_PLL2VCIRange__ | ) | MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__)) |
Macro to select the PLL2 reference frequency range.
- Parameters
-
<strong>RCC_PLL2VCIRange</strong> specifies the PLL2 input frequency range This parameter can be one of the following values: - RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz
- RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz
- RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz
- RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz
- Return values
-
None
Definition at line 1866 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL2_VCORANGE [1/2]
| #define __HAL_RCC_PLL2_VCORANGE | ( | __RCC_PLL2VCORange__ | ) | MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__)) |
Macro to select the PLL2 reference frequency range.
- Parameters
-
<strong>RCC_PLL2VCORange</strong> Specifies the PLL2 input frequency range This parameter can be one of the following values: - RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)
- RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz
- Return values
-
None
Definition at line 1880 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL2_VCORANGE [2/2]
| #define __HAL_RCC_PLL2_VCORANGE | ( | __RCC_PLL2VCORange__ | ) | MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__)) |
Macro to select the PLL2 reference frequency range.
- Parameters
-
<strong>RCC_PLL2VCORange</strong> Specifies the PLL2 input frequency range This parameter can be one of the following values: - RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)
- RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz
- Return values
-
None
Definition at line 1880 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL2CLKOUT_DISABLE [1/2]
| #define __HAL_RCC_PLL2CLKOUT_DISABLE | ( | __RCC_PLL2ClockOut__ | ) | CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) |
Definition at line 1788 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL2CLKOUT_DISABLE [2/2]
| #define __HAL_RCC_PLL2CLKOUT_DISABLE | ( | __RCC_PLL2ClockOut__ | ) | CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) |
Definition at line 1788 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL2CLKOUT_ENABLE [1/2]
| #define __HAL_RCC_PLL2CLKOUT_ENABLE | ( | __RCC_PLL2ClockOut__ | ) | SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) |
Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)
- Note
- Enabling/disabling those Clocks can be done only when the PLL2 is disabled, This is mainly used to save Power.
- Parameters
-
<strong>RCC_PLL2ClockOut</strong> Specifies the PLL2 clock to be outputted This parameter can be one of the following values: - RCC_PLL2_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
- RCC_PLL2_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
- RCC_PLL2_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
- Return values
-
None
Definition at line 1786 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL2CLKOUT_ENABLE [2/2]
| #define __HAL_RCC_PLL2CLKOUT_ENABLE | ( | __RCC_PLL2ClockOut__ | ) | SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) |
Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)
- Note
- Enabling/disabling those Clocks can be done only when the PLL2 is disabled, This is mainly used to save Power.
- Parameters
-
<strong>RCC_PLL2ClockOut</strong> Specifies the PLL2 clock to be outputted This parameter can be one of the following values: - RCC_PLL2_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
- RCC_PLL2_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
- RCC_PLL2_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
- Return values
-
None
Definition at line 1786 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL2FRACN_CONFIG [1/2]
| #define __HAL_RCC_PLL2FRACN_CONFIG | ( | __RCC_PLL2FRACN__ | ) | MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos)) |
Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor.
- Note
- These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO
- Parameters
-
<strong>RCC_PLL2FRACN</strong> Specifies Fractional Part Of The Multiplication factor for PLL2 VCO It should be a value between 0 and 8191
- Note
- Warning: the software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is: 192 to 836 MHz or 128 to 560 MHz(*) if PLL2VCOSEL = 0 150 to 420 MHz if PLL2VCOSEL = 1.
(*) : For stm32h7a3xx and stm32h7b3xx family lines.
- Return values
-
None
Definition at line 1854 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL2FRACN_CONFIG [2/2]
| #define __HAL_RCC_PLL2FRACN_CONFIG | ( | __RCC_PLL2FRACN__ | ) | MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos)) |
Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor.
- Note
- These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO
- Parameters
-
<strong>RCC_PLL2FRACN</strong> Specifies Fractional Part Of The Multiplication factor for PLL2 VCO It should be a value between 0 and 8191
- Note
- Warning: the software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is: 192 to 836 MHz or 128 to 560 MHz(*) if PLL2VCOSEL = 0 150 to 420 MHz if PLL2VCOSEL = 1.
(*) : For stm32h7a3xx and stm32h7b3xx family lines.
- Return values
-
None
Definition at line 1854 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL2FRACN_DISABLE [1/2]
| #define __HAL_RCC_PLL2FRACN_DISABLE | ( | ) | CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) |
Definition at line 1797 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL2FRACN_DISABLE [2/2]
| #define __HAL_RCC_PLL2FRACN_DISABLE | ( | ) | CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) |
Definition at line 1797 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL2FRACN_ENABLE [1/2]
| #define __HAL_RCC_PLL2FRACN_ENABLE | ( | ) | SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) |
Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO.
- Note
- Enabling/disabling Fractional Part can be any time without the need to stop the PLL2
- Return values
-
None
Definition at line 1795 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL2FRACN_ENABLE [2/2]
| #define __HAL_RCC_PLL2FRACN_ENABLE | ( | ) | SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) |
Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO.
- Note
- Enabling/disabling Fractional Part can be any time without the need to stop the PLL2
- Return values
-
None
Definition at line 1795 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL3_CONFIG [1/2]
| #define __HAL_RCC_PLL3_CONFIG | ( | __PLL3M__, | |
| __PLL3N__, | |||
| __PLL3P__, | |||
| __PLL3Q__, | |||
| __PLL3R__ | |||
| ) |
Value:
WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \
((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \
} while(0)
Macro to configures the PLL3 multiplication and division factors.
- Note
- This function must be used only when PLL3 is disabled.
- Parameters
-
<strong>PLL3M</strong> specifies the division factor for PLL3 VCO input clock This parameter must be a number between 1 and 63.
- Note
- You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 16 MHz.
- Parameters
-
<strong>PLL3N</strong> specifies the multiplication factor for PLL3 VCO output clock This parameter must be a number between 4 and 512.
- Note
- You have to set the PLL3N parameter correctly to ensure that the VCO output frequency is between 150 and 420 MHz (when in medium VCO range) or between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
- Parameters
-
<strong>PLL3P</strong> specifies the division factor for peripheral kernel clocks This parameter must be a number between 2 and 128 (where odd numbers not allowed) <strong>PLL3Q</strong> specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128 <strong>PLL3R</strong> specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128
- Note
- To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible value to PLL3P, PLL3Q or PLL3R parameters.
- Return values
-
None (*) : For stm32h7a3xx and stm32h7b3xx family lines.
Definition at line 1953 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL3_CONFIG [2/2]
| #define __HAL_RCC_PLL3_CONFIG | ( | __PLL3M__, | |
| __PLL3N__, | |||
| __PLL3P__, | |||
| __PLL3Q__, | |||
| __PLL3R__ | |||
| ) |
Value:
WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \
((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \
} while(0)
Macro to configures the PLL3 multiplication and division factors.
- Note
- This function must be used only when PLL3 is disabled.
- Parameters
-
<strong>PLL3M</strong> specifies the division factor for PLL3 VCO input clock This parameter must be a number between 1 and 63.
- Note
- You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 16 MHz.
- Parameters
-
<strong>PLL3N</strong> specifies the multiplication factor for PLL3 VCO output clock This parameter must be a number between 4 and 512.
- Note
- You have to set the PLL3N parameter correctly to ensure that the VCO output frequency is between 150 and 420 MHz (when in medium VCO range) or between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
- Parameters
-
<strong>PLL3P</strong> specifies the division factor for peripheral kernel clocks This parameter must be a number between 2 and 128 (where odd numbers not allowed) <strong>PLL3Q</strong> specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128 <strong>PLL3R</strong> specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128
- Note
- To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible value to PLL3P, PLL3Q or PLL3R parameters.
- Return values
-
None (*) : For stm32h7a3xx and stm32h7b3xx family lines.
Definition at line 1953 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL3_DISABLE [1/2]
| #define __HAL_RCC_PLL3_DISABLE | ( | ) | CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON) |
Definition at line 1890 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL3_DISABLE [2/2]
| #define __HAL_RCC_PLL3_DISABLE | ( | ) | CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON) |
Definition at line 1890 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL3_ENABLE [1/2]
| #define __HAL_RCC_PLL3_ENABLE | ( | ) | SET_BIT(RCC->CR, RCC_CR_PLL3ON) |
Macros to enable or disable the main PLL3.
- Note
- After enabling PLL3, the application software should wait on PLL3RDY flag to be set indicating that PLL3 clock is stable and can be used as kernel clock source.
- PLL3 is disabled by hardware when entering STOP and STANDBY modes.
Definition at line 1889 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL3_ENABLE [2/2]
| #define __HAL_RCC_PLL3_ENABLE | ( | ) | SET_BIT(RCC->CR, RCC_CR_PLL3ON) |
Macros to enable or disable the main PLL3.
- Note
- After enabling PLL3, the application software should wait on PLL3RDY flag to be set indicating that PLL3 clock is stable and can be used as kernel clock source.
- PLL3 is disabled by hardware when entering STOP and STANDBY modes.
Definition at line 1889 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL3_VCIRANGE [1/2]
| #define __HAL_RCC_PLL3_VCIRANGE | ( | __RCC_PLL3VCIRange__ | ) | MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__)) |
Macro to select the PLL3 reference frequency range.
- Parameters
-
<strong>RCC_PLL3VCIRange</strong> specifies the PLL1 input frequency range This parameter can be one of the following values: - RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz
- RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz
- RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz
- RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz
- Return values
-
None
Definition at line 1988 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL3_VCIRANGE [2/2]
| #define __HAL_RCC_PLL3_VCIRANGE | ( | __RCC_PLL3VCIRange__ | ) | MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__)) |
Macro to select the PLL3 reference frequency range.
- Parameters
-
<strong>RCC_PLL3VCIRange</strong> specifies the PLL1 input frequency range This parameter can be one of the following values: - RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz
- RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz
- RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz
- RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz
- Return values
-
None
Definition at line 1988 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL3_VCORANGE [1/2]
| #define __HAL_RCC_PLL3_VCORANGE | ( | __RCC_PLL3VCORange__ | ) | MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__)) |
Macro to select the PLL3 reference frequency range.
- Parameters
-
<strong>RCC_PLL3VCORange</strong> specifies the PLL1 input frequency range This parameter can be one of the following values: - RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)
- RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz
- Return values
-
None
Definition at line 2002 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL3_VCORANGE [2/2]
| #define __HAL_RCC_PLL3_VCORANGE | ( | __RCC_PLL3VCORange__ | ) | MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__)) |
Macro to select the PLL3 reference frequency range.
- Parameters
-
<strong>RCC_PLL3VCORange</strong> specifies the PLL1 input frequency range This parameter can be one of the following values: - RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)
- RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz
- Return values
-
None
Definition at line 2002 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL3CLKOUT_DISABLE [1/2]
| #define __HAL_RCC_PLL3CLKOUT_DISABLE | ( | __RCC_PLL3ClockOut__ | ) | CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) |
Definition at line 1919 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL3CLKOUT_DISABLE [2/2]
| #define __HAL_RCC_PLL3CLKOUT_DISABLE | ( | __RCC_PLL3ClockOut__ | ) | CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) |
Definition at line 1919 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL3CLKOUT_ENABLE [1/2]
| #define __HAL_RCC_PLL3CLKOUT_ENABLE | ( | __RCC_PLL3ClockOut__ | ) | SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) |
Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)
- Note
- Enabling/disabling those Clocks can be done only when the PLL3 is disabled, This is mainly used to save Power.
- Parameters
-
<strong>RCC_PLL3ClockOut</strong> specifies the PLL3 clock to be outputted This parameter can be one of the following values: - RCC_PLL3_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
- RCC_PLL3_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
- RCC_PLL3_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
- Return values
-
None
Definition at line 1917 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL3CLKOUT_ENABLE [2/2]
| #define __HAL_RCC_PLL3CLKOUT_ENABLE | ( | __RCC_PLL3ClockOut__ | ) | SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) |
Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)
- Note
- Enabling/disabling those Clocks can be done only when the PLL3 is disabled, This is mainly used to save Power.
- Parameters
-
<strong>RCC_PLL3ClockOut</strong> specifies the PLL3 clock to be outputted This parameter can be one of the following values: - RCC_PLL3_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
- RCC_PLL3_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
- RCC_PLL3_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
- Return values
-
None
Definition at line 1917 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL3FRACN_CONFIG [1/2]
| #define __HAL_RCC_PLL3FRACN_CONFIG | ( | __RCC_PLL3FRACN__ | ) | MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos) |
Macro to configures PLL3 clock Fractional Part of The Multiplication Factor.
- Note
- These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO
- Parameters
-
<strong>RCC_PLL3FRACN</strong> specifies Fractional Part Of The Multiplication Factor for PLL3 VCO It should be a value between 0 and 8191
- Note
- Warning: the software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is: 192 to 836 MHz or 128 to 560 MHz(*) if PLL3VCOSEL = 0 150 to 420 MHz if PLL3VCOSEL = 1.
(*) : For stm32h7a3xx and stm32h7b3xx family lines.
- Return values
-
None
Definition at line 1977 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL3FRACN_CONFIG [2/2]
| #define __HAL_RCC_PLL3FRACN_CONFIG | ( | __RCC_PLL3FRACN__ | ) | MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos) |
Macro to configures PLL3 clock Fractional Part of The Multiplication Factor.
- Note
- These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO
- Parameters
-
<strong>RCC_PLL3FRACN</strong> specifies Fractional Part Of The Multiplication Factor for PLL3 VCO It should be a value between 0 and 8191
- Note
- Warning: the software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is: 192 to 836 MHz or 128 to 560 MHz(*) if PLL3VCOSEL = 0 150 to 420 MHz if PLL3VCOSEL = 1.
(*) : For stm32h7a3xx and stm32h7b3xx family lines.
- Return values
-
None
Definition at line 1977 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL3FRACN_DISABLE [1/2]
| #define __HAL_RCC_PLL3FRACN_DISABLE | ( | ) | CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) |
Definition at line 1899 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL3FRACN_DISABLE [2/2]
| #define __HAL_RCC_PLL3FRACN_DISABLE | ( | ) | CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) |
Definition at line 1899 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL3FRACN_ENABLE [1/2]
| #define __HAL_RCC_PLL3FRACN_ENABLE | ( | ) | SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) |
Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO.
- Note
- Enabling/disabling Fractional Part can be any time without the need to stop the PLL3
- Return values
-
None
Definition at line 1897 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL3FRACN_ENABLE [2/2]
| #define __HAL_RCC_PLL3FRACN_ENABLE | ( | ) | SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) |
Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO.
- Note
- Enabling/disabling Fractional Part can be any time without the need to stop the PLL3
- Return values
-
None
Definition at line 1897 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL_CONFIG [1/4]
| #define __HAL_RCC_PLL_CONFIG | ( | __RCC_PLLSource__, | |
| __PLLM__, | |||
| __PLLN__, | |||
| __PLLP__, | |||
| __PLLQ__ | |||
| ) |
Value:
(RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \
((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) | \
((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)))
Macro to configure the main PLL clock source, multiplication and division factors.
- Note
- This function must be used only when the main PLL is disabled.
- Parameters
-
<strong>RCC_PLLSource</strong> specifies the PLL entry clock source. This parameter can be one of the following values: - RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
- RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
- Note
- This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
- Parameters
-
<strong>PLLM</strong> specifies the division factor for PLL VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.
- Note
- You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.
- Parameters
-
<strong>PLLN</strong> specifies the multiplication factor for PLL VCO output clock This parameter must be a number between Min_Data = 50 and Max_Data = 432.
- Note
- You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 100 and 432 MHz.
- Parameters
-
<strong>PLLP</strong> specifies the division factor for main system clock (SYSCLK) This parameter must be a number in the range {2, 4, 6, or 8}.
- Note
- You have to set the PLLP parameter correctly to not exceed 216 MHz on the System clock frequency.
- Parameters
-
<strong>PLLQ</strong> specifies the division factor for OTG FS, SDMMC and RNG clocks This parameter must be a number between Min_Data = 2 and Max_Data = 15.
- Note
- If the USB OTG FS is used in your application, you have to set the PLLQ parameter correctly to have 48 MHz clock for the USB. However, the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work correctly.
Definition at line 2577 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL_CONFIG [2/4]
| #define __HAL_RCC_PLL_CONFIG | ( | __RCC_PLLSource__, | |
| __PLLM__, | |||
| __PLLN__, | |||
| __PLLP__, | |||
| __PLLQ__ | |||
| ) |
Value:
(RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \
((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \
((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)))
Macro to configure the main PLL clock source, multiplication and division factors.
- Note
- This function must be used only when the main PLL is disabled.
- Parameters
-
<strong>RCC_PLLSource</strong> specifies the PLL entry clock source. This parameter can be one of the following values: - RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
- RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
- Note
- This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
- Parameters
-
<strong>PLLM</strong> specifies the division factor for PLL VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.
- Note
- You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.
- Parameters
-
<strong>PLLN</strong> specifies the multiplication factor for PLL VCO output clock This parameter must be a number between Min_Data = 50 and Max_Data = 432 Except for STM32F411xE devices where Min_Data = 192.
- Note
- You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 100 and 432 MHz, Except for STM32F411xE devices where frequency is between 192 and 432 MHz.
- Parameters
-
<strong>PLLP</strong> specifies the division factor for main system clock (SYSCLK) This parameter must be a number in the range {2, 4, 6, or 8}. <strong>PLLQ</strong> specifies the division factor for OTG FS, SDIO and RNG clocks This parameter must be a number between Min_Data = 2 and Max_Data = 15.
- Note
- If the USB OTG FS is used in your application, you have to set the PLLQ parameter correctly to have 48 MHz clock for the USB. However, the SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly.
Definition at line 5810 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL_CONFIG [3/4]
| #define __HAL_RCC_PLL_CONFIG | ( | __RCC_PLLSource__, | |
| __PLLM__, | |||
| __PLLN__, | |||
| __PLLP__, | |||
| __PLLQ__ | |||
| ) |
Value:
(RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \
((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \
((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)))
Macro to configure the main PLL clock source, multiplication and division factors.
- Note
- This function must be used only when the main PLL is disabled.
- Parameters
-
<strong>RCC_PLLSource</strong> specifies the PLL entry clock source. This parameter can be one of the following values: - RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
- RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
- Note
- This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
- Parameters
-
<strong>PLLM</strong> specifies the division factor for PLL VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.
- Note
- You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.
- Parameters
-
<strong>PLLN</strong> specifies the multiplication factor for PLL VCO output clock This parameter must be a number between Min_Data = 50 and Max_Data = 432 Except for STM32F411xE devices where Min_Data = 192.
- Note
- You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 100 and 432 MHz, Except for STM32F411xE devices where frequency is between 192 and 432 MHz.
- Parameters
-
<strong>PLLP</strong> specifies the division factor for main system clock (SYSCLK) This parameter must be a number in the range {2, 4, 6, or 8}. <strong>PLLQ</strong> specifies the division factor for OTG FS, SDIO and RNG clocks This parameter must be a number between Min_Data = 2 and Max_Data = 15.
- Note
- If the USB OTG FS is used in your application, you have to set the PLLQ parameter correctly to have 48 MHz clock for the USB. However, the SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly.
Definition at line 5810 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLL_CONFIG [4/4]
| #define __HAL_RCC_PLL_CONFIG | ( | __RCC_PLLSource__, | |
| __PLLM__, | |||
| __PLLN__, | |||
| __PLLP__, | |||
| __PLLQ__ | |||
| ) |
Value:
(RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \
((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \
((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)))
Macro to configure the main PLL clock source, multiplication and division factors.
- Note
- This function must be used only when the main PLL is disabled.
- Parameters
-
<strong>RCC_PLLSource</strong> specifies the PLL entry clock source. This parameter can be one of the following values: - RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
- RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
- Note
- This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
- Parameters
-
<strong>PLLM</strong> specifies the division factor for PLL VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.
- Note
- You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.
- Parameters
-
<strong>PLLN</strong> specifies the multiplication factor for PLL VCO output clock This parameter must be a number between Min_Data = 50 and Max_Data = 432 Except for STM32F411xE devices where Min_Data = 192.
- Note
- You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 100 and 432 MHz, Except for STM32F411xE devices where frequency is between 192 and 432 MHz.
- Parameters
-
<strong>PLLP</strong> specifies the division factor for main system clock (SYSCLK) This parameter must be a number in the range {2, 4, 6, or 8}. <strong>PLLQ</strong> specifies the division factor for OTG FS, SDIO and RNG clocks This parameter must be a number between Min_Data = 2 and Max_Data = 15.
- Note
- If the USB OTG FS is used in your application, you have to set the PLLQ parameter correctly to have 48 MHz clock for the USB. However, the SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly.
Definition at line 5810 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLLI2S_CONFIG [1/4]
| #define __HAL_RCC_PLLI2S_CONFIG | ( | __PLLI2SN__, | |
| __PLLI2SP__, | |||
| __PLLI2SQ__, | |||
| __PLLI2SR__ | |||
| ) |
Value:
(RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\
((__PLLI2SP__) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\
((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\
((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))
Macro to configure the PLLI2S clock multiplication and division factors.
- Note
- This macro must be used only when the PLLI2S is disabled.
- PLLI2S clock source is common with the main PLL (configured in HAL_RCC_ClockConfig() API)
- Parameters
-
<strong>PLLI2SN</strong> specifies the multiplication factor for PLLI2S VCO output clock. This parameter must be a number between Min_Data = 50 and Max_Data = 432.
- Note
- You have to set the PLLI2SN parameter correctly to ensure that the VCO output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
- Parameters
-
<strong>PLLI2SP</strong> specifies the division factor for SPDDIF-RX clock. This parameter can be a value of RCC PLLI2SP Clock Divider. <strong>PLLI2SQ</strong> specifies the division factor for SAI clock. This parameter must be a number between Min_Data = 2 and Max_Data = 15. <strong>PLLI2SR</strong> specifies the division factor for I2S clock This parameter must be a number between Min_Data = 2 and Max_Data = 7.
- Note
- You have to set the PLLI2SR parameter correctly to not exceed 192 MHz on the I2S clock frequency.
Definition at line 2684 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLLI2S_CONFIG [2/4]
| #define __HAL_RCC_PLLI2S_CONFIG | ( | __PLLI2SN__, | |
| __PLLI2SR__ | |||
| ) |
Value:
(RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\
((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
Macro to configure the PLLI2S clock multiplication and division factors .
- Note
- This macro must be used only when the PLLI2S is disabled.
- PLLI2S clock source is common with the main PLL (configured in HAL_RCC_ClockConfig() API).
- Parameters
-
<strong>PLLI2SN</strong> specifies the multiplication factor for PLLI2S VCO output clock This parameter must be a number between Min_Data = 50 and Max_Data = 432.
- Note
- You have to set the PLLI2SN parameter correctly to ensure that the VCO output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
- Parameters
-
<strong>PLLI2SR</strong> specifies the division factor for I2S clock This parameter must be a number between Min_Data = 2 and Max_Data = 7.
- Note
- You have to set the PLLI2SR parameter correctly to not exceed 192 MHz on the I2S clock frequency.
Definition at line 5914 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLLI2S_CONFIG [3/4]
| #define __HAL_RCC_PLLI2S_CONFIG | ( | __PLLI2SN__, | |
| __PLLI2SR__ | |||
| ) |
Value:
(RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\
((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
Macro to configure the PLLI2S clock multiplication and division factors .
- Note
- This macro must be used only when the PLLI2S is disabled.
- PLLI2S clock source is common with the main PLL (configured in HAL_RCC_ClockConfig() API).
- Parameters
-
<strong>PLLI2SN</strong> specifies the multiplication factor for PLLI2S VCO output clock This parameter must be a number between Min_Data = 50 and Max_Data = 432.
- Note
- You have to set the PLLI2SN parameter correctly to ensure that the VCO output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
- Parameters
-
<strong>PLLI2SR</strong> specifies the division factor for I2S clock This parameter must be a number between Min_Data = 2 and Max_Data = 7.
- Note
- You have to set the PLLI2SR parameter correctly to not exceed 192 MHz on the I2S clock frequency.
Definition at line 5914 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLLI2S_CONFIG [4/4]
| #define __HAL_RCC_PLLI2S_CONFIG | ( | __PLLI2SN__, | |
| __PLLI2SR__ | |||
| ) |
Value:
(RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\
((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
Macro to configure the PLLI2S clock multiplication and division factors .
- Note
- This macro must be used only when the PLLI2S is disabled.
- PLLI2S clock source is common with the main PLL (configured in HAL_RCC_ClockConfig() API).
- Parameters
-
<strong>PLLI2SN</strong> specifies the multiplication factor for PLLI2S VCO output clock This parameter must be a number between Min_Data = 50 and Max_Data = 432.
- Note
- You have to set the PLLI2SN parameter correctly to ensure that the VCO output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
- Parameters
-
<strong>PLLI2SR</strong> specifies the division factor for I2S clock This parameter must be a number between Min_Data = 2 and Max_Data = 7.
- Note
- You have to set the PLLI2SR parameter correctly to not exceed 192 MHz on the I2S clock frequency.
Definition at line 5914 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG
| #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG | ( | __PLLI2SDivQ__ | ) | (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1)) |
Macro to configure the SAI clock Divider coming from PLLI2S.
- Note
- This function must be called before enabling the PLLI2S.
- Parameters
-
<strong>PLLI2SDivQ</strong> specifies the PLLI2S division factor for SAI1 clock . This parameter must be a number between 1 and 32. SAI1 clock frequency = f(PLLI2SQ) / PLLI2SDivQ
Definition at line 2697 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLLSAI_CLEAR_IT
| #define __HAL_RCC_PLLSAI_CLEAR_IT | ( | ) | (RCC->CIR |= (RCC_CIR_PLLSAIRDYF)) |
Clear the PLLSAI RDY interrupt pending bits.
Definition at line 2796 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLLSAI_CONFIG
| #define __HAL_RCC_PLLSAI_CONFIG | ( | __PLLSAIN__, | |
| __PLLSAIP__, | |||
| __PLLSAIQ__, | |||
| __PLLSAIR__ | |||
| ) |
Value:
(RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\
((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\
((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\
((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))
Macro to configure the PLLSAI clock multiplication and division factors.
- Note
- This function must be used only when the PLLSAI is disabled.
- PLLSAI clock source is common with the main PLL (configured in RCC_PLLConfig function )
- Parameters
-
<strong>PLLSAIN</strong> specifies the multiplication factor for PLLSAI VCO output clock. This parameter must be a number between Min_Data = 50 and Max_Data = 432.
- Note
- You have to set the PLLSAIN parameter correctly to ensure that the VCO output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
- Parameters
-
<strong>PLLSAIP</strong> specifies the division factor for USB, RNG, SDMMC clocks This parameter can be a value of RCC PLLSAIP Clock Divider. <strong>PLLSAIQ</strong> specifies the division factor for SAI clock This parameter must be a number between Min_Data = 2 and Max_Data = 15. <strong>PLLSAIR</strong> specifies the division factor for LTDC clock This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Definition at line 2661 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLLSAI_DISABLE
| #define __HAL_RCC_PLLSAI_DISABLE | ( | ) | (RCC->CR &= ~(RCC_CR_PLLSAION)) |
Definition at line 2605 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLLSAI_DISABLE_IT
| #define __HAL_RCC_PLLSAI_DISABLE_IT | ( | ) | (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE)) |
Disable PLLSAI_RDY interrupt.
Definition at line 2792 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLLSAI_ENABLE
| #define __HAL_RCC_PLLSAI_ENABLE | ( | ) | (RCC->CR |= (RCC_CR_PLLSAION)) |
Macros to Enable or Disable the PLLISAI.
- Note
- The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
Definition at line 2604 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLLSAI_ENABLE_IT
| #define __HAL_RCC_PLLSAI_ENABLE_IT | ( | ) | (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE)) |
Enable PLLSAI_RDY interrupt.
Definition at line 2788 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLLSAI_GET_FLAG
| #define __HAL_RCC_PLLSAI_GET_FLAG | ( | ) | ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY)) |
Check PLLSAI RDY flag is set or not.
- Return values
-
The new state (TRUE or FALSE).
Definition at line 2806 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLLSAI_GET_IT
| #define __HAL_RCC_PLLSAI_GET_IT | ( | ) | ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE)) |
Check the PLLSAI RDY interrupt has occurred or not.
- Return values
-
The new state (TRUE or FALSE).
Definition at line 2801 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG
| #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG | ( | __PLLSAIDivQ__ | ) | (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8)) |
Macro to configure the SAI clock Divider coming from PLLSAI.
- Note
- This function must be called before enabling the PLLSAI.
- Parameters
-
<strong>PLLSAIDivQ</strong> specifies the PLLSAI division factor for SAI1 clock . This parameter must be a number between Min_Data = 1 and Max_Data = 32. SAI1 clock frequency = f(PLLSAIQ) / PLLSAIDivQ
Definition at line 2705 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_RNG_CONFIG [1/2]
| #define __HAL_RCC_RNG_CONFIG | ( | __RNGCLKSource__ | ) | MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__)) |
macro to configure the RNG clock (RNGCLK).
- Parameters
-
<strong>RNGCLKSource</strong> specifies the RNG clock source. This parameter can be one of the following values: - RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
- RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
- RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
- RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock
Definition at line 3552 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_RNG_CONFIG [2/2]
| #define __HAL_RCC_RNG_CONFIG | ( | __RNGCLKSource__ | ) | MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__)) |
macro to configure the RNG clock (RNGCLK).
- Parameters
-
<strong>RNGCLKSource</strong> specifies the RNG clock source. This parameter can be one of the following values: - RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
- RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
- RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
- RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock
Definition at line 3556 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SAI1_CONFIG [1/3]
| #define __HAL_RCC_SAI1_CONFIG | ( | __RCC_SAI1CLKSource__ | ) | MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__)) |
Macro to Configure the SAI1 clock source.
- Parameters
-
<strong>RCC_SAI1CLKSource</strong> defines the SAI1 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values: - RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
- RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2
- RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3
- RCC_SAI1CLKSOURCE_OSC: SAI1 clock = OSC
- RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock
- Return values
-
None
Definition at line 2020 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SAI1_CONFIG [2/3]
| #define __HAL_RCC_SAI1_CONFIG | ( | __RCC_SAI1CLKSource__ | ) | MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__)) |
Macro to Configure the SAI1 clock source.
- Parameters
-
<strong>RCC_SAI1CLKSource</strong> defines the SAI1 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values: - RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
- RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2
- RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3
- RCC_SAI1CLKSOURCE_OSC: SAI1 clock = OSC
- RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock
- Return values
-
None
Definition at line 2020 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SAI1_CONFIG [3/3]
| #define __HAL_RCC_SAI1_CONFIG | ( | __SOURCE__ | ) | MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__)) |
Macro to configure SAI1 clock source selection.
- Note
- This function must be called before enabling PLLSAI, PLLI2S and the SAI clock.
- Parameters
-
<strong>SOURCE</strong> specifies the SAI1 clock source. This parameter can be one of the following values: - RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
- RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
- RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
- RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI1 clock.
- Note
- The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
Definition at line 2735 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SAI2_CONFIG
| #define __HAL_RCC_SAI2_CONFIG | ( | __SOURCE__ | ) | MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__)) |
Macro to configure SAI2 clock source selection.
- Note
- This function must be called before enabling PLLSAI, PLLI2S and the SAI clock.
- Parameters
-
<strong>SOURCE</strong> specifies the SAI2 clock source. This parameter can be one of the following values: - RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
- RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
- RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin used as SAI2 clock.
- RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
- Note
- The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
Definition at line 2767 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SDMMC1_CONFIG
| #define __HAL_RCC_SDMMC1_CONFIG | ( | __SDMMC1_CLKSOURCE__ | ) | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)) |
Macro to configure the SDMMC1 clock (SDMMC1CLK).
- Parameters
-
<strong>SDMMC1_CLKSOURCE</strong> specifies the SDMMC1 clock source. This parameter can be one of the following values: - RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock
- RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock
Definition at line 3121 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SDMMC_CONFIG [1/2]
| #define __HAL_RCC_SDMMC_CONFIG | ( | __SDMMCCLKSource__ | ) | MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__)) |
Macro to configure the SDMMC clock.
- Parameters
-
<strong>SDMMCCLKSource</strong> specifies clock source for SDMMC This parameter can be one of the following values: - RCC_SDMMCCLKSOURCE_PLL: PLLQ selected as SDMMC clock
- RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock
Definition at line 3527 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SDMMC_CONFIG [2/2]
| #define __HAL_RCC_SDMMC_CONFIG | ( | __SDMMCCLKSource__ | ) | MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__)) |
Macro to configure the SDMMC clock.
- Parameters
-
<strong>SDMMCCLKSource</strong> specifies clock source for SDMMC This parameter can be one of the following values: - RCC_SDMMCCLKSOURCE_PLL: PLLQ selected as SDMMC clock
- RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock
Definition at line 3531 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SPDIFRX_CONFIG [1/2]
| #define __HAL_RCC_SPDIFRX_CONFIG | ( | __RCC_SPDIFCLKSource__ | ) | MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__)) |
Macro to Configure the SPDIFRX clock source.
- Parameters
-
<strong>RCC_SPDIFCLKSource</strong> defines the SPDIFRX clock source. This clock is derived from system PLL, PLL2, PLL3, or internal OSC clock This parameter can be one of the following values: - RCC_SPDIFRXCLKSOURCE_PLL: SPDIFRX clock = PLL
- RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2
- RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3
- RCC_SPDIFRXCLKSOURCE_HSI: SPDIFRX clock = HSI
- Return values
-
None
Definition at line 2053 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SPDIFRX_CONFIG [2/2]
| #define __HAL_RCC_SPDIFRX_CONFIG | ( | __RCC_SPDIFCLKSource__ | ) | MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__)) |
Macro to Configure the SPDIFRX clock source.
- Parameters
-
<strong>RCC_SPDIFCLKSource</strong> defines the SPDIFRX clock source. This clock is derived from system PLL, PLL2, PLL3, or internal OSC clock This parameter can be one of the following values: - RCC_SPDIFRXCLKSOURCE_PLL: SPDIFRX clock = PLL
- RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2
- RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3
- RCC_SPDIFRXCLKSOURCE_HSI: SPDIFRX clock = HSI
- Return values
-
None
Definition at line 2053 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SPI123_CONFIG [1/2]
| #define __HAL_RCC_SPI123_CONFIG | ( | __RCC_SPI123CLKSource__ | ) | MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__)) |
Macro to Configure the SPI1/2/3 clock source.
- Parameters
-
<strong>RCC_SPI123CLKSource</strong> defines the SPI1/2/3 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values: - RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
- RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
- RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
- RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP
- RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock
- Return values
-
None
Definition at line 3297 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SPI123_CONFIG [2/2]
| #define __HAL_RCC_SPI123_CONFIG | ( | __RCC_SPI123CLKSource__ | ) | MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__)) |
Macro to Configure the SPI1/2/3 clock source.
- Parameters
-
<strong>RCC_SPI123CLKSource</strong> defines the SPI1/2/3 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values: - RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
- RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
- RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
- RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP
- RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock
- Return values
-
None
Definition at line 3301 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SPI1_CONFIG [1/2]
| #define __HAL_RCC_SPI1_CONFIG __HAL_RCC_SPI123_CONFIG |
Macro to Configure the SPI1 clock source.
- Parameters
-
<strong>RCC_SPI1CLKSource</strong> defines the SPI1 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values: - RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
- RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2
- RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3
- RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP
- RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock
- Return values
-
None
Definition at line 3327 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SPI1_CONFIG [2/2]
| #define __HAL_RCC_SPI1_CONFIG __HAL_RCC_SPI123_CONFIG |
Macro to Configure the SPI1 clock source.
- Parameters
-
<strong>RCC_SPI1CLKSource</strong> defines the SPI1 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values: - RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
- RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2
- RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3
- RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP
- RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock
- Return values
-
None
Definition at line 3331 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SPI2_CONFIG [1/2]
| #define __HAL_RCC_SPI2_CONFIG __HAL_RCC_SPI123_CONFIG |
Macro to Configure the SPI2 clock source.
- Parameters
-
<strong>RCC_SPI2CLKSource</strong> defines the SPI2 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values: - RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
- RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2
- RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3
- RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP
- RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock
- Return values
-
None
Definition at line 3351 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SPI2_CONFIG [2/2]
| #define __HAL_RCC_SPI2_CONFIG __HAL_RCC_SPI123_CONFIG |
Macro to Configure the SPI2 clock source.
- Parameters
-
<strong>RCC_SPI2CLKSource</strong> defines the SPI2 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values: - RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
- RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2
- RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3
- RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP
- RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock
- Return values
-
None
Definition at line 3355 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SPI3_CONFIG [1/2]
| #define __HAL_RCC_SPI3_CONFIG __HAL_RCC_SPI123_CONFIG |
Macro to Configure the SPI3 clock source.
- Parameters
-
<strong>RCC_SPI3CLKSource</strong> defines the SPI3 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values: - RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
- RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2
- RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3
- RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP
- RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock
- Return values
-
None
Definition at line 3375 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SPI3_CONFIG [2/2]
| #define __HAL_RCC_SPI3_CONFIG __HAL_RCC_SPI123_CONFIG |
Macro to Configure the SPI3 clock source.
- Parameters
-
<strong>RCC_SPI3CLKSource</strong> defines the SPI3 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values: - RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
- RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2
- RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3
- RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP
- RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock
- Return values
-
None
Definition at line 3379 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SPI45_CONFIG [1/2]
| #define __HAL_RCC_SPI45_CONFIG | ( | __RCC_SPI45CLKSource__ | ) | MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__)) |
Macro to Configure the SPI4/5 clock source.
- Parameters
-
<strong>RCC_SPI45CLKSource</strong> defines the SPI4/5 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values: - RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
- RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2
- RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3
- RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI
- RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI
- RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE
- Return values
-
None
Definition at line 3404 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SPI45_CONFIG [2/2]
| #define __HAL_RCC_SPI45_CONFIG | ( | __RCC_SPI45CLKSource__ | ) | MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__)) |
Macro to Configure the SPI4/5 clock source.
- Parameters
-
<strong>RCC_SPI45CLKSource</strong> defines the SPI4/5 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values: - RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
- RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2
- RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3
- RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI
- RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI
- RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE
- Return values
-
None
Definition at line 3408 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SPI4_CONFIG [1/2]
| #define __HAL_RCC_SPI4_CONFIG __HAL_RCC_SPI45_CONFIG |
Macro to Configure the SPI4 clock source.
- Parameters
-
<strong>RCC_SPI4CLKSource</strong> defines the SPI4 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values: - RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
- RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2
- RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3
- RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI
- RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI
- RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE
- Return values
-
None
Definition at line 3436 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SPI4_CONFIG [2/2]
| #define __HAL_RCC_SPI4_CONFIG __HAL_RCC_SPI45_CONFIG |
Macro to Configure the SPI4 clock source.
- Parameters
-
<strong>RCC_SPI4CLKSource</strong> defines the SPI4 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values: - RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
- RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2
- RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3
- RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI
- RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI
- RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE
- Return values
-
None
Definition at line 3440 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SPI5_CONFIG [1/2]
| #define __HAL_RCC_SPI5_CONFIG __HAL_RCC_SPI45_CONFIG |
Macro to Configure the SPI5 clock source.
- Parameters
-
<strong>RCC_SPI5CLKSource</strong> defines the SPI5 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values: - RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
- RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2
- RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3
- RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI
- RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI
- RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE
- Return values
-
None
Definition at line 3462 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SPI5_CONFIG [2/2]
| #define __HAL_RCC_SPI5_CONFIG __HAL_RCC_SPI45_CONFIG |
Macro to Configure the SPI5 clock source.
- Parameters
-
<strong>RCC_SPI5CLKSource</strong> defines the SPI5 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values: - RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
- RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2
- RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3
- RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI
- RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI
- RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE
- Return values
-
None
Definition at line 3466 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SPI6_CONFIG [1/2]
| #define __HAL_RCC_SPI6_CONFIG | ( | __RCC_SPI6CLKSource__ | ) | MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__)) |
Macro to Configure the SPI6 clock source.
- Parameters
-
<strong>RCC_SPI6CLKSource</strong> defines the SPI6 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values: - RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
- RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2
- RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3
- RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI
- RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI
- RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE
- RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN (*)
- Return values
-
None (*) : Available on stm32h7a3xx and stm32h7b3xx family lines.
Definition at line 3497 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SPI6_CONFIG [2/2]
| #define __HAL_RCC_SPI6_CONFIG | ( | __RCC_SPI6CLKSource__ | ) | MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__)) |
Macro to Configure the SPI6 clock source.
- Parameters
-
<strong>RCC_SPI6CLKSource</strong> defines the SPI6 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values: - RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
- RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2
- RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3
- RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI
- RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI
- RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE
- RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN (*)
- Return values
-
None (*) : Available on stm32h7a3xx and stm32h7b3xx family lines.
Definition at line 3501 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SWPMI1_CONFIG [1/2]
| #define __HAL_RCC_SWPMI1_CONFIG | ( | __SWPMI1CLKSource__ | ) | MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__)) |
Macro to configure the SWPMI1 clock.
- Parameters
-
<strong>SWPMI1CLKSource</strong> specifies the SWPMI1 clock source. This parameter can be one of the following values: - RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock
- RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
Definition at line 3138 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_SWPMI1_CONFIG [2/2]
| #define __HAL_RCC_SWPMI1_CONFIG | ( | __SWPMI1CLKSource__ | ) | MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__)) |
Macro to configure the SWPMI1 clock.
- Parameters
-
<strong>SWPMI1CLKSource</strong> specifies the SWPMI1 clock source. This parameter can be one of the following values: - RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock
- RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
Definition at line 3142 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_TIMCLKPRESCALER [1/3]
| #define __HAL_RCC_TIMCLKPRESCALER | ( | __PRESC__ | ) |
Value:
Macro to configure the Timers clocks prescalers.
- Parameters
-
<strong>PRESC</strong> specifies the Timers clocks prescalers selection This parameter can be one of the following values: - RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1 or 2, else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to division by 4 or more.
- RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding to division by 8 or more.
Definition at line 2597 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_TIMCLKPRESCALER [2/3]
| #define __HAL_RCC_TIMCLKPRESCALER | ( | __PRESC__ | ) |
Value:
Macro to configure the Timers clocks prescalers.
- Parameters
-
<strong>PRESC</strong> specifies the Timers clocks prescalers selection This parameter can be one of the following values: - RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2, else it is equal to 2 x Frcc_pclkx_d2 (default after reset)
- RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4, else it is equal to 4 x Frcc_pclkx_d2
Definition at line 3597 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_TIMCLKPRESCALER [3/3]
| #define __HAL_RCC_TIMCLKPRESCALER | ( | __PRESC__ | ) |
Value:
Macro to configure the Timers clocks prescalers.
- Parameters
-
<strong>PRESC</strong> specifies the Timers clocks prescalers selection This parameter can be one of the following values: - RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2, else it is equal to 2 x Frcc_pclkx_d2 (default after reset)
- RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4, else it is equal to 4 x Frcc_pclkx_d2
Definition at line 3601 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_UART4_CONFIG [1/3]
| #define __HAL_RCC_UART4_CONFIG | ( | __UART4_CLKSOURCE__ | ) | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) |
Macro to configure the UART4 clock (UART4CLK).
- Parameters
-
<strong>UART4_CLKSOURCE</strong> specifies the UART4 clock source. This parameter can be one of the following values: - RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
- RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
- RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
- RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
Definition at line 2963 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_UART4_CONFIG [2/3]
| #define __HAL_RCC_UART4_CONFIG __HAL_RCC_USART234578_CONFIG |
macro to configure the UART4 clock (UART4CLK).
- Parameters
-
<strong>UART4CLKSource</strong> specifies the UART4 clock source. This parameter can be one of the following values: - RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
- RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
- RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
- RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
- RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
- RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
Definition at line 2600 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_UART4_CONFIG [3/3]
| #define __HAL_RCC_UART4_CONFIG __HAL_RCC_USART234578_CONFIG |
macro to configure the UART4 clock (UART4CLK).
- Parameters
-
<strong>UART4CLKSource</strong> specifies the UART4 clock source. This parameter can be one of the following values: - RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
- RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
- RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
- RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
- RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
- RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
Definition at line 2604 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_UART5_CONFIG [1/3]
| #define __HAL_RCC_UART5_CONFIG | ( | __UART5_CLKSOURCE__ | ) | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) |
Macro to configure the UART5 clock (UART5CLK).
- Parameters
-
<strong>UART5_CLKSOURCE</strong> specifies the UART5 clock source. This parameter can be one of the following values: - RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
- RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
- RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
- RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
Definition at line 2984 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_UART5_CONFIG [2/3]
| #define __HAL_RCC_UART5_CONFIG __HAL_RCC_USART234578_CONFIG |
macro to configure the UART5 clock (UART5CLK).
- Parameters
-
<strong>UART5CLKSource</strong> specifies the UART5 clock source. This parameter can be one of the following values: - RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
- RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
- RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
- RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
- RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
- RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
Definition at line 2624 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_UART5_CONFIG [3/3]
| #define __HAL_RCC_UART5_CONFIG __HAL_RCC_USART234578_CONFIG |
macro to configure the UART5 clock (UART5CLK).
- Parameters
-
<strong>UART5CLKSource</strong> specifies the UART5 clock source. This parameter can be one of the following values: - RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
- RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
- RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
- RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
- RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
- RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
Definition at line 2628 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_UART7_CONFIG [1/3]
| #define __HAL_RCC_UART7_CONFIG | ( | __UART7_CLKSOURCE__ | ) | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__)) |
Macro to configure the UART7 clock (UART7CLK).
- Parameters
-
<strong>UART7_CLKSOURCE</strong> specifies the UART7 clock source. This parameter can be one of the following values: - RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
- RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
- RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
- RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
Definition at line 3026 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_UART7_CONFIG [2/3]
| #define __HAL_RCC_UART7_CONFIG __HAL_RCC_USART234578_CONFIG |
macro to configure the UART5 clock (UART7CLK).
- Parameters
-
<strong>UART7CLKSource</strong> specifies the UART7 clock source. This parameter can be one of the following values: - RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
- RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
- RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
- RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
- RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
- RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
Definition at line 2672 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_UART7_CONFIG [3/3]
| #define __HAL_RCC_UART7_CONFIG __HAL_RCC_USART234578_CONFIG |
macro to configure the UART5 clock (UART7CLK).
- Parameters
-
<strong>UART7CLKSource</strong> specifies the UART7 clock source. This parameter can be one of the following values: - RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
- RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
- RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
- RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
- RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
- RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
Definition at line 2676 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_UART8_CONFIG [1/3]
| #define __HAL_RCC_UART8_CONFIG | ( | __UART8_CLKSOURCE__ | ) | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__)) |
Macro to configure the UART8 clock (UART8CLK).
- Parameters
-
<strong>UART8_CLKSOURCE</strong> specifies the UART8 clock source. This parameter can be one of the following values: - RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
- RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
- RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
- RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
Definition at line 3047 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_UART8_CONFIG [2/3]
| #define __HAL_RCC_UART8_CONFIG __HAL_RCC_USART234578_CONFIG |
macro to configure the UART8 clock (UART8CLK).
- Parameters
-
<strong>UART8CLKSource</strong> specifies the UART8 clock source. This parameter can be one of the following values: - RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
- RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
- RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
- RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
- RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
- RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
Definition at line 2696 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_UART8_CONFIG [3/3]
| #define __HAL_RCC_UART8_CONFIG __HAL_RCC_USART234578_CONFIG |
macro to configure the UART8 clock (UART8CLK).
- Parameters
-
<strong>UART8CLKSource</strong> specifies the UART8 clock source. This parameter can be one of the following values: - RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
- RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
- RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
- RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
- RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
- RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
Definition at line 2700 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_USART16910_CONFIG [1/2]
| #define __HAL_RCC_USART16910_CONFIG | ( | __USART16910CLKSource__ | ) | MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__)) |
macro to configure the USART1/6/9* /10* clock (USART16CLK).
- Parameters
-
<strong>USART16910CLKSource</strong> specifies the USART1/6/9* /10* clock source. This parameter can be one of the following values: - RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock
- RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock
- RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock
- RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock
- RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock
- RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock
Definition at line 2454 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_USART16910_CONFIG [2/2]
| #define __HAL_RCC_USART16910_CONFIG | ( | __USART16910CLKSource__ | ) | MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__)) |
macro to configure the USART1/6/9* /10* clock (USART16CLK).
- Parameters
-
<strong>USART16910CLKSource</strong> specifies the USART1/6/9* /10* clock source. This parameter can be one of the following values: - RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock
- RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock
- RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock
- RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock
- RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock
- RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock
Definition at line 2458 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_USART16_CONFIG [1/2]
| #define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG |
Definition at line 2457 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_USART16_CONFIG [2/2]
| #define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG |
Definition at line 2461 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_USART1_CONFIG [1/3]
| #define __HAL_RCC_USART1_CONFIG | ( | __USART1_CLKSOURCE__ | ) | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) |
Macro to configure the USART1 clock (USART1CLK).
- Parameters
-
<strong>USART1_CLKSOURCE</strong> specifies the USART1 clock source. This parameter can be one of the following values: - RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
- RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
- RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
- RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Definition at line 2900 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_USART1_CONFIG [2/3]
| #define __HAL_RCC_USART1_CONFIG __HAL_RCC_USART16_CONFIG |
macro to configure the USART1 clock (USART1CLK).
- Parameters
-
<strong>USART1CLKSource</strong> specifies the USART1 clock source. This parameter can be one of the following values: - RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
- RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
- RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
- RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
- RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
- RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Definition at line 2528 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_USART1_CONFIG [3/3]
| #define __HAL_RCC_USART1_CONFIG __HAL_RCC_USART16_CONFIG |
macro to configure the USART1 clock (USART1CLK).
- Parameters
-
<strong>USART1CLKSource</strong> specifies the USART1 clock source. This parameter can be one of the following values: - RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
- RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
- RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
- RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
- RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
- RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Definition at line 2532 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_USART234578_CONFIG [1/2]
| #define __HAL_RCC_USART234578_CONFIG | ( | __USART234578CLKSource__ | ) | MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__)) |
macro to configure the USART234578 clock (USART234578CLK).
- Parameters
-
<strong>USART234578CLKSource</strong> specifies the USART2/3/4/5/7/8 clock source. This parameter can be one of the following values: - RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
- RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
- RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock
- RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock
- RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock
- RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock
Definition at line 2498 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_USART234578_CONFIG [2/2]
| #define __HAL_RCC_USART234578_CONFIG | ( | __USART234578CLKSource__ | ) | MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__)) |
macro to configure the USART234578 clock (USART234578CLK).
- Parameters
-
<strong>USART234578CLKSource</strong> specifies the USART2/3/4/5/7/8 clock source. This parameter can be one of the following values: - RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
- RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
- RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock
- RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock
- RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock
- RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock
Definition at line 2502 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_USART2_CONFIG [1/3]
| #define __HAL_RCC_USART2_CONFIG | ( | __USART2_CLKSOURCE__ | ) | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) |
Macro to configure the USART2 clock (USART2CLK).
- Parameters
-
<strong>USART2_CLKSOURCE</strong> specifies the USART2 clock source. This parameter can be one of the following values: - RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
- RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
- RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
- RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Definition at line 2921 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_USART2_CONFIG [2/3]
| #define __HAL_RCC_USART2_CONFIG __HAL_RCC_USART234578_CONFIG |
macro to configure the USART2 clock (USART2CLK).
- Parameters
-
<strong>USART2CLKSource</strong> specifies the USART2 clock source. This parameter can be one of the following values: - RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
- RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
- RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
- RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
- RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
- RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Definition at line 2552 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_USART2_CONFIG [3/3]
| #define __HAL_RCC_USART2_CONFIG __HAL_RCC_USART234578_CONFIG |
macro to configure the USART2 clock (USART2CLK).
- Parameters
-
<strong>USART2CLKSource</strong> specifies the USART2 clock source. This parameter can be one of the following values: - RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
- RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
- RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
- RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
- RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
- RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Definition at line 2556 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_USART3_CONFIG [1/3]
| #define __HAL_RCC_USART3_CONFIG | ( | __USART3_CLKSOURCE__ | ) | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) |
Macro to configure the USART3 clock (USART3CLK).
- Parameters
-
<strong>USART3_CLKSOURCE</strong> specifies the USART3 clock source. This parameter can be one of the following values: - RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
- RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
- RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
- RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Definition at line 2942 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_USART3_CONFIG [2/3]
| #define __HAL_RCC_USART3_CONFIG __HAL_RCC_USART234578_CONFIG |
macro to configure the USART3 clock (USART3CLK).
- Parameters
-
<strong>USART3CLKSource</strong> specifies the USART3 clock source. This parameter can be one of the following values: - RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
- RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
- RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
- RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
- RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
- RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Definition at line 2576 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_USART3_CONFIG [3/3]
| #define __HAL_RCC_USART3_CONFIG __HAL_RCC_USART234578_CONFIG |
macro to configure the USART3 clock (USART3CLK).
- Parameters
-
<strong>USART3CLKSource</strong> specifies the USART3 clock source. This parameter can be one of the following values: - RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
- RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
- RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
- RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
- RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
- RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Definition at line 2580 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_USART6_CONFIG [1/3]
| #define __HAL_RCC_USART6_CONFIG | ( | __USART6_CLKSOURCE__ | ) | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__)) |
Macro to configure the USART6 clock (USART6CLK).
- Parameters
-
<strong>USART6_CLKSOURCE</strong> specifies the USART6 clock source. This parameter can be one of the following values: - RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
- RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
- RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
- RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
Definition at line 3005 of file stm32f7xx_hal_rcc_ex.h.
◆ __HAL_RCC_USART6_CONFIG [2/3]
| #define __HAL_RCC_USART6_CONFIG __HAL_RCC_USART16_CONFIG |
macro to configure the USART6 clock (USART6CLK).
- Parameters
-
<strong>USART6CLKSource</strong> specifies the USART6 clock source. This parameter can be one of the following values: - RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
- RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
- RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
- RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
- RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
- RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
Definition at line 2648 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_USART6_CONFIG [3/3]
| #define __HAL_RCC_USART6_CONFIG __HAL_RCC_USART16_CONFIG |
macro to configure the USART6 clock (USART6CLK).
- Parameters
-
<strong>USART6CLKSource</strong> specifies the USART6 clock source. This parameter can be one of the following values: - RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
- RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
- RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
- RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
- RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
- RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
Definition at line 2652 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_USB_CONFIG [1/2]
| #define __HAL_RCC_USB_CONFIG | ( | __USBCLKSource__ | ) | MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__)) |
Macro to configure the USB clock (USBCLK).
- Parameters
-
<strong>USBCLKSource</strong> specifies the USB clock source. This parameter can be one of the following values: - RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock
- RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock
- RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock
Definition at line 3085 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ __HAL_RCC_USB_CONFIG [2/2]
| #define __HAL_RCC_USB_CONFIG | ( | __USBCLKSource__ | ) | MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__)) |
Macro to configure the USB clock (USBCLK).
- Parameters
-
<strong>USBCLKSource</strong> specifies the USB clock source. This parameter can be one of the following values: - RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock
- RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock
- RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock
Definition at line 3089 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ RCC_CRS_FLAG_ERROR_MASK [1/2]
| #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) |
Clear the CRS specified FLAG.
- Parameters
-
<strong>FLAG</strong> specifies the flag to clear. This parameter can be one of the following values: - RCC_CRS_FLAG_SYNCOK SYNC event OK
- RCC_CRS_FLAG_SYNCWARN SYNC warning
- RCC_CRS_FLAG_ERR Error
- RCC_CRS_FLAG_ESYNC Expected SYNC
- RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
- RCC_CRS_FLAG_SYNCERR SYNC error
- RCC_CRS_FLAG_SYNCMISS SYNC missed
- Note
- RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
- Return values
-
None
Definition at line 3819 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ RCC_CRS_FLAG_ERROR_MASK [2/2]
| #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) |
Clear the CRS specified FLAG.
- Parameters
-
<strong>FLAG</strong> specifies the flag to clear. This parameter can be one of the following values: - RCC_CRS_FLAG_SYNCOK SYNC event OK
- RCC_CRS_FLAG_SYNCWARN SYNC warning
- RCC_CRS_FLAG_ERR Error
- RCC_CRS_FLAG_ESYNC Expected SYNC
- RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
- RCC_CRS_FLAG_SYNCERR SYNC error
- RCC_CRS_FLAG_SYNCMISS SYNC missed
- Note
- RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
- Return values
-
None
Definition at line 3823 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ RCC_CRS_IT_ERROR_MASK [1/2]
| #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) |
Clear the CRS interrupt pending bits.
- Parameters
-
<strong>INTERRUPT</strong> specifies the interrupt pending bit to clear. This parameter can be any combination of the following values: - RCC_CRS_IT_SYNCOK SYNC event OK interrupt
- RCC_CRS_IT_SYNCWARN SYNC warning interrupt
- RCC_CRS_IT_ERR Synchronization or trimming error interrupt
- RCC_CRS_IT_ESYNC Expected SYNC interrupt
- RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
- RCC_CRS_IT_SYNCERR SYNC error interrupt
- RCC_CRS_IT_SYNCMISS SYNC missed interrupt
Definition at line 3775 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.
◆ RCC_CRS_IT_ERROR_MASK [2/2]
| #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) |
Clear the CRS interrupt pending bits.
- Parameters
-
<strong>INTERRUPT</strong> specifies the interrupt pending bit to clear. This parameter can be any combination of the following values: - RCC_CRS_IT_SYNCOK SYNC event OK interrupt
- RCC_CRS_IT_SYNCWARN SYNC warning interrupt
- RCC_CRS_IT_ERR Synchronization or trimming error interrupt
- RCC_CRS_IT_ESYNC Expected SYNC interrupt
- RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
- RCC_CRS_IT_SYNCERR SYNC error interrupt
- RCC_CRS_IT_SYNCMISS SYNC missed interrupt
Definition at line 3779 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h.