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Defines | |
#define | _ATH5K_RESET |
Functions | |
static void | ath5k_hw_commit_eeprom_settings (struct ath5k_hw *ah, struct ieee80211_channel *channel, u8 *ant, u8 ee_mode) |
static int | ath5k_hw_nic_reset (struct ath5k_hw *ah, u32 val) |
int | ath5k_hw_nic_wakeup (struct ath5k_hw *ah, int flags, bool initial) |
int | ath5k_hw_on_hold (struct ath5k_hw *ah) |
int | ath5k_hw_reset (struct ath5k_hw *ah, struct ieee80211_channel *channel, bool change_channel) |
int | ath5k_hw_set_power (struct ath5k_hw *ah, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration) |
static void | ath5k_hw_set_sleep_clock (struct ath5k_hw *ah, bool enable) |
static void | ath5k_hw_tweak_initval_settings (struct ath5k_hw *ah, struct ieee80211_channel *channel) |
static int | ath5k_hw_write_ofdm_timings (struct ath5k_hw *ah, struct ieee80211_channel *channel) |
static void | ath5k_hw_write_rate_duration (struct ath5k_hw *ah, unsigned int mode) |
Variables | |
static const unsigned int | control_rates [] |
#define _ATH5K_RESET |
Definition at line 53 of file ath5k_reset.c.
static void ath5k_hw_commit_eeprom_settings | ( | struct ath5k_hw * | ah, |
struct ieee80211_channel * | channel, | ||
u8 * | ant, | ||
u8 | ee_mode | ||
) | [static] |
Definition at line 744 of file ath5k_reset.c.
static int ath5k_hw_nic_reset | ( | struct ath5k_hw * | ah, |
u32 | val | ||
) | [static] |
Definition at line 208 of file ath5k_reset.c.
int ath5k_hw_nic_wakeup | ( | struct ath5k_hw * | ah, |
int | flags, | ||
bool | initial | ||
) |
Definition at line 394 of file ath5k_reset.c.
int ath5k_hw_on_hold | ( | struct ath5k_hw * | ah | ) |
Definition at line 343 of file ath5k_reset.c.
int ath5k_hw_reset | ( | struct ath5k_hw * | ah, |
struct ieee80211_channel * | channel, | ||
bool | change_channel | ||
) |
Definition at line 897 of file ath5k_reset.c.
int ath5k_hw_set_power | ( | struct ath5k_hw * | ah, |
enum ath5k_power_mode | mode, | ||
bool | set_chip, | ||
u16 | sleep_duration | ||
) |
Definition at line 252 of file ath5k_reset.c.
static void ath5k_hw_set_sleep_clock | ( | struct ath5k_hw * | ah, |
bool | enable | ||
) | [static] |
Definition at line 546 of file ath5k_reset.c.
static void ath5k_hw_tweak_initval_settings | ( | struct ath5k_hw * | ah, |
struct ieee80211_channel * | channel | ||
) | [static] |
Definition at line 641 of file ath5k_reset.c.
static int ath5k_hw_write_ofdm_timings | ( | struct ath5k_hw * | ah, |
struct ieee80211_channel * | channel | ||
) | [inline, static] |
ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
: the &struct ath5k_hw : the currently set channel upon reset
Write the delta slope coefficient (used on pilot tracking ?) for OFDM operation on the AR5212 upon reset. This is a helper for ath5k_hw_reset().
Since delta slope is floating point we split it on its exponent and mantissa and provide these values on hw.
For more infos i think this patent is related http://www.freepatentsonline.com/7184495.html
Definition at line 79 of file ath5k_reset.c.
static void ath5k_hw_write_rate_duration | ( | struct ath5k_hw * | ah, |
unsigned int | mode | ||
) | [inline, static] |
ath5k_hw_write_rate_duration - fill rate code to duration table
: the &struct ath5k_hw : one of enum ath5k_driver_mode
Write the rate code to duration table upon hw reset. This is a helper for ath5k_hw_reset(). It seems all this is doing is setting an ACK timeout on the hardware, based on current mode, for each rate. The rates which are capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have different rate code so we write their value twice (one for long preample and one for short).
Note: Band doesn't matter here, if we set the values for OFDM it works on both a and g modes. So all we have to do is set values for all g rates that include all OFDM and CCK rates. If we operate in turbo or xr/half/ quarter rate mode, we need to use another set of bitrates (that's why we need the mode parameter) but we don't handle these proprietary modes yet.
Definition at line 155 of file ath5k_reset.c.
const unsigned int control_rates[] [static] |
{ 0, 1, 1, 1, 4, 4, 6, 6, 8, 8, 8, 8 }
Definition at line 133 of file ath5k_reset.c.