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00053 #define _ATH5K_RESET
00054
00055
00056
00057
00058
00059 #include "ath5k.h"
00060 #include "reg.h"
00061 #include "base.h"
00062 #include "debug.h"
00063
00079 static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
00080 struct ieee80211_channel *channel)
00081 {
00082
00083 u32 coef_scaled, coef_exp, coef_man,
00084 ds_coef_exp, ds_coef_man, clock;
00085
00086 BUG_ON(!(ah->ah_version == AR5K_AR5212) ||
00087 !(channel->hw_value & CHANNEL_OFDM));
00088
00089
00090
00091
00092
00093
00094 clock = ath5k_hw_htoclock(1, channel->hw_value & CHANNEL_TURBO);
00095
00096 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq;
00097
00098
00099
00100 coef_exp = ilog2(coef_scaled);
00101
00102
00103 if (!coef_scaled || !coef_exp)
00104 return -EINVAL;
00105
00106
00107 coef_exp = 14 - (coef_exp - 24);
00108
00109
00110
00111
00112 coef_man = coef_scaled +
00113 (1 << (24 - coef_exp - 1));
00114
00115
00116
00117 ds_coef_man = coef_man >> (24 - coef_exp);
00118 ds_coef_exp = coef_exp - 16;
00119
00120 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
00121 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
00122 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
00123 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
00124
00125 return 0;
00126 }
00127
00128
00129
00130
00131
00132
00133 static const unsigned int control_rates[] =
00134 { 0, 1, 1, 1, 4, 4, 6, 6, 8, 8, 8, 8 };
00135
00155 static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah,
00156 unsigned int mode)
00157 {
00158 struct ath5k_softc *sc = ah->ah_sc;
00159 struct ieee80211_rate *rate;
00160 unsigned int i;
00161
00162
00163 for (i = 0; i < sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates; i++) {
00164 u32 reg;
00165 u16 tx_time;
00166
00167 rate = &sc->sbands[IEEE80211_BAND_2GHZ].bitrates[control_rates[i]];
00168
00169
00170 reg = AR5K_RATE_DUR(rate->hw_value);
00171
00172
00173
00174
00175
00176
00177
00178 tx_time = le16_to_cpu(ath5k_generic_frame_duration(mode,
00179 sc->tx_info.use_short_preamble, 10, rate->bitrate));
00180
00181 ath5k_hw_reg_write(ah, tx_time, reg);
00182
00183 if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE))
00184 continue;
00185
00186
00187
00188
00189
00190
00191
00192
00193
00194
00195
00196
00197
00198
00199
00200 ath5k_hw_reg_write(ah, tx_time,
00201 reg + (AR5K_SET_SHORT_PREAMBLE << 2));
00202 }
00203 }
00204
00205
00206
00207
00208 static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
00209 {
00210 int ret;
00211 u32 mask = val ? val : ~0U;
00212
00213 ATH5K_TRACE(ah->ah_sc);
00214
00215
00216 ath5k_hw_reg_read(ah, AR5K_RXDP);
00217
00218
00219
00220
00221 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
00222
00223
00224 udelay(15);
00225
00226 if (ah->ah_version == AR5K_AR5210) {
00227 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
00228 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
00229 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
00230 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
00231 } else {
00232 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
00233 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
00234 }
00235
00236 ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);
00237
00238
00239
00240
00241
00242
00243 if ((val & AR5K_RESET_CTL_PCU) == 0)
00244 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
00245
00246 return ret;
00247 }
00248
00249
00250
00251
00252 int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
00253 bool set_chip, u16 sleep_duration)
00254 {
00255 unsigned int i;
00256 u32 staid, data;
00257
00258 ATH5K_TRACE(ah->ah_sc);
00259 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
00260
00261 switch (mode) {
00262 case AR5K_PM_AUTO:
00263 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
00264
00265 case AR5K_PM_NETWORK_SLEEP:
00266 if (set_chip)
00267 ath5k_hw_reg_write(ah,
00268 AR5K_SLEEP_CTL_SLE_ALLOW |
00269 sleep_duration,
00270 AR5K_SLEEP_CTL);
00271
00272 staid |= AR5K_STA_ID1_PWR_SV;
00273 break;
00274
00275 case AR5K_PM_FULL_SLEEP:
00276 if (set_chip)
00277 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
00278 AR5K_SLEEP_CTL);
00279
00280 staid |= AR5K_STA_ID1_PWR_SV;
00281 break;
00282
00283 case AR5K_PM_AWAKE:
00284
00285 staid &= ~AR5K_STA_ID1_PWR_SV;
00286
00287 if (!set_chip)
00288 goto commit;
00289
00290 data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);
00291
00292
00293
00294
00295 if (data & 0xffc00000)
00296 data = 0;
00297 else
00298
00299 data = data & ~AR5K_SLEEP_CTL_SLE;
00300
00301 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
00302 AR5K_SLEEP_CTL);
00303 udelay(15);
00304
00305 for (i = 200; i > 0; i--) {
00306
00307 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
00308 AR5K_PCICFG_SPWR_DN) == 0)
00309 break;
00310
00311
00312 udelay(50);
00313 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
00314 AR5K_SLEEP_CTL);
00315 }
00316
00317
00318 if (i == 0)
00319 return -EIO;
00320
00321 break;
00322
00323 default:
00324 return -EINVAL;
00325 }
00326
00327 commit:
00328 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
00329
00330 return 0;
00331 }
00332
00333
00334
00335
00336
00337
00338
00339
00340
00341
00342
00343 int ath5k_hw_on_hold(struct ath5k_hw *ah)
00344 {
00345 u32 bus_flags;
00346 int ret;
00347
00348
00349 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
00350 if (ret) {
00351 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
00352 return ret;
00353 }
00354
00355
00356
00357
00358
00359
00360
00361
00362
00363 bus_flags = AR5K_RESET_CTL_PCI;
00364
00365 if (ah->ah_version == AR5K_AR5210) {
00366 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
00367 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
00368 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
00369 mdelay(2);
00370 } else {
00371 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
00372 AR5K_RESET_CTL_BASEBAND | bus_flags);
00373 }
00374
00375 if (ret) {
00376 ATH5K_ERR(ah->ah_sc, "failed to put device on warm reset\n");
00377 return -EIO;
00378 }
00379
00380
00381 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
00382 if (ret) {
00383 ATH5K_ERR(ah->ah_sc, "failed to put device on hold\n");
00384 return ret;
00385 }
00386
00387 return ret;
00388 }
00389
00390
00391
00392
00393
00394 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
00395 {
00396 u32 turbo, mode, clock, bus_flags;
00397 int ret;
00398
00399 turbo = 0;
00400 mode = 0;
00401 clock = 0;
00402
00403 ATH5K_TRACE(ah->ah_sc);
00404
00405
00406 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
00407 if (ret) {
00408 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
00409 return ret;
00410 }
00411
00412
00413
00414
00415
00416
00417
00418
00419
00420 bus_flags = AR5K_RESET_CTL_PCI;
00421
00422 if (ah->ah_version == AR5K_AR5210) {
00423 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
00424 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
00425 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
00426 mdelay(2);
00427 } else {
00428 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
00429 AR5K_RESET_CTL_BASEBAND | bus_flags);
00430 }
00431
00432 if (ret) {
00433 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n");
00434 return -EIO;
00435 }
00436
00437
00438 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
00439 if (ret) {
00440 ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n");
00441 return ret;
00442 }
00443
00444
00445
00446 if (ath5k_hw_nic_reset(ah, 0)) {
00447 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
00448 return -EIO;
00449 }
00450
00451
00452
00453 if (initial)
00454 return 0;
00455
00456 if (ah->ah_version != AR5K_AR5210) {
00457
00458
00459
00460
00461 if (ah->ah_radio >= AR5K_RF5112) {
00462 mode = AR5K_PHY_MODE_RAD_RF5112;
00463 clock = AR5K_PHY_PLL_RF5112;
00464 } else {
00465 mode = AR5K_PHY_MODE_RAD_RF5111;
00466 clock = AR5K_PHY_PLL_RF5111;
00467 }
00468
00469 if (flags & CHANNEL_2GHZ) {
00470 mode |= AR5K_PHY_MODE_FREQ_2GHZ;
00471 clock |= AR5K_PHY_PLL_44MHZ;
00472
00473 if (flags & CHANNEL_CCK) {
00474 mode |= AR5K_PHY_MODE_MOD_CCK;
00475 } else if (flags & CHANNEL_OFDM) {
00476
00477
00478
00479
00480
00481
00482 if (ah->ah_version == AR5K_AR5211)
00483 mode |= AR5K_PHY_MODE_MOD_OFDM;
00484 else
00485 mode |= AR5K_PHY_MODE_MOD_DYN;
00486 } else {
00487 ATH5K_ERR(ah->ah_sc,
00488 "invalid radio modulation mode\n");
00489 return -EINVAL;
00490 }
00491 } else if (flags & CHANNEL_5GHZ) {
00492 mode |= AR5K_PHY_MODE_FREQ_5GHZ;
00493
00494 if (ah->ah_radio == AR5K_RF5413)
00495 clock = AR5K_PHY_PLL_40MHZ_5413;
00496 else
00497 clock |= AR5K_PHY_PLL_40MHZ;
00498
00499 if (flags & CHANNEL_OFDM)
00500 mode |= AR5K_PHY_MODE_MOD_OFDM;
00501 else {
00502 ATH5K_ERR(ah->ah_sc,
00503 "invalid radio modulation mode\n");
00504 return -EINVAL;
00505 }
00506 } else {
00507 ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n");
00508 return -EINVAL;
00509 }
00510
00511 if (flags & CHANNEL_TURBO)
00512 turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT;
00513 } else {
00514
00515
00516 if (flags & CHANNEL_TURBO)
00517 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
00518 AR5K_PHY_TURBO);
00519 }
00520
00521 if (ah->ah_version != AR5K_AR5210) {
00522
00523
00524 if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
00525 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
00526 udelay(300);
00527 }
00528
00529
00530 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
00531 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
00532 }
00533
00534 return 0;
00535 }
00536
00537
00538
00539
00540
00541
00542
00543
00544
00545
00546 static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
00547 {
00548 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
00549 u32 scal, spending, usec32;
00550
00551
00552
00553 if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
00554 AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&
00555 enable) {
00556
00557
00558 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1);
00559
00560 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61);
00561
00562
00563
00564 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
00565
00566 if ((ah->ah_radio == AR5K_RF5112) ||
00567 (ah->ah_radio == AR5K_RF5413) ||
00568 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
00569 spending = 0x14;
00570 else
00571 spending = 0x18;
00572 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
00573
00574 if ((ah->ah_radio == AR5K_RF5112) ||
00575 (ah->ah_radio == AR5K_RF5413) ||
00576 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
00577 ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT);
00578 ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL);
00579 ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK);
00580 ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY);
00581 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
00582 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02);
00583 } else {
00584 ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT);
00585 ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL);
00586 ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK);
00587 ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY);
00588 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
00589 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03);
00590 }
00591
00592
00593 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,
00594 AR5K_PCICFG_SLEEP_CLOCK_EN);
00595
00596 } else {
00597
00598
00599
00600 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
00601 AR5K_PCICFG_SLEEP_CLOCK_EN);
00602
00603 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
00604 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0);
00605
00606 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
00607 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
00608
00609 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
00610 scal = AR5K_PHY_SCAL_32MHZ_2417;
00611 else if (ee->ee_is_hb63)
00612 scal = AR5K_PHY_SCAL_32MHZ_HB63;
00613 else
00614 scal = AR5K_PHY_SCAL_32MHZ;
00615 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
00616
00617 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
00618 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
00619
00620 if ((ah->ah_radio == AR5K_RF5112) ||
00621 (ah->ah_radio == AR5K_RF5413) ||
00622 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
00623 spending = 0x14;
00624 else
00625 spending = 0x18;
00626 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
00627
00628 if ((ah->ah_radio == AR5K_RF5112) ||
00629 (ah->ah_radio == AR5K_RF5413))
00630 usec32 = 39;
00631 else
00632 usec32 = 31;
00633 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, usec32);
00634
00635 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
00636 }
00637 return;
00638 }
00639
00640
00641 static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
00642 struct ieee80211_channel *channel)
00643 {
00644 if (ah->ah_version == AR5K_AR5212 &&
00645 ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
00646
00647
00648 ath5k_hw_reg_write(ah,
00649 (AR5K_REG_SM(2,
00650 AR5K_PHY_ADC_CTL_INBUFGAIN_OFF) |
00651 AR5K_REG_SM(2,
00652 AR5K_PHY_ADC_CTL_INBUFGAIN_ON) |
00653 AR5K_PHY_ADC_CTL_PWD_DAC_OFF |
00654 AR5K_PHY_ADC_CTL_PWD_ADC_OFF),
00655 AR5K_PHY_ADC_CTL);
00656
00657
00658
00659
00660 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
00661 AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR);
00662
00663 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
00664 AR5K_PHY_DAG_CCK_CTL_RSSI_THR, 2);
00665
00666
00667 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);
00668 }
00669
00670
00671 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212B)
00672 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BLUETOOTH);
00673
00674
00675 if (ah->ah_phy_revision > AR5K_SREV_PHY_5212B)
00676 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
00677 AR5K_TXCFG_DCU_DBL_BUF_DIS);
00678
00679
00680 if (ah->ah_version == AR5K_AR5212) {
00681 u32 scal;
00682 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
00683 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
00684 scal = AR5K_PHY_SCAL_32MHZ_2417;
00685 else if (ee->ee_is_hb63)
00686 scal = AR5K_PHY_SCAL_32MHZ_HB63;
00687 else
00688 scal = AR5K_PHY_SCAL_32MHZ;
00689 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
00690 }
00691
00692
00693 if ((ah->ah_radio == AR5K_RF5413) ||
00694 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
00695 u32 fast_adc = true;
00696
00697 if (channel->center_freq == 2462 ||
00698 channel->center_freq == 2467)
00699 fast_adc = 0;
00700
00701
00702 if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc)
00703 ath5k_hw_reg_write(ah, fast_adc,
00704 AR5K_PHY_FAST_ADC);
00705 }
00706
00707
00708 if (ah->ah_radio == AR5K_RF5112 &&
00709 ah->ah_radio_5ghz_revision <
00710 AR5K_SREV_RAD_5112A) {
00711 u32 data;
00712 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
00713 AR5K_PHY_CCKTXCTL);
00714 if (channel->hw_value & CHANNEL_5GHZ)
00715 data = 0xffb81020;
00716 else
00717 data = 0xffb80d20;
00718 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
00719 }
00720
00721 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
00722 u32 usec_reg;
00723
00724
00725
00726
00727 usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
00728 ath5k_hw_reg_write(ah, usec_reg & (AR5K_USEC_1 |
00729 AR5K_USEC_32 |
00730 AR5K_USEC_TX_LATENCY_5211 |
00731 AR5K_REG_SM(29,
00732 AR5K_USEC_RX_LATENCY_5210)),
00733 AR5K_USEC_5211);
00734
00735 ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT);
00736
00737 ath5k_hw_reg_write(ah, 0x08, AR5K_PHY_SCAL);
00738
00739 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
00740 AR5K_DIAG_SW_ECO_ENABLE);
00741 }
00742 }
00743
00744 static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
00745 struct ieee80211_channel *channel, u8 *ant, u8 ee_mode)
00746 {
00747 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
00748 s16 cck_ofdm_pwr_delta;
00749
00750
00751 if (channel->center_freq == 2484)
00752 cck_ofdm_pwr_delta =
00753 ((ee->ee_cck_ofdm_power_delta -
00754 ee->ee_scaled_cck_delta) * 2) / 10;
00755 else
00756 cck_ofdm_pwr_delta =
00757 (ee->ee_cck_ofdm_power_delta * 2) / 10;
00758
00759
00760
00761 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
00762 if (channel->hw_value == CHANNEL_G)
00763 ath5k_hw_reg_write(ah,
00764 AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1),
00765 AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA) |
00766 AR5K_REG_SM((cck_ofdm_pwr_delta * -1),
00767 AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX),
00768 AR5K_PHY_TX_PWR_ADJ);
00769 else
00770 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ);
00771 } else {
00772
00773
00774 ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta;
00775 ah->ah_txpower.txp_cck_ofdm_gainf_delta =
00776 ee->ee_cck_ofdm_gain_delta;
00777 }
00778
00779
00780 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL,
00781 AR5K_PHY_ANT_CTL_SWTABLE_IDLE,
00782 (ah->ah_ant_ctl[ee_mode][0] |
00783 AR5K_PHY_ANT_CTL_TXRX_EN));
00784
00785
00786 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant[0]],
00787 AR5K_PHY_ANT_SWITCH_TABLE_0);
00788 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant[1]],
00789 AR5K_PHY_ANT_SWITCH_TABLE_1);
00790
00791
00792 ath5k_hw_reg_write(ah,
00793 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
00794 AR5K_PHY_NFTHRES);
00795
00796 if ((channel->hw_value & CHANNEL_TURBO) &&
00797 (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) {
00798
00799 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
00800 AR5K_PHY_SETTLING_SWITCH,
00801 ee->ee_switch_settling_turbo[ee_mode]);
00802
00803
00804 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
00805 AR5K_PHY_GAIN_TXRX_ATTEN,
00806 ee->ee_atn_tx_rx_turbo[ee_mode]);
00807
00808
00809 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
00810 AR5K_PHY_DESIRED_SIZE_ADC,
00811 ee->ee_adc_desired_size_turbo[ee_mode]);
00812
00813 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
00814 AR5K_PHY_DESIRED_SIZE_PGA,
00815 ee->ee_pga_desired_size_turbo[ee_mode]);
00816
00817
00818 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
00819 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
00820 ee->ee_margin_tx_rx_turbo[ee_mode]);
00821
00822 } else {
00823
00824 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
00825 AR5K_PHY_SETTLING_SWITCH,
00826 ee->ee_switch_settling[ee_mode]);
00827
00828
00829 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
00830 AR5K_PHY_GAIN_TXRX_ATTEN,
00831 ee->ee_atn_tx_rx[ee_mode]);
00832
00833
00834 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
00835 AR5K_PHY_DESIRED_SIZE_ADC,
00836 ee->ee_adc_desired_size[ee_mode]);
00837
00838 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
00839 AR5K_PHY_DESIRED_SIZE_PGA,
00840 ee->ee_pga_desired_size[ee_mode]);
00841
00842
00843 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
00844 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
00845 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
00846 ee->ee_margin_tx_rx[ee_mode]);
00847 }
00848
00849
00850 ath5k_hw_reg_write(ah,
00851 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
00852 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
00853 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
00854 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4);
00855
00856
00857 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL3,
00858 AR5K_PHY_RF_CTL3_TXE2XLNA_ON,
00859 ee->ee_tx_end2xlna_enable[ee_mode]);
00860
00861
00862 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_NF,
00863 AR5K_PHY_NF_THRESH62,
00864 ee->ee_thr_62[ee_mode]);
00865
00866
00867
00868
00869
00870 if (ath5k_hw_chan_has_spur_noise(ah, channel))
00871 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
00872 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
00873 AR5K_INIT_CYCRSSI_THR1 +
00874 ee->ee_false_detect[ee_mode]);
00875 else
00876 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
00877 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
00878 AR5K_INIT_CYCRSSI_THR1);
00879
00880
00881
00882 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
00883 AR5K_PHY_IQ_CORR_ENABLE |
00884 (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) |
00885 ee->ee_q_cal[ee_mode]);
00886
00887
00888 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1)
00889 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE);
00890
00891 return;
00892 }
00893
00894
00895
00896
00897 int ath5k_hw_reset(struct ath5k_hw *ah,
00898 struct ieee80211_channel *channel, bool change_channel)
00899 {
00900 u32 s_seq[10], s_ant, s_led[3], staid1_flags, tsf_up, tsf_lo;
00901 u32 phy_tst1;
00902 u8 mode, freq, ee_mode, ant[2];
00903 int i, ret;
00904
00905 ATH5K_TRACE(ah->ah_sc);
00906
00907 s_ant = 0;
00908 ee_mode = 0;
00909 staid1_flags = 0;
00910 tsf_up = 0;
00911 tsf_lo = 0;
00912 freq = 0;
00913 mode = 0;
00914
00915
00916
00917
00918
00919 if (ah->ah_version != AR5K_AR5210) {
00920
00921 switch (channel->hw_value & CHANNEL_MODES) {
00922 case CHANNEL_A:
00923 mode = AR5K_MODE_11A;
00924 freq = AR5K_INI_RFGAIN_5GHZ;
00925 ee_mode = AR5K_EEPROM_MODE_11A;
00926 break;
00927 case CHANNEL_G:
00928 mode = AR5K_MODE_11G;
00929 freq = AR5K_INI_RFGAIN_2GHZ;
00930 ee_mode = AR5K_EEPROM_MODE_11G;
00931 break;
00932 case CHANNEL_B:
00933 mode = AR5K_MODE_11B;
00934 freq = AR5K_INI_RFGAIN_2GHZ;
00935 ee_mode = AR5K_EEPROM_MODE_11B;
00936 break;
00937 case CHANNEL_T:
00938 mode = AR5K_MODE_11A_TURBO;
00939 freq = AR5K_INI_RFGAIN_5GHZ;
00940 ee_mode = AR5K_EEPROM_MODE_11A;
00941 break;
00942 case CHANNEL_TG:
00943 if (ah->ah_version == AR5K_AR5211) {
00944 ATH5K_ERR(ah->ah_sc,
00945 "TurboG mode not available on 5211");
00946 return -EINVAL;
00947 }
00948 mode = AR5K_MODE_11G_TURBO;
00949 freq = AR5K_INI_RFGAIN_2GHZ;
00950 ee_mode = AR5K_EEPROM_MODE_11G;
00951 break;
00952 case CHANNEL_XR:
00953 if (ah->ah_version == AR5K_AR5211) {
00954 ATH5K_ERR(ah->ah_sc,
00955 "XR mode not available on 5211");
00956 return -EINVAL;
00957 }
00958 mode = AR5K_MODE_XR;
00959 freq = AR5K_INI_RFGAIN_5GHZ;
00960 ee_mode = AR5K_EEPROM_MODE_11A;
00961 break;
00962 default:
00963 ATH5K_ERR(ah->ah_sc,
00964 "invalid channel: %d\n", channel->center_freq);
00965 return -EINVAL;
00966 }
00967
00968 if (change_channel) {
00969
00970
00971
00972
00973
00974 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
00975
00976 for (i = 0; i < 10; i++)
00977 s_seq[i] = ath5k_hw_reg_read(ah,
00978 AR5K_QUEUE_DCU_SEQNUM(i));
00979
00980 } else {
00981 s_seq[0] = ath5k_hw_reg_read(ah,
00982 AR5K_QUEUE_DCU_SEQNUM(0));
00983 }
00984
00985
00986
00987
00988
00989
00990
00991
00992
00993
00994
00995
00996
00997
00998 if (ah->ah_version == AR5K_AR5211) {
00999 tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
01000 tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
01001 }
01002 }
01003
01004
01005 s_ant = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
01006
01007 if (ah->ah_version == AR5K_AR5212) {
01008
01009
01010
01011 ath5k_hw_set_sleep_clock(ah, false);
01012
01013
01014
01015
01016 if (change_channel && ah->ah_rf_banks != NULL)
01017 ath5k_hw_gainf_calibrate(ah);
01018 }
01019 }
01020
01021
01022 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) &
01023 AR5K_PCICFG_LEDSTATE;
01024 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
01025 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
01026
01027
01028
01029 staid1_flags = ath5k_hw_reg_read(ah, AR5K_STA_ID1) &
01030 (AR5K_STA_ID1_DEFAULT_ANTENNA |
01031 AR5K_STA_ID1_DESC_ANTENNA |
01032 AR5K_STA_ID1_RTS_DEF_ANTENNA |
01033 AR5K_STA_ID1_ACKCTS_6MB |
01034 AR5K_STA_ID1_BASE_RATE_11B |
01035 AR5K_STA_ID1_SELFGEN_DEF_ANT);
01036
01037
01038 ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false);
01039 if (ret)
01040 return ret;
01041
01042
01043 if (ah->ah_mac_srev >= AR5K_SREV_AR5211)
01044 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
01045 else
01046 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40,
01047 AR5K_PHY(0));
01048
01049
01050 ret = ath5k_hw_write_initvals(ah, mode, change_channel);
01051 if (ret)
01052 return ret;
01053
01054
01055
01056
01057 if (ah->ah_version != AR5K_AR5210) {
01058
01059
01060
01061
01062
01063 ret = ath5k_hw_rfgain_init(ah, freq);
01064 if (ret)
01065 return ret;
01066
01067 mdelay(1);
01068
01069
01070
01071
01072
01073
01074 ath5k_hw_tweak_initval_settings(ah, channel);
01075
01076
01077
01078
01079 ret = ath5k_hw_txpower(ah, channel, ee_mode,
01080 ah->ah_txpower.txp_max_pwr / 2);
01081 if (ret)
01082 return ret;
01083
01084
01085
01086
01087
01088 if (ah->ah_version == AR5K_AR5212)
01089 ath5k_hw_write_rate_duration(ah, mode);
01090
01091
01092
01093
01094 ret = ath5k_hw_rfregs_init(ah, channel, mode);
01095 if (ret)
01096 return ret;
01097
01098
01099
01100 if (ah->ah_version == AR5K_AR5212 &&
01101 channel->hw_value & CHANNEL_OFDM) {
01102 struct ath5k_eeprom_info *ee =
01103 &ah->ah_capabilities.cap_eeprom;
01104
01105 ret = ath5k_hw_write_ofdm_timings(ah, channel);
01106 if (ret)
01107 return ret;
01108
01109
01110
01111
01112
01113 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 ||
01114 (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
01115 ee->ee_version >= AR5K_EEPROM_VERSION_5_3))
01116 ath5k_hw_set_spur_mitigation_filter(ah,
01117 channel);
01118 }
01119
01120
01121
01122 if (ah->ah_radio == AR5K_RF5111) {
01123 if (mode == AR5K_MODE_11B)
01124 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
01125 AR5K_TXCFG_B_MODE);
01126 else
01127 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
01128 AR5K_TXCFG_B_MODE);
01129 }
01130
01131
01132
01133
01134
01135 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A)
01136 ant[0] = ant[1] = AR5K_ANT_SWTABLE_A;
01137 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B)
01138 ant[0] = ant[1] = AR5K_ANT_SWTABLE_B;
01139 else {
01140 ant[0] = AR5K_ANT_SWTABLE_A;
01141 ant[1] = AR5K_ANT_SWTABLE_B;
01142 }
01143
01144
01145 ath5k_hw_commit_eeprom_settings(ah, channel, ant, ee_mode);
01146
01147 } else {
01148
01149
01150
01151
01152
01153
01154 mdelay(1);
01155
01156 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
01157 mdelay(1);
01158 }
01159
01160
01161
01162
01163
01164
01165 if (ah->ah_version != AR5K_AR5210) {
01166
01167 if (change_channel) {
01168 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
01169 for (i = 0; i < 10; i++)
01170 ath5k_hw_reg_write(ah, s_seq[i],
01171 AR5K_QUEUE_DCU_SEQNUM(i));
01172 } else {
01173 ath5k_hw_reg_write(ah, s_seq[0],
01174 AR5K_QUEUE_DCU_SEQNUM(0));
01175 }
01176
01177
01178 if (ah->ah_version == AR5K_AR5211) {
01179 ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32);
01180 ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32);
01181 }
01182 }
01183
01184 ath5k_hw_reg_write(ah, s_ant, AR5K_DEFAULT_ANTENNA);
01185 }
01186
01187
01188 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
01189
01190
01191 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
01192 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
01193
01194
01195 ath5k_hw_reg_write(ah, AR5K_LOW_ID(ah->ah_sta_id),
01196 AR5K_STA_ID0);
01197 ath5k_hw_reg_write(ah, staid1_flags | AR5K_HIGH_ID(ah->ah_sta_id),
01198 AR5K_STA_ID1);
01199
01200
01201
01202
01203
01204
01205
01206 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
01207
01208
01209 ath5k_hw_set_opmode(ah);
01210
01211
01212
01213 if (ah->ah_version != AR5K_AR5210)
01214 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
01215
01216
01217
01218
01219
01220
01221
01222
01223
01224 ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES |
01225 AR5K_TUNE_BMISS_THRES <<
01226 AR5K_RSSI_THR_BMISS_S),
01227 AR5K_RSSI_THR);
01228
01229
01230 if (ah->ah_mac_srev >= AR5K_SREV_AR2413) {
01231 ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL);
01232 ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL);
01233 }
01234
01235
01236 if (ah->ah_version == AR5K_AR5212) {
01237 ath5k_hw_reg_write(ah,
01238 AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) |
01239 AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET) |
01240 AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET),
01241 AR5K_QOS_NOACK);
01242 }
01243
01244
01245
01246
01247
01248
01249
01250 ret = ath5k_hw_channel(ah, channel);
01251 if (ret)
01252 return ret;
01253
01254
01255
01256
01257
01258
01259 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
01260
01261
01262
01263
01264
01265
01266
01267 if (ah->ah_version != AR5K_AR5210) {
01268 u32 delay;
01269 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
01270 AR5K_PHY_RX_DELAY_M;
01271 delay = (channel->hw_value & CHANNEL_CCK) ?
01272 ((delay << 2) / 22) : (delay / 10);
01273
01274 udelay(100 + (2 * delay));
01275 } else {
01276 mdelay(1);
01277 }
01278
01279
01280
01281
01282
01283 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
01284 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
01285 for (i = 0; i <= 20; i++) {
01286 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
01287 break;
01288 udelay(200);
01289 }
01290 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
01291
01292
01293
01294
01295
01296
01297
01298
01299
01300
01301
01302
01303
01304
01305
01306
01307
01308
01309
01310
01311 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
01312 AR5K_PHY_AGCCTL_CAL);
01313
01314
01315
01316 ah->ah_calibration = false;
01317 if (!(mode == AR5K_MODE_11B)) {
01318 ah->ah_calibration = true;
01319 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
01320 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
01321 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
01322 AR5K_PHY_IQ_RUN);
01323 }
01324
01325
01326
01327 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
01328 AR5K_PHY_AGCCTL_CAL, 0, false)) {
01329 ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n",
01330 channel->center_freq);
01331 }
01332
01333
01334
01335
01336
01337
01338
01339
01340
01341
01342
01343
01344
01345
01346 ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
01347
01348
01349 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
01350
01351
01352
01353
01354
01355
01356
01357
01358
01359
01360
01361
01362
01363 for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) {
01364 ret = ath5k_hw_reset_tx_queue(ah, i);
01365 if (ret) {
01366 ATH5K_ERR(ah->ah_sc,
01367 "failed to reset TX queue #%d\n", i);
01368 return ret;
01369 }
01370 }
01371
01372
01373
01374
01375
01376
01377
01378
01379
01380
01381
01382
01383
01384
01385
01386
01387
01388
01389
01390 if (ah->ah_version != AR5K_AR5210) {
01391 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
01392 AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B);
01393 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG,
01394 AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B);
01395 }
01396
01397
01398 if (ah->ah_version != AR5K_AR5210)
01399 ath5k_hw_set_imr(ah, ah->ah_imr);
01400
01401
01402
01403
01404
01405 if (ah->ah_version == AR5K_AR5212)
01406 ath5k_hw_set_sleep_clock(ah, true);
01407
01408
01409
01410
01411 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE |
01412 AR5K_BEACON_RESET_TSF);
01413
01414 return 0;
01415 }
01416
01417 #undef _ATH5K_RESET