stm32h7xx_hal_flash_ex.c

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/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
 
#ifdef HAL_FLASH_MODULE_ENABLED
 
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define FLASH_TIMEOUT_VALUE       50000U /* 50 s */
 
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks);
static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks);
static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Bank);
static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank);
static void FLASH_OB_RDPConfig(uint32_t RDPLevel);
static uint32_t FLASH_OB_GetRDP(void);
static void FLASH_OB_PCROPConfig(uint32_t PCROConfigRDP, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks);
static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr,uint32_t *PCROPEndAddr, uint32_t Bank);
static void FLASH_OB_BOR_LevelConfig(uint32_t Level);
static uint32_t FLASH_OB_GetBOR(void);
static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
static uint32_t FLASH_OB_GetUser(void);
static void FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1);
static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1);
static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks);
static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank);
static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank);
static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank);
 
#if defined (DUAL_CORE)
static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1);
static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1);
#endif /*DUAL_CORE*/
 
#if defined (FLASH_OTPBL_LOCKBL)
static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block);
static uint32_t FLASH_OB_OTP_GetLock(void);
#endif /* FLASH_OTPBL_LOCKBL */
 
#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
static void FLASH_OB_SharedRAM_Config(uint32_t SharedRamConfig);
static uint32_t FLASH_OB_SharedRAM_GetConfig(void);
#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
 
#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
static void FLASH_OB_CPUFreq_BoostConfig(uint32_t FreqBoost);
static uint32_t FLASH_OB_CPUFreq_GetBoost(void);
#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
 
/* Exported functions ---------------------------------------------------------*/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
{
  HAL_StatusTypeDef status = HAL_OK;
  uint32_t sector_index;
 
  /* Check the parameters */
  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
  assert_param(IS_FLASH_BANK(pEraseInit->Banks));
 
  /* Process Locked */
  __HAL_LOCK(&pFlash);
 
  /* Reset error code */
  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 
  /* Wait for last operation to be completed on Bank1 */
  if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
  {
    if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
    {
      status = HAL_ERROR;
    }
  }
 
#if defined (DUAL_BANK)
  /* Wait for last operation to be completed on Bank2 */
  if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
  {
    if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
    {
      status = HAL_ERROR;
    }
  }
#endif /* DUAL_BANK */
 
  if(status == HAL_OK)
  {
    if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
    {
      /* Mass erase to be done */
      FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks);
 
      /* Wait for last operation to be completed on Bank 1 */
      if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
      {
        if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
        {
          status = HAL_ERROR;
        }
        /* if the erase operation is completed, disable the Bank1 BER Bit */
        FLASH->CR1 &= (~FLASH_CR_BER);
      }
#if defined (DUAL_BANK)
      /* Wait for last operation to be completed on Bank 2 */
      if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
      {
        if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
        {
          status = HAL_ERROR;
        }
        /* if the erase operation is completed, disable the Bank2 BER Bit */
        FLASH->CR2 &= (~FLASH_CR_BER);
      }
#endif /* DUAL_BANK */
    }
    else
    {
      /*Initialization of SectorError variable*/
      *SectorError = 0xFFFFFFFFU;
 
      /* Erase by sector by sector to be done*/
      for(sector_index = pEraseInit->Sector; sector_index < (pEraseInit->NbSectors + pEraseInit->Sector); sector_index++)
      {
        FLASH_Erase_Sector(sector_index, pEraseInit->Banks, pEraseInit->VoltageRange);
 
        if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
        {
          /* Wait for last operation to be completed */
          status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
 
          /* If the erase operation is completed, disable the SER Bit */
          FLASH->CR1 &= (~(FLASH_CR_SER | FLASH_CR_SNB));
        }
#if defined (DUAL_BANK)
        if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
        {
          /* Wait for last operation to be completed */
          status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
 
          /* If the erase operation is completed, disable the SER Bit */
          FLASH->CR2 &= (~(FLASH_CR_SER | FLASH_CR_SNB));
        }
#endif /* DUAL_BANK */
 
        if(status != HAL_OK)
        {
          /* In case of error, stop erase procedure and return the faulty sector */
          *SectorError = sector_index;
          break;
        }
      }
    }
  }
 
  /* Process Unlocked */
  __HAL_UNLOCK(&pFlash);
 
  return status;
}
 
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
{
  HAL_StatusTypeDef status = HAL_OK;
 
  /* Check the parameters */
  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
  assert_param(IS_FLASH_BANK(pEraseInit->Banks));
 
  /* Process Locked */
  __HAL_LOCK(&pFlash);
 
  /* Reset error code */
  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 
  /* Wait for last operation to be completed on Bank 1 */
  if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
  {
    if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
    {
      status = HAL_ERROR;
    }
  }
 
#if defined (DUAL_BANK)
  /* Wait for last operation to be completed on Bank 2 */
  if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
  {
    if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
    {
      status = HAL_ERROR;
    }
  }
#endif /* DUAL_BANK */
 
  if (status != HAL_OK)
  {
    /* Process Unlocked */
    __HAL_UNLOCK(&pFlash);
  }
  else
  {
    if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
    {
      /* Enable End of Operation and Error interrupts for Bank 1 */
#if defined (FLASH_CR_OPERRIE)
      __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1     | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
                                  FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
#else
      __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1     | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
                                  FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
#endif /* FLASH_CR_OPERRIE */
    }
#if defined (DUAL_BANK)
    if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
    {
      /* Enable End of Operation and Error interrupts for Bank 2 */
#if defined (FLASH_CR_OPERRIE)
      __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2     | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
                                  FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
#else
      __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2     | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
                                  FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
#endif /* FLASH_CR_OPERRIE */
    }
#endif /* DUAL_BANK */
 
    if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
    {
      /*Mass erase to be done*/
      if(pEraseInit->Banks == FLASH_BANK_1)
      {
        pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK1;
      }
#if defined (DUAL_BANK)
      else if(pEraseInit->Banks == FLASH_BANK_2)
      {
        pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK2;
      }
#endif /* DUAL_BANK */
      else
      {
        pFlash.ProcedureOnGoing = FLASH_PROC_ALLBANK_MASSERASE;
      }
 
      FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks);
    }
    else
    {
      /* Erase by sector to be done */
#if defined (DUAL_BANK)
      if(pEraseInit->Banks == FLASH_BANK_1)
      {
        pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1;
      }
      else
      {
        pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK2;
      }
#else
      pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1;
#endif /* DUAL_BANK */
 
      pFlash.NbSectorsToErase = pEraseInit->NbSectors;
      pFlash.Sector = pEraseInit->Sector;
      pFlash.VoltageForErase = pEraseInit->VoltageRange;
 
      /* Erase first sector and wait for IT */
      FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->Banks, pEraseInit->VoltageRange);
    }
  }
 
  return status;
}
 
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
{
  HAL_StatusTypeDef status;
 
  /* Check the parameters */
  assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
 
  /* Process Locked */
  __HAL_LOCK(&pFlash);
 
  /* Reset Error Code */
  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 
  /* Wait for last operation to be completed */
  if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
  {
    status = HAL_ERROR;
  }
#if defined (DUAL_BANK)
  else if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
  {
    status = HAL_ERROR;
  }
#endif /* DUAL_BANK */
  else
  {
    status = HAL_OK;
  }
 
  if(status == HAL_OK)
  {
    /*Write protection configuration*/
    if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
    {
      assert_param(IS_WRPSTATE(pOBInit->WRPState));
 
      if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
      {
        /*Enable of Write protection on the selected Sector*/
        FLASH_OB_EnableWRP(pOBInit->WRPSector,pOBInit->Banks);
      }
      else
      {
        /*Disable of Write protection on the selected Sector*/
        FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks);
      }
    }
 
    /* Read protection configuration */
    if((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U)
    {
      /* Configure the Read protection level */
      FLASH_OB_RDPConfig(pOBInit->RDPLevel);
    }
 
    /* User Configuration */
    if((pOBInit->OptionType & OPTIONBYTE_USER) != 0U)
    {
      /* Configure the user option bytes */
      FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig);
    }
 
    /* PCROP Configuration */
    if((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U)
    {
      assert_param(IS_FLASH_BANK(pOBInit->Banks));
 
      /*Configure the Proprietary code readout protection */
      FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr, pOBInit->Banks);
    }
 
    /* BOR Level configuration */
    if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
    {
      FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
    }
 
#if defined(DUAL_CORE)
    /* CM7 Boot Address  configuration */
    if((pOBInit->OptionType & OPTIONBYTE_CM7_BOOTADD) == OPTIONBYTE_CM7_BOOTADD)
    {
      FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1);
    }
 
    /* CM4 Boot Address  configuration */
    if((pOBInit->OptionType & OPTIONBYTE_CM4_BOOTADD) == OPTIONBYTE_CM4_BOOTADD)
    {
      FLASH_OB_CM4BootAddConfig(pOBInit->CM4BootConfig, pOBInit->CM4BootAddr0, pOBInit->CM4BootAddr1);
    }
#else /* Single Core*/
    /* Boot Address  configuration */
    if((pOBInit->OptionType & OPTIONBYTE_BOOTADD) == OPTIONBYTE_BOOTADD)
    {
      FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1);
    }
#endif /*DUAL_CORE*/
 
    /* Secure area configuration */
    if((pOBInit->OptionType & OPTIONBYTE_SECURE_AREA) == OPTIONBYTE_SECURE_AREA)
    {
      FLASH_OB_SecureAreaConfig(pOBInit->SecureAreaConfig, pOBInit->SecureAreaStartAddr, pOBInit->SecureAreaEndAddr,pOBInit->Banks);
    }
 
#if defined(FLASH_OTPBL_LOCKBL)
    /* OTP Block Lock configuration */
    if((pOBInit->OptionType & OPTIONBYTE_OTP_LOCK) == OPTIONBYTE_OTP_LOCK)
    {
      FLASH_OB_OTP_LockConfig(pOBInit->OTPBlockLock);
    }
#endif /* FLASH_OTPBL_LOCKBL */
 
#if defined(FLASH_OPTSR2_TCM_AXI_SHARED)
    /* TCM / AXI Shared RAM configuration */
    if((pOBInit->OptionType & OPTIONBYTE_SHARED_RAM) == OPTIONBYTE_SHARED_RAM)
    {
      FLASH_OB_SharedRAM_Config(pOBInit->SharedRamConfig);
    }
#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
 
#if defined(FLASH_OPTSR2_CPUFREQ_BOOST)
    /* CPU Frequency Boost configuration */
    if((pOBInit->OptionType & OPTIONBYTE_FREQ_BOOST) == OPTIONBYTE_FREQ_BOOST)
    {
      FLASH_OB_CPUFreq_BoostConfig(pOBInit->FreqBoostState);
    }
#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
  }
 
  /* Process Unlocked */
  __HAL_UNLOCK(&pFlash);
 
  return status;
}
 
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
{
  pOBInit->OptionType = (OPTIONBYTE_USER | OPTIONBYTE_RDP | OPTIONBYTE_BOR);
 
  /* Get Read protection level */
  pOBInit->RDPLevel = FLASH_OB_GetRDP();
 
  /* Get the user option bytes */
  pOBInit->USERConfig = FLASH_OB_GetUser();
 
  /*Get BOR Level*/
  pOBInit->BORLevel = FLASH_OB_GetBOR();
 
#if defined (DUAL_BANK)
  if ((pOBInit->Banks == FLASH_BANK_1) || (pOBInit->Banks == FLASH_BANK_2))
#else
  if (pOBInit->Banks == FLASH_BANK_1)
#endif /* DUAL_BANK */
  {
    pOBInit->OptionType |= (OPTIONBYTE_WRP | OPTIONBYTE_PCROP | OPTIONBYTE_SECURE_AREA);
 
    /* Get write protection on the selected area */
    FLASH_OB_GetWRP(&(pOBInit->WRPState), &(pOBInit->WRPSector), pOBInit->Banks);
 
    /* Get the Proprietary code readout protection */
    FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr), pOBInit->Banks);
 
    /*Get Bank Secure area*/
    FLASH_OB_GetSecureArea(&(pOBInit->SecureAreaConfig), &(pOBInit->SecureAreaStartAddr), &(pOBInit->SecureAreaEndAddr), pOBInit->Banks);
  }
 
  /*Get Boot Address*/
  FLASH_OB_GetBootAdd(&(pOBInit->BootAddr0), &(pOBInit->BootAddr1));
#if defined(DUAL_CORE)
  pOBInit->OptionType |= OPTIONBYTE_CM7_BOOTADD | OPTIONBYTE_CM4_BOOTADD;
 
  /*Get CM4 Boot Address*/
  FLASH_OB_GetCM4BootAdd(&(pOBInit->CM4BootAddr0), &(pOBInit->CM4BootAddr1));
#else
  pOBInit->OptionType |= OPTIONBYTE_BOOTADD;
#endif /*DUAL_CORE*/
 
#if defined (FLASH_OTPBL_LOCKBL)
  pOBInit->OptionType |= OPTIONBYTE_OTP_LOCK;
 
  /* Get OTP Block Lock */
  pOBInit->OTPBlockLock = FLASH_OB_OTP_GetLock();
#endif /* FLASH_OTPBL_LOCKBL */
 
#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
  pOBInit->OptionType |= OPTIONBYTE_SHARED_RAM;
 
  /* Get TCM / AXI Shared RAM */
  pOBInit->SharedRamConfig = FLASH_OB_SharedRAM_GetConfig();
#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
 
#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
  pOBInit->OptionType |= OPTIONBYTE_FREQ_BOOST;
 
  /* Get CPU Frequency Boost */
  pOBInit->FreqBoostState = FLASH_OB_CPUFreq_GetBoost();
#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
}
 
HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void)
{
  if(READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U)
  {
    /* Authorize the FLASH Bank1 Registers access */
    WRITE_REG(FLASH->KEYR1, FLASH_KEY1);
    WRITE_REG(FLASH->KEYR1, FLASH_KEY2);
 
    /* Verify Flash Bank1 is unlocked */
    if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U)
    {
      return HAL_ERROR;
    }
  }
 
  return HAL_OK;
}
 
HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void)
{
  /* Set the LOCK Bit to lock the FLASH Bank1 Registers access */
  SET_BIT(FLASH->CR1, FLASH_CR_LOCK);
  return HAL_OK;
}
 
#if defined (DUAL_BANK)
 
HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void)
{
  if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
  {
    /* Authorize the FLASH Bank2 Registers access */
    WRITE_REG(FLASH->KEYR2, FLASH_KEY1);
    WRITE_REG(FLASH->KEYR2, FLASH_KEY2);
 
    /* Verify Flash Bank1 is unlocked */
    if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
    {
      return HAL_ERROR;
    }
  }
 
  return HAL_OK;
}
 
HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void)
{
  /* Set the LOCK Bit to lock the FLASH Bank2 Registers access */
  SET_BIT(FLASH->CR2, FLASH_CR_LOCK);
  return HAL_OK;
}
#endif /* DUAL_BANK */
 
/*
  * @brief  Perform a CRC computation on the specified FLASH memory area
  * @param  pCRCInit pointer to an FLASH_CRCInitTypeDef structure that
  *         contains the configuration information for the CRC computation.
  * @note   CRC computation uses CRC-32 (Ethernet) polynomial 0x4C11DB7
  * @note   The application should avoid running a CRC on PCROP or secure-only
  *         user Flash memory area since it may alter the expected CRC value.
  *         A special error flag (CRC read error: CRCRDERR) can be used to
  *         detect such a case.
  * @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result)
{
  HAL_StatusTypeDef status;
  uint32_t sector_index;
 
  /* Check the parameters */
  assert_param(IS_FLASH_BANK_EXCLUSIVE(pCRCInit->Bank));
  assert_param(IS_FLASH_TYPECRC(pCRCInit->TypeCRC));
 
  /* Wait for OB change operation to be completed */
  status = FLASH_OB_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
 
  if (status == HAL_OK)
  {
    if (pCRCInit->Bank == FLASH_BANK_1)
    {
      /* Enable CRC feature */
      FLASH->CR1 |= FLASH_CR_CRC_EN;
 
      /* Clear CRC flags in Status Register: CRC end of calculation and CRC read error */
      FLASH->CCR1 |= (FLASH_CCR_CLR_CRCEND | FLASH_CCR_CLR_CRCRDERR);
 
      /* Clear current CRC result, program burst size and define memory area on which CRC has to be computed */
      FLASH->CRCCR1 |= FLASH_CRCCR_CLEAN_CRC | pCRCInit->BurstSize | pCRCInit->TypeCRC;
 
      if (pCRCInit->TypeCRC == FLASH_CRC_SECTORS)
      {
        /* Clear sectors list */
        FLASH->CRCCR1 |= FLASH_CRCCR_CLEAN_SECT;
 
        /* Select CRC sectors */
        for(sector_index = pCRCInit->Sector; sector_index < (pCRCInit->NbSectors + pCRCInit->Sector); sector_index++)
        {
          FLASH_CRC_AddSector(sector_index, FLASH_BANK_1);
        }
      }
      else if (pCRCInit->TypeCRC == FLASH_CRC_BANK)
      {
        /* Enable Bank 1 CRC select bit */
        FLASH->CRCCR1 |= FLASH_CRCCR_ALL_BANK;
      }
      else
      {
        /* Select CRC start and end addresses */
        FLASH_CRC_SelectAddress(pCRCInit->CRCStartAddr, pCRCInit->CRCEndAddr, FLASH_BANK_1);
      }
 
      /* Start the CRC calculation */
      FLASH->CRCCR1 |= FLASH_CRCCR_START_CRC;
 
      /* Wait on CRC busy flag */
      status = FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
 
      /* Return CRC result */
      (*CRC_Result) = FLASH->CRCDATA;
 
      /* Disable CRC feature */
      FLASH->CR1 &= (~FLASH_CR_CRC_EN);
 
      /* Clear CRC flags */
      __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_CRCEND_BANK1 | FLASH_FLAG_CRCRDERR_BANK1);
    }
#if defined (DUAL_BANK)
    else
    {
      /* Enable CRC feature */
      FLASH->CR2 |= FLASH_CR_CRC_EN;
 
      /* Clear CRC flags in Status Register: CRC end of calculation and CRC read error */
      FLASH->CCR2 |= (FLASH_CCR_CLR_CRCEND | FLASH_CCR_CLR_CRCRDERR);
 
      /* Clear current CRC result, program burst size and define memory area on which CRC has to be computed */
      FLASH->CRCCR2 |= FLASH_CRCCR_CLEAN_CRC | pCRCInit->BurstSize | pCRCInit->TypeCRC;
 
      if (pCRCInit->TypeCRC == FLASH_CRC_SECTORS)
      {
        /* Clear sectors list */
        FLASH->CRCCR2 |= FLASH_CRCCR_CLEAN_SECT;
 
        /* Add CRC sectors */
        for(sector_index = pCRCInit->Sector; sector_index < (pCRCInit->NbSectors + pCRCInit->Sector); sector_index++)
        {
          FLASH_CRC_AddSector(sector_index, FLASH_BANK_2);
        }
      }
      else if (pCRCInit->TypeCRC == FLASH_CRC_BANK)
      {
        /* Enable Bank 2 CRC select bit */
        FLASH->CRCCR2 |= FLASH_CRCCR_ALL_BANK;
      }
      else
      {
        /* Select CRC start and end addresses */
        FLASH_CRC_SelectAddress(pCRCInit->CRCStartAddr, pCRCInit->CRCEndAddr, FLASH_BANK_2);
      }
 
      /* Start the CRC calculation */
      FLASH->CRCCR2 |= FLASH_CRCCR_START_CRC;
 
      /* Wait on CRC busy flag */
      status = FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
 
      /* Return CRC result */
      (*CRC_Result) = FLASH->CRCDATA;
 
      /* Disable CRC feature */
      FLASH->CR2 &= (~FLASH_CR_CRC_EN);
 
      /* Clear CRC flags */
      __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_CRCEND_BANK2 | FLASH_FLAG_CRCRDERR_BANK2);
    }
#endif /* DUAL_BANK */
  }
 
  return status;
}
 
/* Private functions ---------------------------------------------------------*/
 
static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks)
{
  /* Check the parameters */
#if defined (FLASH_CR_PSIZE)
  assert_param(IS_VOLTAGERANGE(VoltageRange));
#else
  UNUSED(VoltageRange);
#endif /* FLASH_CR_PSIZE */
  assert_param(IS_FLASH_BANK(Banks));
 
#if defined (DUAL_BANK)
  /* Flash Mass Erase */
  if((Banks & FLASH_BANK_BOTH) == FLASH_BANK_BOTH)
  {
#if defined (FLASH_CR_PSIZE)
    /* Reset Program/erase VoltageRange for Bank1 and Bank2 */
    FLASH->CR1 &= (~FLASH_CR_PSIZE);
    FLASH->CR2 &= (~FLASH_CR_PSIZE);
 
    /* Set voltage range */
    FLASH->CR1 |= VoltageRange;
    FLASH->CR2 |= VoltageRange;
#endif /* FLASH_CR_PSIZE */
 
    /* Set Mass Erase Bit */
    FLASH->OPTCR |= FLASH_OPTCR_MER;
  }
  else
#endif /* DUAL_BANK */
  {
    /* Proceed to erase Flash Bank  */
    if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
    {
#if defined (FLASH_CR_PSIZE)
      /* Set Program/erase VoltageRange for Bank1 */
      FLASH->CR1 &= (~FLASH_CR_PSIZE);
      FLASH->CR1 |=  VoltageRange;
#endif /* FLASH_CR_PSIZE */
 
      /* Erase Bank1 */
      FLASH->CR1 |= (FLASH_CR_BER | FLASH_CR_START);
    }
 
#if defined (DUAL_BANK)
    if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
    {
#if defined (FLASH_CR_PSIZE)
      /* Set Program/erase VoltageRange for Bank2 */
      FLASH->CR2 &= (~FLASH_CR_PSIZE);
      FLASH->CR2 |= VoltageRange;
#endif /* FLASH_CR_PSIZE */
 
      /* Erase Bank2 */
      FLASH->CR2 |= (FLASH_CR_BER | FLASH_CR_START);
    }
#endif /* DUAL_BANK */
  }
}
 
void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange)
{
  assert_param(IS_FLASH_SECTOR(Sector));
  assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
#if defined (FLASH_CR_PSIZE)
  assert_param(IS_VOLTAGERANGE(VoltageRange));
#else
  UNUSED(VoltageRange);
#endif /* FLASH_CR_PSIZE */
 
  if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
  {
#if defined (FLASH_CR_PSIZE)
    /* Reset Program/erase VoltageRange and Sector Number for Bank1 */
    FLASH->CR1 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB);
 
    FLASH->CR1 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
#else
    /* Reset Sector Number for Bank1 */
    FLASH->CR1 &= ~(FLASH_CR_SNB);
 
    FLASH->CR1 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
#endif /* FLASH_CR_PSIZE */
  }
 
#if defined (DUAL_BANK)
  if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
  {
#if defined (FLASH_CR_PSIZE)
    /* Reset Program/erase VoltageRange and Sector Number for Bank2 */
    FLASH->CR2 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB);
 
    FLASH->CR2 |= (FLASH_CR_SER | VoltageRange  | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
#else
    /* Reset Sector Number for Bank2 */
    FLASH->CR2 &= ~(FLASH_CR_SNB);
 
    FLASH->CR2 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
#endif /* FLASH_CR_PSIZE */
  }
#endif /* DUAL_BANK */
}
 
static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
{
  /* Check the parameters */
  assert_param(IS_OB_WRP_SECTOR(WRPSector));
  assert_param(IS_FLASH_BANK(Banks));
 
  if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
  {
    /* Enable Write Protection for bank 1 */
    FLASH->WPSN_PRG1 &= (~(WRPSector & FLASH_WPSN_WRPSN));
  }
 
#if defined (DUAL_BANK)
  if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
  {
    /* Enable Write Protection for bank 2 */
    FLASH->WPSN_PRG2 &= (~(WRPSector & FLASH_WPSN_WRPSN));
  }
#endif /* DUAL_BANK */
}
 
static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
{
  /* Check the parameters */
  assert_param(IS_OB_WRP_SECTOR(WRPSector));
  assert_param(IS_FLASH_BANK(Banks));
 
  if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
  {
    /* Disable Write Protection for bank 1 */
    FLASH->WPSN_PRG1 |= (WRPSector & FLASH_WPSN_WRPSN);
  }
 
#if defined (DUAL_BANK)
  if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
  {
    /* Disable Write Protection for bank 2 */
    FLASH->WPSN_PRG2 |= (WRPSector & FLASH_WPSN_WRPSN);
  }
#endif /* DUAL_BANK */
}
 
static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank)
{
  uint32_t regvalue = 0U;
 
  if(Bank == FLASH_BANK_1)
  {
    regvalue = FLASH->WPSN_CUR1;
  }
 
#if defined (DUAL_BANK)
  if(Bank == FLASH_BANK_2)
  {
    regvalue = FLASH->WPSN_CUR2;
  }
#endif /* DUAL_BANK */
 
  (*WRPSector) = (~regvalue) & FLASH_WPSN_WRPSN;
 
  if(*WRPSector == 0U)
  {
    (*WRPState) = OB_WRPSTATE_DISABLE;
  }
  else
  {
    (*WRPState) = OB_WRPSTATE_ENABLE;
  }
}
 
static void FLASH_OB_RDPConfig(uint32_t RDPLevel)
{
  /* Check the parameters */
  assert_param(IS_OB_RDP_LEVEL(RDPLevel));
 
  /* Configure the RDP level in the option bytes register */
  MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_RDP, RDPLevel);
}
 
static uint32_t FLASH_OB_GetRDP(void)
{
  uint32_t rdp_level = READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_RDP);
  
  if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2))
  {
    return (OB_RDP_LEVEL_1);
  }
  else
  {
    return rdp_level;
  }
}
 
#if defined(DUAL_CORE)
 
#else
 
#endif /*DUAL_CORE*/
static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
{
  uint32_t optr_reg_val = 0;
  uint32_t optr_reg_mask = 0;
 
  /* Check the parameters */
  assert_param(IS_OB_USER_TYPE(UserType));
 
  if((UserType & OB_USER_IWDG1_SW) != 0U)
  {
    /* IWDG_HW option byte should be modified */
    assert_param(IS_OB_IWDG1_SOURCE(UserConfig & FLASH_OPTSR_IWDG1_SW));
 
    /* Set value and mask for IWDG_HW option byte */
    optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG1_SW);
    optr_reg_mask |= FLASH_OPTSR_IWDG1_SW;
  }
#if defined(DUAL_CORE)
  if((UserType & OB_USER_IWDG2_SW) != 0U)
  {
    /* IWDG2_SW option byte should be modified */
    assert_param(IS_OB_IWDG2_SOURCE(UserConfig & FLASH_OPTSR_IWDG2_SW));
 
    /* Set value and mask for IWDG2_SW option byte */
    optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG2_SW);
    optr_reg_mask |= FLASH_OPTSR_IWDG2_SW;
  }
#endif /*DUAL_CORE*/
  if((UserType & OB_USER_NRST_STOP_D1) != 0U)
  {
    /* NRST_STOP option byte should be modified */
    assert_param(IS_OB_STOP_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STOP_D1));
 
    /* Set value and mask for NRST_STOP option byte */
    optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STOP_D1);
    optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D1;
  }
 
  if((UserType & OB_USER_NRST_STDBY_D1) != 0U)
  {
    /* NRST_STDBY option byte should be modified */
    assert_param(IS_OB_STDBY_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STBY_D1));
 
    /* Set value and mask for NRST_STDBY option byte */
    optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D1);
    optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D1;
  }
 
  if((UserType & OB_USER_IWDG_STOP) != 0U)
  {
    /* IWDG_STOP option byte should be modified */
    assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTSR_FZ_IWDG_STOP));
 
    /* Set value and mask for IWDG_STOP option byte */
    optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_STOP);
    optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_STOP;
  }
 
  if((UserType & OB_USER_IWDG_STDBY) != 0U)
  {
    /* IWDG_STDBY option byte should be modified */
    assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY));
 
    /* Set value and mask for IWDG_STDBY option byte */
    optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY);
    optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_SDBY;
  }
 
  if((UserType & OB_USER_ST_RAM_SIZE) != 0U)
  {
    /* ST_RAM_SIZE option byte should be modified */
    assert_param(IS_OB_USER_ST_RAM_SIZE(UserConfig & FLASH_OPTSR_ST_RAM_SIZE));
 
    /* Set value and mask for ST_RAM_SIZE option byte */
    optr_reg_val |= (UserConfig & FLASH_OPTSR_ST_RAM_SIZE);
    optr_reg_mask |= FLASH_OPTSR_ST_RAM_SIZE;
  }
 
  if((UserType & OB_USER_SECURITY) != 0U)
  {
    /* SECURITY option byte should be modified */
    assert_param(IS_OB_USER_SECURITY(UserConfig & FLASH_OPTSR_SECURITY));
 
    /* Set value and mask for SECURITY option byte */
    optr_reg_val |= (UserConfig & FLASH_OPTSR_SECURITY);
    optr_reg_mask |= FLASH_OPTSR_SECURITY;
  }
 
#if defined(DUAL_CORE)
  if((UserType & OB_USER_BCM4) != 0U)
  {
    /* BCM4 option byte should be modified */
    assert_param(IS_OB_USER_BCM4(UserConfig & FLASH_OPTSR_BCM4));
 
    /* Set value and mask for BCM4 option byte */
    optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM4);
    optr_reg_mask |= FLASH_OPTSR_BCM4;
  }
 
  if((UserType & OB_USER_BCM7) != 0U)
  {
    /* BCM7 option byte should be modified */
    assert_param(IS_OB_USER_BCM7(UserConfig & FLASH_OPTSR_BCM7));
 
    /* Set value and mask for BCM7 option byte */
    optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM7);
    optr_reg_mask |= FLASH_OPTSR_BCM7;
  }
#endif /* DUAL_CORE */
 
#if defined (FLASH_OPTSR_NRST_STOP_D2)
  if((UserType & OB_USER_NRST_STOP_D2) != 0U)
  {
    /* NRST_STOP option byte should be modified */
    assert_param(IS_OB_STOP_D2_RESET(UserConfig & FLASH_OPTSR_NRST_STOP_D2));
 
    /* Set value and mask for NRST_STOP option byte */
    optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STOP_D2);
    optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D2;
  }
 
  if((UserType & OB_USER_NRST_STDBY_D2) != 0U)
  {
    /* NRST_STDBY option byte should be modified */
    assert_param(IS_OB_STDBY_D2_RESET(UserConfig & FLASH_OPTSR_NRST_STBY_D2));
 
    /* Set value and mask for NRST_STDBY option byte */
    optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D2);
    optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D2;
  }
#endif /* FLASH_OPTSR_NRST_STOP_D2 */
 
#if defined (DUAL_BANK)
  if((UserType & OB_USER_SWAP_BANK) != 0U)
  {
    /* SWAP_BANK_OPT option byte should be modified */
    assert_param(IS_OB_USER_SWAP_BANK(UserConfig & FLASH_OPTSR_SWAP_BANK_OPT));
 
    /* Set value and mask for SWAP_BANK_OPT option byte */
    optr_reg_val |= (UserConfig & FLASH_OPTSR_SWAP_BANK_OPT);
    optr_reg_mask |= FLASH_OPTSR_SWAP_BANK_OPT;
  }
#endif /* DUAL_BANK */
 
  if((UserType & OB_USER_IOHSLV) != 0U)
  {
    /* IOHSLV_OPT option byte should be modified */
    assert_param(IS_OB_USER_IOHSLV(UserConfig & FLASH_OPTSR_IO_HSLV));
 
    /* Set value and mask for IOHSLV_OPT option byte */
    optr_reg_val |= (UserConfig & FLASH_OPTSR_IO_HSLV);
    optr_reg_mask |= FLASH_OPTSR_IO_HSLV;
  }
 
#if defined (FLASH_OPTSR_VDDMMC_HSLV)
  if((UserType & OB_USER_VDDMMC_HSLV) != 0U)
  {
    /* VDDMMC_HSLV option byte should be modified */
    assert_param(IS_OB_USER_VDDMMC_HSLV(UserConfig & FLASH_OPTSR_VDDMMC_HSLV));
 
    /* Set value and mask for VDDMMC_HSLV option byte */
    optr_reg_val |= (UserConfig & FLASH_OPTSR_VDDMMC_HSLV);
    optr_reg_mask |= FLASH_OPTSR_VDDMMC_HSLV;
  }
#endif /* FLASH_OPTSR_VDDMMC_HSLV */
 
  /* Configure the option bytes register */
  MODIFY_REG(FLASH->OPTSR_PRG, optr_reg_mask, optr_reg_val);
}
 
#if defined(DUAL_CORE)
 
#else
 
#endif /*DUAL_CORE*/
static uint32_t FLASH_OB_GetUser(void)
{
  uint32_t userConfig = READ_REG(FLASH->OPTSR_CUR);
  userConfig &= (~(FLASH_OPTSR_BOR_LEV | FLASH_OPTSR_RDP));
 
  return userConfig;
}
 
static void FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks)
{
  /* Check the parameters */
  assert_param(IS_FLASH_BANK(Banks));
  assert_param(IS_OB_PCROP_RDP(PCROPConfig));
 
  if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
  {
    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPStartAddr));
    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPEndAddr));
 
    /* Configure the Proprietary code readout protection */
    FLASH->PRAR_PRG1 = ((PCROPStartAddr - FLASH_BANK1_BASE) >> 8)                                 | \
                       (((PCROPEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | \
                       PCROPConfig;
  }
 
#if defined (DUAL_BANK)
  if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
  {
    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPStartAddr));
    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPEndAddr));
 
    /* Configure the Proprietary code readout protection */
    FLASH->PRAR_PRG2 = ((PCROPStartAddr - FLASH_BANK2_BASE) >> 8)                                 | \
                       (((PCROPEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | \
                       PCROPConfig;
  }
#endif /* DUAL_BANK */
}
 
static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr, uint32_t Bank)
{
  uint32_t regvalue = 0;
  uint32_t bankBase = 0;
 
  if(Bank == FLASH_BANK_1)
  {
    regvalue = FLASH->PRAR_CUR1;
    bankBase = FLASH_BANK1_BASE;
  }
 
#if defined (DUAL_BANK)
  if(Bank == FLASH_BANK_2)
  {
    regvalue = FLASH->PRAR_CUR2;
    bankBase = FLASH_BANK2_BASE;
  }
#endif /* DUAL_BANK */
 
  (*PCROPConfig) =  (regvalue & FLASH_PRAR_DMEP);
 
  (*PCROPStartAddr) = ((regvalue & FLASH_PRAR_PROT_AREA_START) << 8) + bankBase;
  (*PCROPEndAddr) = (regvalue & FLASH_PRAR_PROT_AREA_END) >> FLASH_PRAR_PROT_AREA_END_Pos;
  (*PCROPEndAddr) = ((*PCROPEndAddr) << 8) + bankBase;
}
 
static void FLASH_OB_BOR_LevelConfig(uint32_t Level)
{
  assert_param(IS_OB_BOR_LEVEL(Level));
 
  /* Configure BOR_LEV option byte */
  MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_BOR_LEV, Level);
}
 
static uint32_t FLASH_OB_GetBOR(void)
{
  return (FLASH->OPTSR_CUR & FLASH_OPTSR_BOR_LEV);
}
 
static void FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1)
{
  /* Check the parameters */
  assert_param(IS_OB_BOOT_ADD_OPTION(BootOption));
 
  if((BootOption & OB_BOOT_ADD0) == OB_BOOT_ADD0)
  {
    /* Check the parameters */
    assert_param(IS_BOOT_ADDRESS(BootAddress0));
 
    /* Configure CM7 BOOT ADD0 */
#if defined(DUAL_CORE)
    MODIFY_REG(FLASH->BOOT7_PRG, FLASH_BOOT7_BCM7_ADD0, (BootAddress0 >> 16));
#else /* Single Core*/
    MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD0, (BootAddress0 >> 16));
#endif /* DUAL_CORE */
  }
 
  if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1)
  {
    /* Check the parameters */
    assert_param(IS_BOOT_ADDRESS(BootAddress1));
 
    /* Configure CM7 BOOT ADD1 */
#if defined(DUAL_CORE)
    MODIFY_REG(FLASH->BOOT7_PRG, FLASH_BOOT7_BCM7_ADD1, BootAddress1);
#else /* Single Core*/
    MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD1, BootAddress1);
#endif /* DUAL_CORE */
  }
}
 
static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1)
{
  uint32_t regvalue;
 
#if defined(DUAL_CORE)
  regvalue = FLASH->BOOT7_CUR;
 
  (*BootAddress0) = (regvalue & FLASH_BOOT7_BCM7_ADD0) << 16;
  (*BootAddress1) = (regvalue & FLASH_BOOT7_BCM7_ADD1);
#else /* Single Core */
  regvalue = FLASH->BOOT_CUR;
 
  (*BootAddress0) = (regvalue & FLASH_BOOT_ADD0) << 16;
  (*BootAddress1) = (regvalue & FLASH_BOOT_ADD1);
#endif /* DUAL_CORE */
}
 
#if defined(DUAL_CORE)
 
static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1)
{
  /* Check the parameters */
  assert_param(IS_OB_BOOT_ADD_OPTION(BootOption));
 
  if((BootOption & OB_BOOT_ADD0) == OB_BOOT_ADD0)
  {
    /* Check the parameters */
    assert_param(IS_BOOT_ADDRESS(BootAddress0));
 
    /* Configure CM4 BOOT ADD0 */
    MODIFY_REG(FLASH->BOOT4_PRG, FLASH_BOOT4_BCM4_ADD0, (BootAddress0 >> 16));
 
  }
 
  if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1)
  {
    /* Check the parameters */
    assert_param(IS_BOOT_ADDRESS(BootAddress1));
 
    /* Configure CM4 BOOT ADD1 */
    MODIFY_REG(FLASH->BOOT4_PRG, FLASH_BOOT4_BCM4_ADD1, BootAddress1);
  }
}
 
static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1)
{
  uint32_t regvalue;
 
  regvalue = FLASH->BOOT4_CUR;
 
  (*BootAddress0) = (regvalue & FLASH_BOOT4_BCM4_ADD0) << 16;
  (*BootAddress1) = (regvalue & FLASH_BOOT4_BCM4_ADD1);
}
#endif /*DUAL_CORE*/
 
static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks)
{
  /* Check the parameters */
  assert_param(IS_FLASH_BANK(Banks));
  assert_param(IS_OB_SECURE_RDP(SecureAreaConfig));
 
  if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
  {
    /* Check the parameters */
    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaStartAddr));
    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaEndAddr));
 
    /* Configure the secure area */
    FLASH->SCAR_PRG1 = ((SecureAreaStartAddr - FLASH_BANK1_BASE) >> 8)                                | \
                       (((SecureAreaEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Pos) | \
                       (SecureAreaConfig & FLASH_SCAR_DMES);
  }
 
#if defined (DUAL_BANK)
  if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
  {
    /* Check the parameters */
    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaStartAddr));
    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaEndAddr));
 
    /* Configure the secure area */
    FLASH->SCAR_PRG2 = ((SecureAreaStartAddr - FLASH_BANK2_BASE) >> 8)                                | \
                       (((SecureAreaEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Pos) | \
                       (SecureAreaConfig & FLASH_SCAR_DMES);
  }
#endif /* DUAL_BANK */
}
 
static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank)
{
  uint32_t regvalue = 0;
  uint32_t bankBase = 0;
 
  /* Check Bank parameter value */
  if(Bank == FLASH_BANK_1)
  {
    regvalue = FLASH->SCAR_CUR1;
    bankBase = FLASH_BANK1_BASE;
  }
 
#if defined (DUAL_BANK)
  if(Bank == FLASH_BANK_2)
  {
    regvalue = FLASH->SCAR_CUR2;
    bankBase = FLASH_BANK2_BASE;
  }
#endif /* DUAL_BANK */
 
  /* Get the secure area settings */
  (*SecureAreaConfig) = (regvalue & FLASH_SCAR_DMES);
  (*SecureAreaStartAddr) = ((regvalue & FLASH_SCAR_SEC_AREA_START) << 8) + bankBase;
  (*SecureAreaEndAddr) = (regvalue & FLASH_SCAR_SEC_AREA_END) >> FLASH_SCAR_SEC_AREA_END_Pos;
  (*SecureAreaEndAddr) = ((*SecureAreaEndAddr) << 8) + bankBase;
}
 
static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank)
{
  /* Check the parameters */
  assert_param(IS_FLASH_SECTOR(Sector));
 
  if (Bank == FLASH_BANK_1)
  {
    /* Clear CRC sector */
    FLASH->CRCCR1 &= (~FLASH_CRCCR_CRC_SECT);
 
    /* Select CRC Sector and activate ADD_SECT bit */
    FLASH->CRCCR1 |= Sector | FLASH_CRCCR_ADD_SECT;
  }
#if defined (DUAL_BANK)
  else
  {
    /* Clear CRC sector */
    FLASH->CRCCR2 &= (~FLASH_CRCCR_CRC_SECT);
 
    /* Select CRC Sector and activate ADD_SECT bit */
    FLASH->CRCCR2 |= Sector | FLASH_CRCCR_ADD_SECT;
  }
#endif /* DUAL_BANK */
}
 
static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank)
{
  if (Bank == FLASH_BANK_1)
  {
    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(CRCStartAddr));
    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(CRCEndAddr));
 
    /* Write CRC Start and End addresses */
    FLASH->CRCSADD1 = CRCStartAddr;
    FLASH->CRCEADD1 = CRCEndAddr;
  }
#if defined (DUAL_BANK)
  else
  {
    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCStartAddr));
    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCEndAddr));
 
    /* Write CRC Start and End addresses */
    FLASH->CRCSADD2 = CRCStartAddr;
    FLASH->CRCEADD2 = CRCEndAddr;
  }
#endif /* DUAL_BANK */
}
#if defined (FLASH_OTPBL_LOCKBL)
 
static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block)
{
  /* Check the parameters */
  assert_param(IS_OTP_BLOCK(OTP_Block));
 
  /* Configure the OTP Block lock in the option bytes register */
  FLASH->OTPBL_PRG |= (OTP_Block & FLASH_OTPBL_LOCKBL);
}
 
static uint32_t FLASH_OB_OTP_GetLock(void)
{
  return (FLASH->OTPBL_CUR);
}
#endif /* FLASH_OTPBL_LOCKBL */
 
#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
 
static void FLASH_OB_SharedRAM_Config(uint32_t SharedRamConfig)
{
  /* Check the parameters */
  assert_param(IS_OB_USER_TCM_AXI_SHARED(SharedRamConfig));
 
  /* Configure the TCM / AXI Shared RAM in the option bytes register */
  MODIFY_REG(FLASH->OPTSR2_PRG, FLASH_OPTSR2_TCM_AXI_SHARED, SharedRamConfig);
}
 
static uint32_t FLASH_OB_SharedRAM_GetConfig(void)
{
  return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_TCM_AXI_SHARED);;
}
#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
 
#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
 
static void FLASH_OB_CPUFreq_BoostConfig(uint32_t FreqBoost)
{
  /* Check the parameters */
  assert_param(IS_OB_USER_CPUFREQ_BOOST(FreqBoost));
 
  /* Configure the CPU Frequency Boost in the option bytes register */
  MODIFY_REG(FLASH->OPTSR2_PRG, FLASH_OPTSR2_CPUFREQ_BOOST, FreqBoost);
}
 
static uint32_t FLASH_OB_CPUFreq_GetBoost(void)
{
  return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_CPUFREQ_BOOST);;
}
#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
 
#endif /* HAL_FLASH_MODULE_ENABLED */
 
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/