Files
file	fsl_clock.h

Classes
struct	_clock_arm_pll_config
	PLL configuration for ARM. More...

struct	_clock_audio_pll_config
	PLL configuration for AUDIO and VIDEO. More...

struct	_clock_enet_pll_config
	PLL configuration for ENET. More...

struct	_clock_sys_pll_config
	PLL configuration for System. More...

struct	_clock_usb_pll_config
	PLL configuration for USB. More...

struct	_clock_video_pll_config
	PLL configuration for AUDIO and VIDEO. More...

Variables
uint32_t	_clock_sys_pll_config::denominator

uint32_t	_clock_audio_pll_config::denominator

uint32_t	_clock_video_pll_config::denominator

bool	_clock_enet_pll_config::enableClkOutput

bool	_clock_enet_pll_config::enableClkOutput25M

uint32_t	_clock_arm_pll_config::loopDivider

uint8_t	_clock_usb_pll_config::loopDivider

uint8_t	_clock_sys_pll_config::loopDivider

uint8_t	_clock_audio_pll_config::loopDivider

uint8_t	_clock_video_pll_config::loopDivider

uint8_t	_clock_enet_pll_config::loopDivider

uint32_t	_clock_sys_pll_config::numerator

uint32_t	_clock_audio_pll_config::numerator

uint32_t	_clock_video_pll_config::numerator

uint8_t	_clock_audio_pll_config::postDivider

uint8_t	_clock_video_pll_config::postDivider

uint8_t	_clock_arm_pll_config::src

uint8_t	_clock_usb_pll_config::src

uint8_t	_clock_sys_pll_config::src

uint8_t	_clock_audio_pll_config::src

uint8_t	_clock_video_pll_config::src

uint8_t	_clock_enet_pll_config::src

uint8_t	_clock_sys_pll_config::ss_enable

uint16_t	_clock_sys_pll_config::ss_step

uint16_t	_clock_sys_pll_config::ss_stop

Driver version
Configure whether driver controls clock When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver. Note All drivers share this feature switcher. If it is set to 1, application should handle clock enable and disable for all drivers.
enum	_clock_name { kCLOCK_CpuClk = 0x0U, kCLOCK_AhbClk = 0x1U, kCLOCK_SemcClk = 0x2U, kCLOCK_IpgClk = 0x3U, kCLOCK_PerClk = 0x4U, kCLOCK_OscClk = 0x5U, kCLOCK_RtcClk = 0x6U, kCLOCK_ArmPllClk = 0x7U, kCLOCK_Usb1PllClk = 0x8U, kCLOCK_Usb1PllPfd0Clk = 0x9U, kCLOCK_Usb1PllPfd1Clk = 0xAU, kCLOCK_Usb1PllPfd2Clk = 0xBU, kCLOCK_Usb1PllPfd3Clk = 0xCU, kCLOCK_Usb2PllClk = 0xDU, kCLOCK_SysPllClk = 0xEU, kCLOCK_SysPllPfd0Clk = 0xFU, kCLOCK_SysPllPfd1Clk = 0x10U, kCLOCK_SysPllPfd2Clk = 0x11U, kCLOCK_SysPllPfd3Clk = 0x12U, kCLOCK_EnetPll0Clk = 0x13U, kCLOCK_EnetPll1Clk = 0x14U, kCLOCK_AudioPllClk = 0x15U, kCLOCK_VideoPllClk = 0x16U }
	Clock name used to get clock frequency. More...

enum	_clock_ip_name { kCLOCK_IpInvalid = -1, kCLOCK_Aips_tz1 = (0U << 8U) \| CCM_CCGR0_CG0_SHIFT, kCLOCK_Aips_tz2 = (0U << 8U) \| CCM_CCGR0_CG1_SHIFT, kCLOCK_Mqs = (0U << 8U) \| CCM_CCGR0_CG2_SHIFT, kCLOCK_FlexSpiExsc = (0U << 8U) \| CCM_CCGR0_CG3_SHIFT, kCLOCK_Sim_M_Main = (0U << 8U) \| CCM_CCGR0_CG4_SHIFT, kCLOCK_Dcp = (0U << 8U) \| CCM_CCGR0_CG5_SHIFT, kCLOCK_Lpuart3 = (0U << 8U) \| CCM_CCGR0_CG6_SHIFT, kCLOCK_Can1 = (0U << 8U) \| CCM_CCGR0_CG7_SHIFT, kCLOCK_Can1S = (0U << 8U) \| CCM_CCGR0_CG8_SHIFT, kCLOCK_Can2 = (0U << 8U) \| CCM_CCGR0_CG9_SHIFT, kCLOCK_Can2S = (0U << 8U) \| CCM_CCGR0_CG10_SHIFT, kCLOCK_Trace = (0U << 8U) \| CCM_CCGR0_CG11_SHIFT, kCLOCK_Gpt2 = (0U << 8U) \| CCM_CCGR0_CG12_SHIFT, kCLOCK_Gpt2S = (0U << 8U) \| CCM_CCGR0_CG13_SHIFT, kCLOCK_Lpuart2 = (0U << 8U) \| CCM_CCGR0_CG14_SHIFT, kCLOCK_Gpio2 = (0U << 8U) \| CCM_CCGR0_CG15_SHIFT, kCLOCK_Lpspi1 = (1U << 8U) \| CCM_CCGR1_CG0_SHIFT, kCLOCK_Lpspi2 = (1U << 8U) \| CCM_CCGR1_CG1_SHIFT, kCLOCK_Lpspi3 = (1U << 8U) \| CCM_CCGR1_CG2_SHIFT, kCLOCK_Lpspi4 = (1U << 8U) \| CCM_CCGR1_CG3_SHIFT, kCLOCK_Adc2 = (1U << 8U) \| CCM_CCGR1_CG4_SHIFT, kCLOCK_Enet = (1U << 8U) \| CCM_CCGR1_CG5_SHIFT, kCLOCK_Pit = (1U << 8U) \| CCM_CCGR1_CG6_SHIFT, kCLOCK_Aoi2 = (1U << 8U) \| CCM_CCGR1_CG7_SHIFT, kCLOCK_Adc1 = (1U << 8U) \| CCM_CCGR1_CG8_SHIFT, kCLOCK_SemcExsc = (1U << 8U) \| CCM_CCGR1_CG9_SHIFT, kCLOCK_Gpt1 = (1U << 8U) \| CCM_CCGR1_CG10_SHIFT, kCLOCK_Gpt1S = (1U << 8U) \| CCM_CCGR1_CG11_SHIFT, kCLOCK_Lpuart4 = (1U << 8U) \| CCM_CCGR1_CG12_SHIFT, kCLOCK_Gpio1 = (1U << 8U) \| CCM_CCGR1_CG13_SHIFT, kCLOCK_Csu = (1U << 8U) \| CCM_CCGR1_CG14_SHIFT, kCLOCK_Gpio5 = (1U << 8U) \| CCM_CCGR1_CG15_SHIFT, kCLOCK_OcramExsc = (2U << 8U) \| CCM_CCGR2_CG0_SHIFT, kCLOCK_Csi = (2U << 8U) \| CCM_CCGR2_CG1_SHIFT, kCLOCK_IomuxcSnvs = (2U << 8U) \| CCM_CCGR2_CG2_SHIFT, kCLOCK_Lpi2c1 = (2U << 8U) \| CCM_CCGR2_CG3_SHIFT, kCLOCK_Lpi2c2 = (2U << 8U) \| CCM_CCGR2_CG4_SHIFT, kCLOCK_Lpi2c3 = (2U << 8U) \| CCM_CCGR2_CG5_SHIFT, kCLOCK_Ocotp = (2U << 8U) \| CCM_CCGR2_CG6_SHIFT, kCLOCK_Xbar3 = (2U << 8U) \| CCM_CCGR2_CG7_SHIFT, kCLOCK_Ipmux1 = (2U << 8U) \| CCM_CCGR2_CG8_SHIFT, kCLOCK_Ipmux2 = (2U << 8U) \| CCM_CCGR2_CG9_SHIFT, kCLOCK_Ipmux3 = (2U << 8U) \| CCM_CCGR2_CG10_SHIFT, kCLOCK_Xbar1 = (2U << 8U) \| CCM_CCGR2_CG11_SHIFT, kCLOCK_Xbar2 = (2U << 8U) \| CCM_CCGR2_CG12_SHIFT, kCLOCK_Gpio3 = (2U << 8U) \| CCM_CCGR2_CG13_SHIFT, kCLOCK_Lcd = (2U << 8U) \| CCM_CCGR2_CG14_SHIFT, kCLOCK_Pxp = (2U << 8U) \| CCM_CCGR2_CG15_SHIFT, kCLOCK_Flexio2 = (3U << 8U) \| CCM_CCGR3_CG0_SHIFT, kCLOCK_Lpuart5 = (3U << 8U) \| CCM_CCGR3_CG1_SHIFT, kCLOCK_Semc = (3U << 8U) \| CCM_CCGR3_CG2_SHIFT, kCLOCK_Lpuart6 = (3U << 8U) \| CCM_CCGR3_CG3_SHIFT, kCLOCK_Aoi1 = (3U << 8U) \| CCM_CCGR3_CG4_SHIFT, kCLOCK_LcdPixel = (3U << 8U) \| CCM_CCGR3_CG5_SHIFT, kCLOCK_Gpio4 = (3U << 8U) \| CCM_CCGR3_CG6_SHIFT, kCLOCK_Ewm0 = (3U << 8U) \| CCM_CCGR3_CG7_SHIFT, kCLOCK_Wdog1 = (3U << 8U) \| CCM_CCGR3_CG8_SHIFT, kCLOCK_FlexRam = (3U << 8U) \| CCM_CCGR3_CG9_SHIFT, kCLOCK_Acmp1 = (3U << 8U) \| CCM_CCGR3_CG10_SHIFT, kCLOCK_Acmp2 = (3U << 8U) \| CCM_CCGR3_CG11_SHIFT, kCLOCK_Acmp3 = (3U << 8U) \| CCM_CCGR3_CG12_SHIFT, kCLOCK_Acmp4 = (3U << 8U) \| CCM_CCGR3_CG13_SHIFT, kCLOCK_Ocram = (3U << 8U) \| CCM_CCGR3_CG14_SHIFT, kCLOCK_IomuxcSnvsGpr = (3U << 8U) \| CCM_CCGR3_CG15_SHIFT, kCLOCK_Iomuxc = (4U << 8U) \| CCM_CCGR4_CG1_SHIFT, kCLOCK_IomuxcGpr = (4U << 8U) \| CCM_CCGR4_CG2_SHIFT, kCLOCK_Bee = (4U << 8U) \| CCM_CCGR4_CG3_SHIFT, kCLOCK_SimM7 = (4U << 8U) \| CCM_CCGR4_CG4_SHIFT, kCLOCK_Tsc = (4U << 8U) \| CCM_CCGR4_CG5_SHIFT, kCLOCK_SimM = (4U << 8U) \| CCM_CCGR4_CG6_SHIFT, kCLOCK_SimEms = (4U << 8U) \| CCM_CCGR4_CG7_SHIFT, kCLOCK_Pwm1 = (4U << 8U) \| CCM_CCGR4_CG8_SHIFT, kCLOCK_Pwm2 = (4U << 8U) \| CCM_CCGR4_CG9_SHIFT, kCLOCK_Pwm3 = (4U << 8U) \| CCM_CCGR4_CG10_SHIFT, kCLOCK_Pwm4 = (4U << 8U) \| CCM_CCGR4_CG11_SHIFT, kCLOCK_Enc1 = (4U << 8U) \| CCM_CCGR4_CG12_SHIFT, kCLOCK_Enc2 = (4U << 8U) \| CCM_CCGR4_CG13_SHIFT, kCLOCK_Enc3 = (4U << 8U) \| CCM_CCGR4_CG14_SHIFT, kCLOCK_Enc4 = (4U << 8U) \| CCM_CCGR4_CG15_SHIFT, kCLOCK_Rom = (5U << 8U) \| CCM_CCGR5_CG0_SHIFT, kCLOCK_Flexio1 = (5U << 8U) \| CCM_CCGR5_CG1_SHIFT, kCLOCK_Wdog3 = (5U << 8U) \| CCM_CCGR5_CG2_SHIFT, kCLOCK_Dma = (5U << 8U) \| CCM_CCGR5_CG3_SHIFT, kCLOCK_Kpp = (5U << 8U) \| CCM_CCGR5_CG4_SHIFT, kCLOCK_Wdog2 = (5U << 8U) \| CCM_CCGR5_CG5_SHIFT, kCLOCK_Aips_tz4 = (5U << 8U) \| CCM_CCGR5_CG6_SHIFT, kCLOCK_Spdif = (5U << 8U) \| CCM_CCGR5_CG7_SHIFT, kCLOCK_SimMain = (5U << 8U) \| CCM_CCGR5_CG8_SHIFT, kCLOCK_Sai1 = (5U << 8U) \| CCM_CCGR5_CG9_SHIFT, kCLOCK_Sai2 = (5U << 8U) \| CCM_CCGR5_CG10_SHIFT, kCLOCK_Sai3 = (5U << 8U) \| CCM_CCGR5_CG11_SHIFT, kCLOCK_Lpuart1 = (5U << 8U) \| CCM_CCGR5_CG12_SHIFT, kCLOCK_Lpuart7 = (5U << 8U) \| CCM_CCGR5_CG13_SHIFT, kCLOCK_SnvsHp = (5U << 8U) \| CCM_CCGR5_CG14_SHIFT, kCLOCK_SnvsLp = (5U << 8U) \| CCM_CCGR5_CG15_SHIFT, kCLOCK_UsbOh3 = (6U << 8U) \| CCM_CCGR6_CG0_SHIFT, kCLOCK_Usdhc1 = (6U << 8U) \| CCM_CCGR6_CG1_SHIFT, kCLOCK_Usdhc2 = (6U << 8U) \| CCM_CCGR6_CG2_SHIFT, kCLOCK_Dcdc = (6U << 8U) \| CCM_CCGR6_CG3_SHIFT, kCLOCK_Ipmux4 = (6U << 8U) \| CCM_CCGR6_CG4_SHIFT, kCLOCK_FlexSpi = (6U << 8U) \| CCM_CCGR6_CG5_SHIFT, kCLOCK_Trng = (6U << 8U) \| CCM_CCGR6_CG6_SHIFT, kCLOCK_Lpuart8 = (6U << 8U) \| CCM_CCGR6_CG7_SHIFT, kCLOCK_Timer4 = (6U << 8U) \| CCM_CCGR6_CG8_SHIFT, kCLOCK_Aips_tz3 = (6U << 8U) \| CCM_CCGR6_CG9_SHIFT, kCLOCK_SimPer = (6U << 8U) \| CCM_CCGR6_CG10_SHIFT, kCLOCK_Anadig = (6U << 8U) \| CCM_CCGR6_CG11_SHIFT, kCLOCK_Lpi2c4 = (6U << 8U) \| CCM_CCGR6_CG12_SHIFT, kCLOCK_Timer1 = (6U << 8U) \| CCM_CCGR6_CG13_SHIFT, kCLOCK_Timer2 = (6U << 8U) \| CCM_CCGR6_CG14_SHIFT, kCLOCK_Timer3 = (6U << 8U) \| CCM_CCGR6_CG15_SHIFT }
	CCM CCGR gate control for each module independently. More...

enum	_clock_osc { kCLOCK_RcOsc = 0U, kCLOCK_XtalOsc = 1U }
	OSC 24M sorce select. More...

enum	_clock_gate_value { kCLOCK_ClockNotNeeded = 0U, kCLOCK_ClockNeededRun = 1U, kCLOCK_ClockNeededRunWait = 3U }
	Clock gate value. More...

enum	_clock_mode_t { kCLOCK_ModeRun = 0U, kCLOCK_ModeWait = 1U, kCLOCK_ModeStop = 2U }
	System clock mode. More...

enum	_clock_mux { kCLOCK_Pll3SwMux, kCLOCK_PeriphMux, kCLOCK_SemcAltMux, kCLOCK_SemcMux, kCLOCK_PrePeriphMux, kCLOCK_TraceMux, kCLOCK_PeriphClk2Mux, kCLOCK_LpspiMux, kCLOCK_FlexspiMux, kCLOCK_Usdhc2Mux, kCLOCK_Usdhc1Mux, kCLOCK_Sai3Mux, kCLOCK_Sai2Mux, kCLOCK_Sai1Mux, kCLOCK_PerclkMux, kCLOCK_Flexio2Mux, kCLOCK_CanMux, kCLOCK_UartMux, kCLOCK_SpdifMux, kCLOCK_Flexio1Mux, kCLOCK_Lpi2cMux, kCLOCK_LcdifPreMux, kCLOCK_CsiMux }
	MUX control names for clock mux setting. More...

enum	_clock_div { kCLOCK_ArmDiv, kCLOCK_PeriphClk2Div, kCLOCK_SemcDiv, kCLOCK_AhbDiv, kCLOCK_IpgDiv, kCLOCK_LpspiDiv, kCLOCK_LcdifDiv, kCLOCK_FlexspiDiv, kCLOCK_PerclkDiv, kCLOCK_CanDiv, kCLOCK_TraceDiv, kCLOCK_Usdhc2Div, kCLOCK_Usdhc1Div, kCLOCK_UartDiv, kCLOCK_Flexio2Div, kCLOCK_Sai3PreDiv, kCLOCK_Sai3Div, kCLOCK_Flexio2PreDiv, kCLOCK_Sai1PreDiv, kCLOCK_Sai1Div, kCLOCK_Sai2PreDiv, kCLOCK_Sai2Div, kCLOCK_Spdif0PreDiv, kCLOCK_Spdif0Div, kCLOCK_Flexio1PreDiv, kCLOCK_Flexio1Div, kCLOCK_Lpi2cDiv, kCLOCK_LcdifPreDiv, kCLOCK_CsiDiv }
	DIV control names for clock div setting. More...

enum	_clock_usb_src { kCLOCK_Usb480M = 0, kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU }
	USB clock source definition. More...

enum	_clock_usb_phy_src { kCLOCK_Usbphy480M = 0 }
	Source of the USB HS PHY. More...

enum	_clock_pll_clk_src { kCLOCK_PllClkSrc24M = 0U, kCLOCK_PllSrcClkPN = 1U }
	PLL clock source, bypass cloco source also. More...

enum	_clock_pll { kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM_OFFSET, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT), kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO_OFFSET, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT), kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT), kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT), kCLOCK_PllUsb2 = CCM_ANALOG_TUPLE(PLL_USB2_OFFSET, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT) }
	PLL name. More...

enum	_clock_pfd { kCLOCK_Pfd0 = 0U, kCLOCK_Pfd1 = 1U, kCLOCK_Pfd2 = 2U, kCLOCK_Pfd3 = 3U }
	PLL PFD name. More...

typedef enum _clock_name	clock_name_t
	Clock name used to get clock frequency. More...

typedef enum _clock_ip_name	clock_ip_name_t
	CCM CCGR gate control for each module independently. More...

typedef enum _clock_osc	clock_osc_t
	OSC 24M sorce select. More...

typedef enum _clock_gate_value	clock_gate_value_t
	Clock gate value. More...

typedef enum _clock_mode_t	clock_mode_t
	System clock mode. More...

typedef enum _clock_mux	clock_mux_t
	MUX control names for clock mux setting. More...

typedef enum _clock_div	clock_div_t
	DIV control names for clock div setting. More...

typedef enum _clock_usb_src	clock_usb_src_t
	USB clock source definition. More...

typedef enum _clock_usb_phy_src	clock_usb_phy_src_t
	Source of the USB HS PHY. More...

typedef struct _clock_arm_pll_config	clock_arm_pll_config_t
	PLL configuration for ARM. More...

typedef struct _clock_usb_pll_config	clock_usb_pll_config_t
	PLL configuration for USB. More...

typedef struct _clock_sys_pll_config	clock_sys_pll_config_t
	PLL configuration for System. More...

typedef struct _clock_audio_pll_config	clock_audio_pll_config_t
	PLL configuration for AUDIO and VIDEO. More...

typedef struct _clock_video_pll_config	clock_video_pll_config_t
	PLL configuration for AUDIO and VIDEO. More...

typedef struct _clock_enet_pll_config	clock_enet_pll_config_t
	PLL configuration for ENET. More...

typedef enum _clock_pll	clock_pll_t
	PLL name. More...

typedef enum _clock_pfd	clock_pfd_t
	PLL PFD name. More...

volatile uint32_t	g_xtalFreq
	External XTAL (24M OSC/SYSOSC) clock frequency. More...

volatile uint32_t	g_rtcXtalFreq
	External RTC XTAL (32K OSC) clock frequency. More...

static void	CLOCK_SetMux (clock_mux_t mux, uint32_t value)
	Set CCM MUX node to certain value. More...

static uint32_t	CLOCK_GetMux (clock_mux_t mux)
	Get CCM MUX value. More...

static void	CLOCK_SetDiv (clock_div_t divider, uint32_t value)
	Set CCM DIV node to certain value. More...

static uint32_t	CLOCK_GetDiv (clock_div_t divider)
	Get CCM DIV node value. More...

static void	CLOCK_ControlGate (clock_ip_name_t name, clock_gate_value_t value)
	Control the clock gate for specific IP. More...

static void	CLOCK_EnableClock (clock_ip_name_t name)
	Enable the clock for specific IP. More...

static void	CLOCK_DisableClock (clock_ip_name_t name)
	Disable the clock for specific IP. More...

static void	CLOCK_SetMode (clock_mode_t mode)
	Setting the low power mode that system will enter on next assertion of dsm_request signal. More...

static uint32_t	CLOCK_GetOscFreq (void)
	Gets the OSC clock frequency. More...

uint32_t	CLOCK_GetAhbFreq (void)
	Gets the AHB clock frequency. More...

uint32_t	CLOCK_GetSemcFreq (void)
	Gets the SEMC clock frequency. More...

uint32_t	CLOCK_GetIpgFreq (void)
	Gets the IPG clock frequency. More...

uint32_t	CLOCK_GetPerClkFreq (void)
	Gets the PER clock frequency. More...

uint32_t	CLOCK_GetFreq (clock_name_t name)
	Gets the clock frequency for a specific clock name. More...

static uint32_t	CLOCK_GetCpuClkFreq (void)
	Get the CCM CPU/core/system frequency. More...

#define	FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 2))
	CLOCK driver version 2.3.2. More...

#define	CCM_ANALOG_PLL_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCSR_OFFSET 0x0C
	CCM registers offset. More...

#define	CBCDR_OFFSET 0x14

#define	CBCMR_OFFSET 0x18

#define	CSCMR1_OFFSET 0x1C

#define	CSCMR2_OFFSET 0x20

#define	CSCDR1_OFFSET 0x24

#define	CDCDR_OFFSET 0x30

#define	CSCDR2_OFFSET 0x38

#define	CSCDR3_OFFSET 0x3C

#define	CACRR_OFFSET 0x10

#define	CS1CDR_OFFSET 0x28

#define	CS2CDR_OFFSET 0x2C

#define	PLL_ARM_OFFSET 0x00
	CCM Analog registers offset. More...

#define	PLL_SYS_OFFSET 0x30

#define	PLL_USB1_OFFSET 0x10

#define	PLL_AUDIO_OFFSET 0x70

#define	PLL_VIDEO_OFFSET 0xA0

#define	PLL_ENET_OFFSET 0xE0

#define	PLL_USB2_OFFSET 0x20

#define	CCM_TUPLE(reg, shift, mask, busyShift) (int)(((reg)&0xFFU) \| ((shift) << 8U) \| ((((mask) >> (shift)) & 0x1FFFU) << 13U) \| ((busyShift) << 26U))

#define	CCM_TUPLE_REG(base, tuple) (((volatile uint32_t )(((uint32_t)(base)) + ((uint32_t)(tuple)&0xFFU))))

#define	CCM_TUPLE_SHIFT(tuple) ((((uint32_t)tuple) >> 8U) & 0x1FU)

#define	CCM_TUPLE_MASK(tuple) ((uint32_t)((((uint32_t)(tuple) >> 13U) & 0x1FFFU) << (((((uint32_t)tuple) >> 8U) & 0x1FU))))

#define	CCM_TUPLE_BUSY_SHIFT(tuple) ((((uint32_t)tuple) >> 26U) & 0x3FU)

#define	CCM_NO_BUSY_WAIT (0x20U)

#define	CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFU) << 16U) \| (shift))
	CCM ANALOG tuple macros to map corresponding registers and bit fields. More...

#define	CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU)

#define	CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) (((volatile uint32_t )((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFU) + (off))))

#define	CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)

#define	CLKPN_FREQ 0U
	clock1PN frequency. More...

#define	CLOCK_SetXtal0Freq CLOCK_SetXtalFreq

#define	CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq

#define	ADC_CLOCKS
	Clock ip name array for ADC. More...

#define	AOI_CLOCKS
	Clock ip name array for AOI. More...

#define	BEE_CLOCKS
	Clock ip name array for BEE. More...

#define	CMP_CLOCKS
	Clock ip name array for CMP. More...

#define	CSI_CLOCKS
	Clock ip name array for CSI. More...

#define	DCDC_CLOCKS
	Clock ip name array for DCDC. More...

#define	DCP_CLOCKS
	Clock ip name array for DCP. More...

#define	DMAMUX_CLOCKS
	Clock ip name array for DMAMUX_CLOCKS. More...

#define	EDMA_CLOCKS
	Clock ip name array for DMA. More...

#define	ENC_CLOCKS
	Clock ip name array for ENC. More...

#define	ENET_CLOCKS
	Clock ip name array for ENET. More...

#define	EWM_CLOCKS
	Clock ip name array for EWM. More...

#define	FLEXCAN_CLOCKS
	Clock ip name array for FLEXCAN. More...

#define	FLEXCAN_PERIPH_CLOCKS
	Clock ip name array for FLEXCAN Peripheral clock. More...

#define	FLEXIO_CLOCKS
	Clock ip name array for FLEXIO. More...

#define	FLEXRAM_CLOCKS
	Clock ip name array for FLEXRAM. More...

#define	FLEXSPI_CLOCKS
	Clock ip name array for FLEXSPI. More...

#define	FLEXSPI_EXSC_CLOCKS
	Clock ip name array for FLEXSPI EXSC. More...

#define	GPIO_CLOCKS
	Clock ip name array for GPIO. More...

#define	GPT_CLOCKS
	Clock ip name array for GPT. More...

#define	KPP_CLOCKS
	Clock ip name array for KPP. More...

#define	LCDIF_CLOCKS
	Clock ip name array for LCDIF. More...

#define	LCDIF_PERIPH_CLOCKS
	Clock ip name array for LCDIF PIXEL. More...

#define	LPI2C_CLOCKS
	Clock ip name array for LPI2C. More...

#define	LPSPI_CLOCKS
	Clock ip name array for LPSPI. More...

#define	LPUART_CLOCKS
	Clock ip name array for LPUART. More...

#define	MQS_CLOCKS
	Clock ip name array for MQS. More...

#define	OCRAM_EXSC_CLOCKS
	Clock ip name array for OCRAM EXSC. More...

#define	PIT_CLOCKS
	Clock ip name array for PIT. More...

#define	PWM_CLOCKS
	Clock ip name array for PWM. More...

#define	PXP_CLOCKS
	Clock ip name array for PXP. More...

#define	RTWDOG_CLOCKS
	Clock ip name array for RTWDOG. More...

#define	SAI_CLOCKS
	Clock ip name array for SAI. More...

#define	SEMC_CLOCKS
	Clock ip name array for SEMC. More...

#define	SEMC_EXSC_CLOCKS
	Clock ip name array for SEMC EXSC. More...

#define	TMR_CLOCKS
	Clock ip name array for QTIMER. More...

#define	TRNG_CLOCKS
	Clock ip name array for TRNG. More...

#define	TSC_CLOCKS
	Clock ip name array for TSC. More...

#define	WDOG_CLOCKS
	Clock ip name array for WDOG. More...

#define	USDHC_CLOCKS
	Clock ip name array for USDHC. More...

#define	SPDIF_CLOCKS
	Clock ip name array for SPDIF. More...

#define	XBARA_CLOCKS
	Clock ip name array for XBARA. More...

#define	XBARB_CLOCKS
	Clock ip name array for XBARB. More...

#define	kCLOCK_CoreSysClk kCLOCK_CpuClk

#define	CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq

OSC operations
void	CLOCK_InitExternalClk (bool bypassXtalOsc)
	Initialize the external 24MHz clock. More...

void	CLOCK_DeinitExternalClk (void)
	Deinitialize the external 24MHz clock. More...

void	CLOCK_SwitchOsc (clock_osc_t osc)
	Switch the OSC. More...

static uint32_t	CLOCK_GetRtcFreq (void)
	Gets the RTC clock frequency. More...

static void	CLOCK_SetXtalFreq (uint32_t freq)
	Set the XTAL (24M OSC) frequency based on board setting. More...

static void	CLOCK_SetRtcXtalFreq (uint32_t freq)
	Set the RTC XTAL (32K OSC) frequency based on board setting. More...

void	CLOCK_InitRcOsc24M (void)
	Initialize the RC oscillator 24MHz clock. More...

void	CLOCK_DeinitRcOsc24M (void)
	Power down the RCOSC 24M clock. More...

bool	CLOCK_EnableUsbhs0Clock (clock_usb_src_t src, uint32_t freq)
	Enable USB HS clock. More...

bool	CLOCK_EnableUsbhs1Clock (clock_usb_src_t src, uint32_t freq)
	Enable USB HS clock. More...

PLL/PFD operations
static void	CLOCK_SetPllBypass (CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass)
	PLL bypass setting. More...

static bool	CLOCK_IsPllBypassed (CCM_ANALOG_Type *base, clock_pll_t pll)
	Check if PLL is bypassed. More...

static bool	CLOCK_IsPllEnabled (CCM_ANALOG_Type *base, clock_pll_t pll)
	Check if PLL is enabled. More...

static void	CLOCK_SetPllBypassRefClkSrc (CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src)
	PLL bypass clock source setting. Note: change the bypass clock source also change the pll reference clock source. More...

static uint32_t	CLOCK_GetPllBypassRefClk (CCM_ANALOG_Type *base, clock_pll_t pll)
	Get PLL bypass clock value, it is PLL reference clock actually. If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 will be returned. More...

void	CLOCK_InitArmPll (const clock_arm_pll_config_t *config)
	Initialize the ARM PLL. More...

void	CLOCK_DeinitArmPll (void)
	De-initialize the ARM PLL. More...

void	CLOCK_InitSysPll (const clock_sys_pll_config_t *config)
	Initialize the System PLL. More...

void	CLOCK_DeinitSysPll (void)
	De-initialize the System PLL. More...

void	CLOCK_InitUsb1Pll (const clock_usb_pll_config_t *config)
	Initialize the USB1 PLL. More...

void	CLOCK_DeinitUsb1Pll (void)
	Deinitialize the USB1 PLL. More...

void	CLOCK_InitUsb2Pll (const clock_usb_pll_config_t *config)
	Initialize the USB2 PLL. More...

void	CLOCK_DeinitUsb2Pll (void)
	Deinitialize the USB2 PLL. More...

void	CLOCK_InitAudioPll (const clock_audio_pll_config_t *config)
	Initializes the Audio PLL. More...

void	CLOCK_DeinitAudioPll (void)
	De-initialize the Audio PLL. More...

void	CLOCK_InitVideoPll (const clock_video_pll_config_t *config)
	Initialize the video PLL. More...

void	CLOCK_DeinitVideoPll (void)
	De-initialize the Video PLL. More...

void	CLOCK_InitEnetPll (const clock_enet_pll_config_t *config)
	Initialize the ENET PLL. More...

void	CLOCK_DeinitEnetPll (void)
	Deinitialize the ENET PLL. More...

uint32_t	CLOCK_GetPllFreq (clock_pll_t pll)
	Get current PLL output frequency. More...

void	CLOCK_InitSysPfd (clock_pfd_t pfd, uint8_t pfdFrac)
	Initialize the System PLL PFD. More...

void	CLOCK_DeinitSysPfd (clock_pfd_t pfd)
	De-initialize the System PLL PFD. More...

void	CLOCK_InitUsb1Pfd (clock_pfd_t pfd, uint8_t pfdFrac)
	Initialize the USB1 PLL PFD. More...

void	CLOCK_DeinitUsb1Pfd (clock_pfd_t pfd)
	De-initialize the USB1 PLL PFD. More...

uint32_t	CLOCK_GetSysPfdFreq (clock_pfd_t pfd)
	Get current System PLL PFD output frequency. More...

uint32_t	CLOCK_GetUsb1PfdFreq (clock_pfd_t pfd)
	Get current USB1 PLL PFD output frequency. More...

bool	CLOCK_EnableUsbhs0PhyPllClock (clock_usb_phy_src_t src, uint32_t freq)
	Enable USB HS PHY PLL clock. More...

void	CLOCK_DisableUsbhs0PhyPllClock (void)
	Disable USB HS PHY PLL clock. More...

bool	CLOCK_EnableUsbhs1PhyPllClock (clock_usb_phy_src_t src, uint32_t freq)
	Enable USB HS PHY PLL clock. More...

void	CLOCK_DisableUsbhs1PhyPllClock (void)
	Disable USB HS PHY PLL clock. More...

Detailed Description

Macro Definition Documentation

◆ ADC_CLOCKS

#define ADC_CLOCKS

Value:

    {                                              \
        kCLOCK_IpInvalid, kCLOCK_Adc1, kCLOCK_Adc2 \
    }

Clock ip name array for ADC.

Definition at line 139 of file fsl_clock.h.

◆ AOI_CLOCKS

#define AOI_CLOCKS

Value:

    {                                              \
        kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \
    }

Clock ip name array for AOI.

Definition at line 145 of file fsl_clock.h.

◆ BEE_CLOCKS

#define BEE_CLOCKS

Value:

    {              \
        kCLOCK_Bee \
    }

Clock ip name array for BEE.

Definition at line 151 of file fsl_clock.h.

◆ CACRR_OFFSET

#define CACRR_OFFSET 0x10

Definition at line 69 of file fsl_clock.h.

◆ CBCDR_OFFSET

#define CBCDR_OFFSET 0x14

Definition at line 61 of file fsl_clock.h.

◆ CBCMR_OFFSET

#define CBCMR_OFFSET 0x18

Definition at line 62 of file fsl_clock.h.

◆ CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK

#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)

Definition at line 52 of file fsl_clock.h.

◆ CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT

#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)

Definition at line 53 of file fsl_clock.h.

◆ CCM_ANALOG_PLL_BYPASS_SHIFT

#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)

Definition at line 51 of file fsl_clock.h.

◆ CCM_ANALOG_TUPLE

#define CCM_ANALOG_TUPLE	(	reg,
		shift
	)	((((reg)&0xFFFU) << 16U) \| (shift))

CCM ANALOG tuple macros to map corresponding registers and bit fields.

Definition at line 97 of file fsl_clock.h.

◆ CCM_ANALOG_TUPLE_REG

#define CCM_ANALOG_TUPLE_REG	(	base,
		tuple
	)	CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)

Definition at line 101 of file fsl_clock.h.

◆ CCM_ANALOG_TUPLE_REG_OFF

#define CCM_ANALOG_TUPLE_REG_OFF	(	base,
		tuple,
		off
	)	(((volatile uint32_t )((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFU) + (off))))

Definition at line 99 of file fsl_clock.h.

◆ CCM_ANALOG_TUPLE_SHIFT

#define CCM_ANALOG_TUPLE_SHIFT ( tuple ) (((uint32_t)tuple) & 0x1FU)

Definition at line 98 of file fsl_clock.h.

◆ CCM_NO_BUSY_WAIT

#define CCM_NO_BUSY_WAIT (0x20U)

Definition at line 92 of file fsl_clock.h.

◆ CCM_TUPLE

#define CCM_TUPLE	(	reg,
		shift,
		mask,
		busyShift
	)	(int)(((reg)&0xFFU) \| ((shift) << 8U) \| ((((mask) >> (shift)) & 0x1FFFU) << 13U) \| ((busyShift) << 26U))

Definition at line 84 of file fsl_clock.h.

◆ CCM_TUPLE_BUSY_SHIFT

#define CCM_TUPLE_BUSY_SHIFT ( tuple ) ((((uint32_t)tuple) >> 26U) & 0x3FU)

Definition at line 90 of file fsl_clock.h.

◆ CCM_TUPLE_MASK

#define CCM_TUPLE_MASK ( tuple ) ((uint32_t)((((uint32_t)(tuple) >> 13U) & 0x1FFFU) << (((((uint32_t)tuple) >> 8U) & 0x1FU))))

Definition at line 88 of file fsl_clock.h.

◆ CCM_TUPLE_REG

#define CCM_TUPLE_REG	(	base,
		tuple
	)	(((volatile uint32_t )(((uint32_t)(base)) + ((uint32_t)(tuple)&0xFFU))))

Definition at line 86 of file fsl_clock.h.

◆ CCM_TUPLE_SHIFT

#define CCM_TUPLE_SHIFT ( tuple ) ((((uint32_t)tuple) >> 8U) & 0x1FU)

Definition at line 87 of file fsl_clock.h.

◆ CCSR_OFFSET

#define CCSR_OFFSET 0x0C

CCM registers offset.

Definition at line 60 of file fsl_clock.h.

◆ CDCDR_OFFSET

#define CDCDR_OFFSET 0x30

Definition at line 66 of file fsl_clock.h.

◆ CLKPN_FREQ

#define CLKPN_FREQ 0U

clock1PN frequency.

Definition at line 113 of file fsl_clock.h.

◆ CLOCK_GetCoreSysClkFreq

#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq

For compatible with other platforms without CCM.

Definition at line 439 of file fsl_clock.h.

◆ CLOCK_SetXtal0Freq

#define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq

Definition at line 135 of file fsl_clock.h.

◆ CLOCK_SetXtal32Freq

#define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq

Definition at line 136 of file fsl_clock.h.

◆ CMP_CLOCKS

#define CMP_CLOCKS

Value:

    {                                                                            \
        kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \
    }

Clock ip name array for CMP.

Definition at line 157 of file fsl_clock.h.

◆ CS1CDR_OFFSET

#define CS1CDR_OFFSET 0x28

Definition at line 70 of file fsl_clock.h.

◆ CS2CDR_OFFSET

#define CS2CDR_OFFSET 0x2C

Definition at line 71 of file fsl_clock.h.

◆ CSCDR1_OFFSET

#define CSCDR1_OFFSET 0x24

Definition at line 65 of file fsl_clock.h.

◆ CSCDR2_OFFSET

#define CSCDR2_OFFSET 0x38

Definition at line 67 of file fsl_clock.h.

◆ CSCDR3_OFFSET

#define CSCDR3_OFFSET 0x3C

Definition at line 68 of file fsl_clock.h.

◆ CSCMR1_OFFSET

#define CSCMR1_OFFSET 0x1C

Definition at line 63 of file fsl_clock.h.

◆ CSCMR2_OFFSET

#define CSCMR2_OFFSET 0x20

Definition at line 64 of file fsl_clock.h.

◆ CSI_CLOCKS

#define CSI_CLOCKS

Value:

    {              \
        kCLOCK_Csi \
    }

Clock ip name array for CSI.

Definition at line 163 of file fsl_clock.h.

◆ DCDC_CLOCKS

#define DCDC_CLOCKS

Value:

    {               \
        kCLOCK_Dcdc \
    }

Clock ip name array for DCDC.

Definition at line 169 of file fsl_clock.h.

◆ DCP_CLOCKS

#define DCP_CLOCKS

Value:

    {              \
        kCLOCK_Dcp \
    }

Clock ip name array for DCP.

Definition at line 175 of file fsl_clock.h.

◆ DMAMUX_CLOCKS

#define DMAMUX_CLOCKS

Value:

    {                 \
        kCLOCK_Dma    \
    }

Clock ip name array for DMAMUX_CLOCKS.

Definition at line 181 of file fsl_clock.h.

◆ EDMA_CLOCKS

#define EDMA_CLOCKS

Value:

    {               \
        kCLOCK_Dma  \
    }

Clock ip name array for DMA.

Definition at line 187 of file fsl_clock.h.

◆ ENC_CLOCKS

#define ENC_CLOCKS

Value:

    {                                                                        \
        kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \
    }

Clock ip name array for ENC.

Definition at line 193 of file fsl_clock.h.

◆ ENET_CLOCKS

#define ENET_CLOCKS

Value:

    {               \
        kCLOCK_Enet \
    }

Clock ip name array for ENET.

Definition at line 199 of file fsl_clock.h.

◆ EWM_CLOCKS

#define EWM_CLOCKS

Value:

    {               \
        kCLOCK_Ewm0 \
    }

Clock ip name array for EWM.

Definition at line 205 of file fsl_clock.h.

◆ FLEXCAN_CLOCKS

#define FLEXCAN_CLOCKS

Value:

    {                                              \
        kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 \
    }

Clock ip name array for FLEXCAN.

Definition at line 211 of file fsl_clock.h.

◆ FLEXCAN_PERIPH_CLOCKS

#define FLEXCAN_PERIPH_CLOCKS

Value:

    {                                                \
        kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S \
    }

Clock ip name array for FLEXCAN Peripheral clock.

Definition at line 217 of file fsl_clock.h.

◆ FLEXIO_CLOCKS

#define FLEXIO_CLOCKS

Value:

    {                                                    \
        kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \
    }

Clock ip name array for FLEXIO.

Definition at line 223 of file fsl_clock.h.

◆ FLEXRAM_CLOCKS

#define FLEXRAM_CLOCKS

Value:

    {                  \
        kCLOCK_FlexRam \
    }

Clock ip name array for FLEXRAM.

Definition at line 229 of file fsl_clock.h.

◆ FLEXSPI_CLOCKS

#define FLEXSPI_CLOCKS

Value:

    {                  \
        kCLOCK_FlexSpi \
    }

Clock ip name array for FLEXSPI.

Definition at line 235 of file fsl_clock.h.

◆ FLEXSPI_EXSC_CLOCKS

#define FLEXSPI_EXSC_CLOCKS

Value:

    {                       \
        kCLOCK_FlexSpiExsc  \
    }

Clock ip name array for FLEXSPI EXSC.

Definition at line 241 of file fsl_clock.h.

◆ FSL_CLOCK_DRIVER_VERSION

#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 2))

CLOCK driver version 2.3.2.

Definition at line 43 of file fsl_clock.h.

◆ GPIO_CLOCKS

#define GPIO_CLOCKS

Value:

    {                                                                                          \
        kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \
    }

Clock ip name array for GPIO.

Definition at line 247 of file fsl_clock.h.

◆ GPT_CLOCKS

#define GPT_CLOCKS

Value:

    {                                              \
        kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \
    }

Clock ip name array for GPT.

Definition at line 253 of file fsl_clock.h.

◆ kCLOCK_CoreSysClk

#define kCLOCK_CoreSysClk kCLOCK_CpuClk

For compatible with other platforms without CCM.

Definition at line 438 of file fsl_clock.h.

◆ KPP_CLOCKS

#define KPP_CLOCKS

Value:

    {              \
        kCLOCK_Kpp \
    }

Clock ip name array for KPP.

Definition at line 259 of file fsl_clock.h.

◆ LCDIF_CLOCKS

#define LCDIF_CLOCKS

Value:

    {                \
        kCLOCK_Lcd   \
    }

Clock ip name array for LCDIF.

Definition at line 265 of file fsl_clock.h.

◆ LCDIF_PERIPH_CLOCKS

#define LCDIF_PERIPH_CLOCKS

Value:

    {                       \
        kCLOCK_LcdPixel     \
    }

Clock ip name array for LCDIF PIXEL.

Definition at line 271 of file fsl_clock.h.

◆ LPI2C_CLOCKS

#define LPI2C_CLOCKS

Value:

    {                                                                                \
        kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 \
    }

Clock ip name array for LPI2C.

Definition at line 277 of file fsl_clock.h.

◆ LPSPI_CLOCKS

#define LPSPI_CLOCKS

Value:

    {                                                                                \
        kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 \
    }

Clock ip name array for LPSPI.

Definition at line 283 of file fsl_clock.h.

◆ LPUART_CLOCKS

#define LPUART_CLOCKS

Value:

    {                                                                                                     \
        kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \
            kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8                                                \
    }

Clock ip name array for LPUART.

Definition at line 289 of file fsl_clock.h.

◆ MQS_CLOCKS

#define MQS_CLOCKS

Value:

    {              \
        kCLOCK_Mqs \
    }

Clock ip name array for MQS.

Definition at line 296 of file fsl_clock.h.

◆ OCRAM_EXSC_CLOCKS

#define OCRAM_EXSC_CLOCKS

Value:

    {                     \
        kCLOCK_OcramExsc  \
    }

Clock ip name array for OCRAM EXSC.

Definition at line 302 of file fsl_clock.h.

◆ PIT_CLOCKS

#define PIT_CLOCKS

Value:

    {              \
        kCLOCK_Pit \
    }

Clock ip name array for PIT.

Definition at line 308 of file fsl_clock.h.

◆ PLL_ARM_OFFSET

#define PLL_ARM_OFFSET 0x00

CCM Analog registers offset.

Definition at line 76 of file fsl_clock.h.

◆ PLL_AUDIO_OFFSET

#define PLL_AUDIO_OFFSET 0x70

Definition at line 79 of file fsl_clock.h.

◆ PLL_ENET_OFFSET

#define PLL_ENET_OFFSET 0xE0

Definition at line 81 of file fsl_clock.h.

◆ PLL_SYS_OFFSET

#define PLL_SYS_OFFSET 0x30

Definition at line 77 of file fsl_clock.h.

◆ PLL_USB1_OFFSET

#define PLL_USB1_OFFSET 0x10

Definition at line 78 of file fsl_clock.h.

◆ PLL_USB2_OFFSET

#define PLL_USB2_OFFSET 0x20

Definition at line 82 of file fsl_clock.h.

◆ PLL_VIDEO_OFFSET

#define PLL_VIDEO_OFFSET 0xA0

Definition at line 80 of file fsl_clock.h.

◆ PWM_CLOCKS

#define PWM_CLOCKS

Value:

    {                                                                             \
        {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \
            {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1},                 \
            {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2},                 \
            {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3},                 \
        {                                                                         \
            kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4                    \
        }                                                                         \
    }

Clock ip name array for PWM.

Definition at line 314 of file fsl_clock.h.

◆ PXP_CLOCKS

#define PXP_CLOCKS

Value:

    {              \
        kCLOCK_Pxp \
    }

Clock ip name array for PXP.

Definition at line 326 of file fsl_clock.h.

◆ RTWDOG_CLOCKS

#define RTWDOG_CLOCKS

Value:

    {                 \
        kCLOCK_Wdog3  \
    }

Clock ip name array for RTWDOG.

Definition at line 332 of file fsl_clock.h.

◆ SAI_CLOCKS

#define SAI_CLOCKS

Value:

    {                                                           \
        kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \
    }

Clock ip name array for SAI.

Definition at line 338 of file fsl_clock.h.

◆ SEMC_CLOCKS

#define SEMC_CLOCKS

Value:

    {               \
        kCLOCK_Semc \
    }

Clock ip name array for SEMC.

Definition at line 344 of file fsl_clock.h.

◆ SEMC_EXSC_CLOCKS

#define SEMC_EXSC_CLOCKS

Value:

    {                    \
        kCLOCK_SemcExsc  \
    }

Clock ip name array for SEMC EXSC.

Definition at line 350 of file fsl_clock.h.

◆ SPDIF_CLOCKS

#define SPDIF_CLOCKS

Value:

    {                \
        kCLOCK_Spdif \
    }

Clock ip name array for SPDIF.

Definition at line 386 of file fsl_clock.h.

◆ TMR_CLOCKS

#define TMR_CLOCKS

Value:

    {                                                                                \
        kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \
    }

Clock ip name array for QTIMER.

Definition at line 356 of file fsl_clock.h.

◆ TRNG_CLOCKS

#define TRNG_CLOCKS

Value:

    {               \
        kCLOCK_Trng \
    }

Clock ip name array for TRNG.

Definition at line 362 of file fsl_clock.h.

◆ TSC_CLOCKS

#define TSC_CLOCKS

Value:

    {              \
        kCLOCK_Tsc \
    }

Clock ip name array for TSC.

Definition at line 368 of file fsl_clock.h.

◆ USDHC_CLOCKS

#define USDHC_CLOCKS

Value:

    {                                                  \
        kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \
    }

Clock ip name array for USDHC.

Definition at line 380 of file fsl_clock.h.

◆ WDOG_CLOCKS

#define WDOG_CLOCKS

Value:

    {                                                \
        kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \
    }

Clock ip name array for WDOG.

Definition at line 374 of file fsl_clock.h.

◆ XBARA_CLOCKS

#define XBARA_CLOCKS

Value:

    {                \
        kCLOCK_Xbar1 \
    }

Clock ip name array for XBARA.

Definition at line 392 of file fsl_clock.h.

◆ XBARB_CLOCKS

#define XBARB_CLOCKS

Value:

    {                                                                  \
        kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \
    }

Clock ip name array for XBARB.

Definition at line 398 of file fsl_clock.h.

Typedef Documentation

◆ clock_arm_pll_config_t

typedef struct _clock_arm_pll_config clock_arm_pll_config_t

PLL configuration for ARM.

◆ clock_audio_pll_config_t

typedef struct _clock_audio_pll_config clock_audio_pll_config_t

PLL configuration for AUDIO and VIDEO.

◆ clock_div_t

typedef enum _clock_div clock_div_t

DIV control names for clock div setting.

These constants define div control names for clock div setting.

0:7: REG offset to CCM_BASE in bytes.
8:15: Root clock setting bit field shift.
16:31: Root clock setting bit field width.

◆ clock_enet_pll_config_t

typedef struct _clock_enet_pll_config clock_enet_pll_config_t

PLL configuration for ENET.

◆ clock_gate_value_t

typedef enum _clock_gate_value clock_gate_value_t

Clock gate value.

◆ clock_ip_name_t

typedef enum _clock_ip_name clock_ip_name_t

CCM CCGR gate control for each module independently.

◆ clock_mode_t

typedef enum _clock_mode_t clock_mode_t

System clock mode.

◆ clock_mux_t

typedef enum _clock_mux clock_mux_t

MUX control names for clock mux setting.

These constants define the mux control names for clock mux setting.

0:7: REG offset to CCM_BASE in bytes.
8:15: Root clock setting bit field shift.
16:31: Root clock setting bit field width.

◆ clock_name_t

typedef enum _clock_name clock_name_t

Clock name used to get clock frequency.

◆ clock_osc_t

typedef enum _clock_osc clock_osc_t

OSC 24M sorce select.

◆ clock_pfd_t

typedef enum _clock_pfd clock_pfd_t

PLL PFD name.

◆ clock_pll_t

typedef enum _clock_pll clock_pll_t

PLL name.

◆ clock_sys_pll_config_t

typedef struct _clock_sys_pll_config clock_sys_pll_config_t

PLL configuration for System.

◆ clock_usb_phy_src_t

typedef enum _clock_usb_phy_src clock_usb_phy_src_t

Source of the USB HS PHY.

◆ clock_usb_pll_config_t

typedef struct _clock_usb_pll_config clock_usb_pll_config_t

PLL configuration for USB.

◆ clock_usb_src_t

typedef enum _clock_usb_src clock_usb_src_t

USB clock source definition.

◆ clock_video_pll_config_t

typedef struct _clock_video_pll_config clock_video_pll_config_t

PLL configuration for AUDIO and VIDEO.

Enumeration Type Documentation

◆ _clock_div

enum _clock_div

DIV control names for clock div setting.

These constants define div control names for clock div setting.

0:7: REG offset to CCM_BASE in bytes.
8:15: Root clock setting bit field shift.
16:31: Root clock setting bit field width.

Enumerator
kCLOCK_ArmDiv	core div name
kCLOCK_PeriphClk2Div	periph clock2 div name
kCLOCK_SemcDiv	semc div name
kCLOCK_AhbDiv	ahb div name
kCLOCK_IpgDiv	ipg div name
kCLOCK_LpspiDiv	lpspi div name
kCLOCK_LcdifDiv	lcdif div name
kCLOCK_FlexspiDiv	flexspi div name
kCLOCK_PerclkDiv	perclk div name
kCLOCK_CanDiv	can div name
kCLOCK_TraceDiv	trace div name
kCLOCK_Usdhc2Div	usdhc2 div name
kCLOCK_Usdhc1Div	usdhc1 div name
kCLOCK_UartDiv	uart div name
kCLOCK_Flexio2Div	flexio2 pre div name
kCLOCK_Sai3PreDiv	sai3 pre div name
kCLOCK_Sai3Div	sai3 div name
kCLOCK_Flexio2PreDiv	sai3 pre div name
kCLOCK_Sai1PreDiv	sai1 pre div name
kCLOCK_Sai1Div	sai1 div name
kCLOCK_Sai2PreDiv	sai2 pre div name
kCLOCK_Sai2Div	sai2 div name
kCLOCK_Spdif0PreDiv	spdif pre div name
kCLOCK_Spdif0Div	spdif div name
kCLOCK_Flexio1PreDiv	flexio1 pre div name
kCLOCK_Flexio1Div	flexio1 div name
kCLOCK_Lpi2cDiv	lpi2c div name
kCLOCK_LcdifPreDiv	lcdif pre div name
kCLOCK_CsiDiv	csi div name

Definition at line 718 of file fsl_clock.h.

◆ _clock_gate_value

enum _clock_gate_value

Clock gate value.

Enumerator
kCLOCK_ClockNotNeeded	Clock is off during all modes.
kCLOCK_ClockNeededRun	Clock is on in run mode, but off in WAIT and STOP modes
kCLOCK_ClockNeededRunWait	Clock is on during all modes, except STOP mode

Definition at line 583 of file fsl_clock.h.

◆ _clock_ip_name

enum _clock_ip_name

CCM CCGR gate control for each module independently.

Enumerator
kCLOCK_IpInvalid
kCLOCK_Aips_tz1	CCGR0, CG0
kCLOCK_Aips_tz2	CCGR0, CG1
kCLOCK_Mqs	CCGR0, CG2
kCLOCK_FlexSpiExsc	CCGR0, CG3
kCLOCK_Sim_M_Main	CCGR0, CG4
kCLOCK_Dcp	CCGR0, CG5
kCLOCK_Lpuart3	CCGR0, CG6
kCLOCK_Can1	CCGR0, CG7
kCLOCK_Can1S	CCGR0, CG8
kCLOCK_Can2	CCGR0, CG9
kCLOCK_Can2S	CCGR0, CG10
kCLOCK_Trace	CCGR0, CG11
kCLOCK_Gpt2	CCGR0, CG12
kCLOCK_Gpt2S	CCGR0, CG13
kCLOCK_Lpuart2	CCGR0, CG14
kCLOCK_Gpio2	CCGR0, CG15
kCLOCK_Lpspi1	CCGR1, CG0
kCLOCK_Lpspi2	CCGR1, CG1
kCLOCK_Lpspi3	CCGR1, CG2
kCLOCK_Lpspi4	CCGR1, CG3
kCLOCK_Adc2	CCGR1, CG4
kCLOCK_Enet	CCGR1, CG5
kCLOCK_Pit	CCGR1, CG6
kCLOCK_Aoi2	CCGR1, CG7
kCLOCK_Adc1	CCGR1, CG8
kCLOCK_SemcExsc	CCGR1, CG9
kCLOCK_Gpt1	CCGR1, CG10
kCLOCK_Gpt1S	CCGR1, CG11
kCLOCK_Lpuart4	CCGR1, CG12
kCLOCK_Gpio1	CCGR1, CG13
kCLOCK_Csu	CCGR1, CG14
kCLOCK_Gpio5	CCGR1, CG15
kCLOCK_OcramExsc	CCGR2, CG0
kCLOCK_Csi	CCGR2, CG1
kCLOCK_IomuxcSnvs	CCGR2, CG2
kCLOCK_Lpi2c1	CCGR2, CG3
kCLOCK_Lpi2c2	CCGR2, CG4
kCLOCK_Lpi2c3	CCGR2, CG5
kCLOCK_Ocotp	CCGR2, CG6
kCLOCK_Xbar3	CCGR2, CG7
kCLOCK_Ipmux1	CCGR2, CG8
kCLOCK_Ipmux2	CCGR2, CG9
kCLOCK_Ipmux3	CCGR2, CG10
kCLOCK_Xbar1	CCGR2, CG11
kCLOCK_Xbar2	CCGR2, CG12
kCLOCK_Gpio3	CCGR2, CG13
kCLOCK_Lcd	CCGR2, CG14
kCLOCK_Pxp	CCGR2, CG15
kCLOCK_Flexio2	CCGR3, CG0
kCLOCK_Lpuart5	CCGR3, CG1
kCLOCK_Semc	CCGR3, CG2
kCLOCK_Lpuart6	CCGR3, CG3
kCLOCK_Aoi1	CCGR3, CG4
kCLOCK_LcdPixel	CCGR3, CG5
kCLOCK_Gpio4	CCGR3, CG6
kCLOCK_Ewm0	CCGR3, CG7
kCLOCK_Wdog1	CCGR3, CG8
kCLOCK_FlexRam	CCGR3, CG9
kCLOCK_Acmp1	CCGR3, CG10
kCLOCK_Acmp2	CCGR3, CG11
kCLOCK_Acmp3	CCGR3, CG12
kCLOCK_Acmp4	CCGR3, CG13
kCLOCK_Ocram	CCGR3, CG14
kCLOCK_IomuxcSnvsGpr	CCGR3, CG15
kCLOCK_Iomuxc	CCGR4, CG1
kCLOCK_IomuxcGpr	CCGR4, CG2
kCLOCK_Bee	CCGR4, CG3
kCLOCK_SimM7	CCGR4, CG4
kCLOCK_Tsc	CCGR4, CG5
kCLOCK_SimM	CCGR4, CG6
kCLOCK_SimEms	CCGR4, CG7
kCLOCK_Pwm1	CCGR4, CG8
kCLOCK_Pwm2	CCGR4, CG9
kCLOCK_Pwm3	CCGR4, CG10
kCLOCK_Pwm4	CCGR4, CG11
kCLOCK_Enc1	CCGR4, CG12
kCLOCK_Enc2	CCGR4, CG13
kCLOCK_Enc3	CCGR4, CG14
kCLOCK_Enc4	CCGR4, CG15
kCLOCK_Rom	CCGR5, CG0
kCLOCK_Flexio1	CCGR5, CG1
kCLOCK_Wdog3	CCGR5, CG2
kCLOCK_Dma	CCGR5, CG3
kCLOCK_Kpp	CCGR5, CG4
kCLOCK_Wdog2	CCGR5, CG5
kCLOCK_Aips_tz4	CCGR5, CG6
kCLOCK_Spdif	CCGR5, CG7
kCLOCK_SimMain	CCGR5, CG8
kCLOCK_Sai1	CCGR5, CG9
kCLOCK_Sai2	CCGR5, CG10
kCLOCK_Sai3	CCGR5, CG11
kCLOCK_Lpuart1	CCGR5, CG12
kCLOCK_Lpuart7	CCGR5, CG13
kCLOCK_SnvsHp	CCGR5, CG14
kCLOCK_SnvsLp	CCGR5, CG15
kCLOCK_UsbOh3	CCGR6, CG0
kCLOCK_Usdhc1	CCGR6, CG1
kCLOCK_Usdhc2	CCGR6, CG2
kCLOCK_Dcdc	CCGR6, CG3
kCLOCK_Ipmux4	CCGR6, CG4
kCLOCK_FlexSpi	CCGR6, CG5
kCLOCK_Trng	CCGR6, CG6
kCLOCK_Lpuart8	CCGR6, CG7
kCLOCK_Timer4	CCGR6, CG8
kCLOCK_Aips_tz3	CCGR6, CG9
kCLOCK_SimPer	CCGR6, CG10
kCLOCK_Anadig	CCGR6, CG11
kCLOCK_Lpi2c4	CCGR6, CG12
kCLOCK_Timer1	CCGR6, CG13
kCLOCK_Timer2	CCGR6, CG14
kCLOCK_Timer3	CCGR6, CG15

Definition at line 444 of file fsl_clock.h.

◆ _clock_mode_t

enum _clock_mode_t

System clock mode.

Enumerator
kCLOCK_ModeRun	Remain in run mode.
kCLOCK_ModeWait	Transfer to wait mode.
kCLOCK_ModeStop	Transfer to stop mode.

Definition at line 591 of file fsl_clock.h.

◆ _clock_mux

enum _clock_mux

MUX control names for clock mux setting.

These constants define the mux control names for clock mux setting.

0:7: REG offset to CCM_BASE in bytes.
8:15: Root clock setting bit field shift.
16:31: Root clock setting bit field width.

Enumerator
kCLOCK_Pll3SwMux	pll3_sw_clk mux name
kCLOCK_PeriphMux	periph mux name
kCLOCK_SemcAltMux	semc mux name
kCLOCK_SemcMux	semc mux name
kCLOCK_PrePeriphMux	pre-periph mux name
kCLOCK_TraceMux	trace mux name
kCLOCK_PeriphClk2Mux	periph clock2 mux name
kCLOCK_LpspiMux	lpspi mux name
kCLOCK_FlexspiMux	flexspi mux name
kCLOCK_Usdhc2Mux	usdhc2 mux name
kCLOCK_Usdhc1Mux	usdhc1 mux name
kCLOCK_Sai3Mux	sai3 mux name
kCLOCK_Sai2Mux	sai2 mux name
kCLOCK_Sai1Mux	sai1 mux name
kCLOCK_PerclkMux	perclk mux name
kCLOCK_Flexio2Mux	flexio2 mux name
kCLOCK_CanMux	can mux name
kCLOCK_UartMux	uart mux name
kCLOCK_SpdifMux	spdif mux name
kCLOCK_Flexio1Mux	flexio1 mux name
kCLOCK_Lpi2cMux	lpi2c mux name
kCLOCK_LcdifPreMux	lcdif pre mux name
kCLOCK_CsiMux	csi mux name

Definition at line 606 of file fsl_clock.h.

◆ _clock_name

enum _clock_name

Clock name used to get clock frequency.

Enumerator
kCLOCK_CpuClk	CPU clock
kCLOCK_AhbClk	AHB clock
kCLOCK_SemcClk	SEMC clock
kCLOCK_IpgClk	IPG clock
kCLOCK_PerClk	PER clock
kCLOCK_OscClk	OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL].
kCLOCK_RtcClk	RTC clock. (RTCCLK)
kCLOCK_ArmPllClk	ARMPLLCLK.
kCLOCK_Usb1PllClk	USB1PLLCLK.
kCLOCK_Usb1PllPfd0Clk	USB1PLLPDF0CLK.
kCLOCK_Usb1PllPfd1Clk	USB1PLLPFD1CLK.
kCLOCK_Usb1PllPfd2Clk	USB1PLLPFD2CLK.
kCLOCK_Usb1PllPfd3Clk	USB1PLLPFD3CLK.
kCLOCK_Usb2PllClk	USB2PLLCLK.
kCLOCK_SysPllClk	SYSPLLCLK.
kCLOCK_SysPllPfd0Clk	SYSPLLPDF0CLK.
kCLOCK_SysPllPfd1Clk	SYSPLLPFD1CLK.
kCLOCK_SysPllPfd2Clk	SYSPLLPFD2CLK.
kCLOCK_SysPllPfd3Clk	SYSPLLPFD3CLK.
kCLOCK_EnetPll0Clk	Enet PLLCLK ref_enetpll0.
kCLOCK_EnetPll1Clk	Enet PLLCLK ref_enetpll1.
kCLOCK_AudioPllClk	Audio PLLCLK.
kCLOCK_VideoPllClk	Video PLLCLK.

Definition at line 404 of file fsl_clock.h.

◆ _clock_osc

enum _clock_osc

OSC 24M sorce select.

Enumerator
kCLOCK_RcOsc	On chip OSC.
kCLOCK_XtalOsc	24M Xtal OSC

Definition at line 576 of file fsl_clock.h.

◆ _clock_pfd

enum _clock_pfd

PLL PFD name.

Enumerator
kCLOCK_Pfd0	PLL PFD0
kCLOCK_Pfd1	PLL PFD1
kCLOCK_Pfd2	PLL PFD2
kCLOCK_Pfd3	PLL PFD3

Definition at line 947 of file fsl_clock.h.

◆ _clock_pll

enum _clock_pll

PLL name.

Enumerator
kCLOCK_PllArm	PLL ARM
kCLOCK_PllSys	PLL SYS
kCLOCK_PllUsb1	PLL USB1
kCLOCK_PllAudio	PLL Audio
kCLOCK_PllVideo	PLL Video
kCLOCK_PllEnet	PLL Enet0
kCLOCK_PllEnet25M	PLL Enet1
kCLOCK_PllUsb2	PLL USB2

Definition at line 930 of file fsl_clock.h.

◆ _clock_pll_clk_src

enum _clock_pll_clk_src

PLL clock source, bypass cloco source also.

Enumerator
kCLOCK_PllClkSrc24M	Pll clock source 24M
kCLOCK_PllSrcClkPN	Pll clock source CLK1_P and CLK1_N

Definition at line 855 of file fsl_clock.h.

◆ _clock_usb_phy_src

enum _clock_usb_phy_src

Source of the USB HS PHY.

Enumerator
kCLOCK_Usbphy480M	Use 480M.

Definition at line 849 of file fsl_clock.h.

◆ _clock_usb_src

enum _clock_usb_src

USB clock source definition.

Enumerator
kCLOCK_Usb480M	Use 480M.
kCLOCK_UsbSrcUnused	Used when the function does not care the clock source.

Definition at line 841 of file fsl_clock.h.

Function Documentation

◆ CLOCK_ControlGate()

static void CLOCK_ControlGate	(	clock_ip_name_t	name,
		clock_gate_value_t	value
	)

inlinestatic

Control the clock gate for specific IP.

Parameters

name	Which clock to enable, see clock_ip_name_t.
value	Clock gate value to set, see clock_gate_value_t.

Definition at line 1042 of file fsl_clock.h.

◆ CLOCK_DeinitArmPll()

void CLOCK_DeinitArmPll ( void )

De-initialize the ARM PLL.

brief De-initialize the ARM PLL.

Definition at line 516 of file fsl_clock.c.

◆ CLOCK_DeinitAudioPll()

void CLOCK_DeinitAudioPll ( void )

De-initialize the Audio PLL.

brief De-initialize the Audio PLL.

Definition at line 711 of file fsl_clock.c.

◆ CLOCK_DeinitEnetPll()

void CLOCK_DeinitEnetPll ( void )

Deinitialize the ENET PLL.

This function disables the ENET PLL.

brief Deinitialize the ENET PLL.

This function disables the ENET PLL.

Definition at line 844 of file fsl_clock.c.

◆ CLOCK_DeinitExternalClk()

void CLOCK_DeinitExternalClk ( void )

Deinitialize the external 24MHz clock.

This function disables the external 24MHz clock.

After this function, please call CLOCK_SetXtal0Freq to set external clock frequency to 0.

brief Deinitialize the external 24MHz clock.

This function disables the external 24MHz clock.

After this function, please call ref CLOCK_SetXtal0Freq to set external clock frequency to 0.

Definition at line 182 of file fsl_clock.c.

◆ CLOCK_DeinitRcOsc24M()

void CLOCK_DeinitRcOsc24M ( void )

Power down the RCOSC 24M clock.

brief Power down the RCOSC 24M clock.

Definition at line 217 of file fsl_clock.c.

◆ CLOCK_DeinitSysPfd()

void CLOCK_DeinitSysPfd ( clock_pfd_t pfd )

De-initialize the System PLL PFD.

This function disables the System PLL PFD.

Parameters

pfd	Which PFD clock to disable.

brief De-initialize the System PLL PFD.

This function disables the System PLL PFD.

param pfd Which PFD clock to disable.

Definition at line 1098 of file fsl_clock.c.

◆ CLOCK_DeinitSysPll()

void CLOCK_DeinitSysPll ( void )

De-initialize the System PLL.

brief De-initialize the System PLL.

Definition at line 558 of file fsl_clock.c.

◆ CLOCK_DeinitUsb1Pfd()

void CLOCK_DeinitUsb1Pfd ( clock_pfd_t pfd )

De-initialize the USB1 PLL PFD.

This function disables the USB1 PLL PFD.

Parameters

pfd	Which PFD clock to disable.

brief De-initialize the USB1 PLL PFD.

This function disables the USB1 PLL PFD.

param pfd Which PFD clock to disable.

Definition at line 1136 of file fsl_clock.c.

◆ CLOCK_DeinitUsb1Pll()

void CLOCK_DeinitUsb1Pll ( void )

Deinitialize the USB1 PLL.

brief Deinitialize the USB1 PLL.

Definition at line 591 of file fsl_clock.c.

◆ CLOCK_DeinitUsb2Pll()

void CLOCK_DeinitUsb2Pll ( void )

Deinitialize the USB2 PLL.

brief Deinitialize the USB2 PLL.

Definition at line 624 of file fsl_clock.c.

◆ CLOCK_DeinitVideoPll()

void CLOCK_DeinitVideoPll ( void )

De-initialize the Video PLL.

brief De-initialize the Video PLL.

Definition at line 797 of file fsl_clock.c.

◆ CLOCK_DisableClock()

static void CLOCK_DisableClock ( clock_ip_name_t name )

inlinestatic

Disable the clock for specific IP.

Parameters

name	Which clock to disable, see clock_ip_name_t.

Definition at line 1069 of file fsl_clock.h.

◆ CLOCK_DisableUsbhs0PhyPllClock()

void CLOCK_DisableUsbhs0PhyPllClock ( void )

Disable USB HS PHY PLL clock.

This function disables USB HS PHY PLL clock.

brief Disable USB HS PHY PLL clock.

This function disables USB HS PHY PLL clock.

Definition at line 482 of file fsl_clock.c.

◆ CLOCK_DisableUsbhs1PhyPllClock()

void CLOCK_DisableUsbhs1PhyPllClock ( void )

Disable USB HS PHY PLL clock.

This function disables USB HS PHY PLL clock.

brief Disable USB HS PHY PLL clock.

This function disables USB HS PHY PLL clock.

Definition at line 1246 of file fsl_clock.c.

◆ CLOCK_EnableClock()

static void CLOCK_EnableClock ( clock_ip_name_t name )

inlinestatic

Enable the clock for specific IP.

Parameters

name	Which clock to enable, see clock_ip_name_t.

Definition at line 1059 of file fsl_clock.h.

◆ CLOCK_EnableUsbhs0Clock()

bool CLOCK_EnableUsbhs0Clock	(	clock_usb_src_t	src,
		uint32_t	freq
	)

Enable USB HS clock.

This function only enables the access to USB HS prepheral, upper layer should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

Parameters

src	USB HS does not care about the clock source, here must be kCLOCK_UsbSrcUnused.
freq	USB HS does not care about the clock source, so this parameter is ignored.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

brief Enable USB HS clock.

This function only enables the access to USB HS prepheral, upper layer should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused. param freq USB HS does not care about the clock source, so this parameter is ignored. retval true The clock is set successfully. retval false The clock source is invalid to get proper USB HS clock.

Definition at line 406 of file fsl_clock.c.

◆ CLOCK_EnableUsbhs0PhyPllClock()

bool CLOCK_EnableUsbhs0PhyPllClock	(	clock_usb_phy_src_t	src,
		uint32_t	freq
	)

Enable USB HS PHY PLL clock.

This function enables the internal 480MHz USB PHY PLL clock.

Parameters

src	USB HS PHY PLL clock source.
freq	The frequency specified by src.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

brief Enable USB HS PHY PLL clock.

This function enables the internal 480MHz USB PHY PLL clock.

param src USB HS PHY PLL clock source. param freq The frequency specified by src. retval true The clock is set successfully. retval false The clock source is invalid to get proper USB HS clock.

Definition at line 458 of file fsl_clock.c.

◆ CLOCK_EnableUsbhs1Clock()

bool CLOCK_EnableUsbhs1Clock	(	clock_usb_src_t	src,
		uint32_t	freq
	)

Enable USB HS clock.

This function only enables the access to USB HS prepheral, upper layer should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

Parameters

src	USB HS does not care about the clock source, here must be kCLOCK_UsbSrcUnused.
freq	USB HS does not care about the clock source, so this parameter is ignored.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

brief Enable USB HS clock.

This function only enables the access to USB HS prepheral, upper layer should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused. param freq USB HS does not care about the clock source, so this parameter is ignored. retval true The clock is set successfully. retval false The clock source is invalid to get proper USB HS clock.

Definition at line 433 of file fsl_clock.c.

◆ CLOCK_EnableUsbhs1PhyPllClock()

bool CLOCK_EnableUsbhs1PhyPllClock	(	clock_usb_phy_src_t	src,
		uint32_t	freq
	)

Enable USB HS PHY PLL clock.

This function enables the internal 480MHz USB PHY PLL clock.

Parameters

src	USB HS PHY PLL clock source.
freq	The frequency specified by src.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

brief Enable USB HS PHY PLL clock.

This function enables the internal 480MHz USB PHY PLL clock.

param src USB HS PHY PLL clock source. param freq The frequency specified by src. retval true The clock is set successfully. retval false The clock source is invalid to get proper USB HS clock.

Definition at line 1228 of file fsl_clock.c.

◆ CLOCK_GetAhbFreq()

uint32_t CLOCK_GetAhbFreq ( void )

Gets the AHB clock frequency.

Returns: The AHB clock frequency value in hertz.

brief Gets the AHB clock frequency.

return The AHB clock frequency value in hertz.

Definition at line 227 of file fsl_clock.c.

◆ CLOCK_GetCpuClkFreq()

static uint32_t CLOCK_GetCpuClkFreq ( void )

inlinestatic

Get the CCM CPU/core/system frequency.

Returns: Clock frequency; If the clock is invalid, returns 0.

Definition at line 1141 of file fsl_clock.h.

◆ CLOCK_GetDiv()

static uint32_t CLOCK_GetDiv ( clock_div_t divider )

inlinestatic

Get CCM DIV node value.

Parameters

divider Which div node to get, see clock_div_t.

Definition at line 1031 of file fsl_clock.h.

◆ CLOCK_GetFreq()

uint32_t CLOCK_GetFreq ( clock_name_t name )

Gets the clock frequency for a specific clock name.

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t.

Parameters

name	Clock names defined in clock_name_t

Returns: Clock frequency value in hertz

brief Gets the clock frequency for a specific clock name.

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t.

param clockName Clock names defined in clock_name_t return Clock frequency value in hertz

Definition at line 310 of file fsl_clock.c.

◆ CLOCK_GetIpgFreq()

uint32_t CLOCK_GetIpgFreq ( void )

Gets the IPG clock frequency.

Returns: The IPG clock frequency value in hertz.

brief Gets the IPG clock frequency.

return The IPG clock frequency value in hertz.

Definition at line 271 of file fsl_clock.c.

◆ CLOCK_GetMux()

static uint32_t CLOCK_GetMux ( clock_mux_t mux )

inlinestatic

Get CCM MUX value.

Parameters

mux	Which mux node to get, see clock_mux_t.

Returns: Clock mux value.

Definition at line 995 of file fsl_clock.h.

◆ CLOCK_GetOscFreq()

static uint32_t CLOCK_GetOscFreq ( void )

inlinestatic

Gets the OSC clock frequency.

This function will return the external XTAL OSC frequency if it is selected as the source of OSC, otherwise internal 24MHz RC OSC frequency will be returned.

Returns: Clock frequency; If the clock is invalid, returns 0.

Definition at line 1092 of file fsl_clock.h.

◆ CLOCK_GetPerClkFreq()

uint32_t CLOCK_GetPerClkFreq ( void )

Gets the PER clock frequency.

Returns: The PER clock frequency value in hertz.

brief Gets the PER clock frequency.

return The PER clock frequency value in hertz.

Definition at line 281 of file fsl_clock.c.

◆ CLOCK_GetPllBypassRefClk()

static uint32_t CLOCK_GetPllBypassRefClk	(	CCM_ANALOG_Type *	base,
		clock_pll_t	pll
	)

inlinestatic

Get PLL bypass clock value, it is PLL reference clock actually. If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 will be returned.

Parameters

base	CCM_ANALOG base pointer.
pll	PLL control name (see ccm_analog_pll_control_t enumeration)

Return values

bypass reference clock frequency value.

Definition at line 1329 of file fsl_clock.h.

◆ CLOCK_GetPllFreq()

uint32_t CLOCK_GetPllFreq ( clock_pll_t pll )

Get current PLL output frequency.

This function get current output frequency of specific PLL

Parameters

pll	pll name to get frequency.

Returns: The PLL output frequency in hertz.

brief Get current PLL output frequency.

This function get current output frequency of specific PLL

param pll pll name to get frequency. return The PLL output frequency in hertz.

Definition at line 857 of file fsl_clock.c.

◆ CLOCK_GetRtcFreq()

static uint32_t CLOCK_GetRtcFreq ( void )

inlinestatic

Gets the RTC clock frequency.

Returns: Clock frequency; If the clock is invalid, returns 0.

Definition at line 1191 of file fsl_clock.h.

◆ CLOCK_GetSemcFreq()

uint32_t CLOCK_GetSemcFreq ( void )

Gets the SEMC clock frequency.

Returns: The SEMC clock frequency value in hertz.

brief Gets the SEMC clock frequency.

return The SEMC clock frequency value in hertz.

Definition at line 237 of file fsl_clock.c.

◆ CLOCK_GetSysPfdFreq()

uint32_t CLOCK_GetSysPfdFreq ( clock_pfd_t pfd )

Get current System PLL PFD output frequency.

This function get current output frequency of specific System PLL PFD

Parameters

pfd	pfd name to get frequency.

Returns: The PFD output frequency in hertz.

brief Get current System PLL PFD output frequency.

This function get current output frequency of specific System PLL PFD

param pfd pfd name to get frequency. return The PFD output frequency in hertz.

Definition at line 1149 of file fsl_clock.c.

◆ CLOCK_GetUsb1PfdFreq()

uint32_t CLOCK_GetUsb1PfdFreq ( clock_pfd_t pfd )

Get current USB1 PLL PFD output frequency.

This function get current output frequency of specific USB1 PLL PFD

Parameters

pfd	pfd name to get frequency.

Returns: The PFD output frequency in hertz.

brief Get current USB1 PLL PFD output frequency.

This function get current output frequency of specific USB1 PLL PFD

param pfd pfd name to get frequency. return The PFD output frequency in hertz.

Definition at line 1188 of file fsl_clock.c.

◆ CLOCK_InitArmPll()

void CLOCK_InitArmPll ( const clock_arm_pll_config_t * config )

Initialize the ARM PLL.

This function initialize the ARM PLL with specific settings

Parameters

config configuration to set to PLL.

brief Initialize the ARM PLL.

This function initialize the ARM PLL with specific settings

param config configuration to set to PLL.

Definition at line 495 of file fsl_clock.c.

◆ CLOCK_InitAudioPll()

void CLOCK_InitAudioPll ( const clock_audio_pll_config_t * config )

Initializes the Audio PLL.

This function initializes the Audio PLL with specific settings

Parameters

config Configuration to set to PLL.

brief Initializes the Audio PLL.

This function initializes the Audio PLL with specific settings

param config Configuration to set to PLL.

Definition at line 636 of file fsl_clock.c.

◆ CLOCK_InitEnetPll()

void CLOCK_InitEnetPll ( const clock_enet_pll_config_t * config )

Initialize the ENET PLL.

This function initializes the ENET PLL with specific settings.

Parameters

config Configuration to set to PLL.

brief Initialize the ENET PLL.

This function initializes the ENET PLL with specific settings.

param config Configuration to set to PLL.

Definition at line 809 of file fsl_clock.c.

◆ CLOCK_InitExternalClk()

void CLOCK_InitExternalClk ( bool bypassXtalOsc )

Initialize the external 24MHz clock.

This function supports two modes:

Use external crystal oscillator.
Bypass the external crystal oscillator, using input source clock directly.

After this function, please call CLOCK_SetXtal0Freq to inform clock driver the external clock frequency.

Parameters

bypassXtalOsc Pass in true to bypass the external crystal oscillator.

Note: This device does not support bypass external crystal oscillator, so the input parameter should always be false.

brief Initialize the external 24MHz clock.

This function supports two modes:

Use external crystal oscillator.
Bypass the external crystal oscillator, using input source clock directly.

After this function, please call ref CLOCK_SetXtal0Freq to inform clock driver the external clock frequency.

param bypassXtalOsc Pass in true to bypass the external crystal oscillator. note This device does not support bypass external crystal oscillator, so the input parameter should always be false.

Definition at line 158 of file fsl_clock.c.

◆ CLOCK_InitRcOsc24M()

void CLOCK_InitRcOsc24M ( void )

Initialize the RC oscillator 24MHz clock.

brief Initialize the RC oscillator 24MHz clock.

Definition at line 209 of file fsl_clock.c.

◆ CLOCK_InitSysPfd()

void CLOCK_InitSysPfd	(	clock_pfd_t	pfd,
		uint8_t	pfdFrac
	)

Initialize the System PLL PFD.

This function initializes the System PLL PFD. During new value setting, the clock output is disabled to prevent glitch.

Parameters

pfd	Which PFD clock to enable.
pfdFrac	The PFD FRAC value.

Note: It is recommended that PFD settings are kept between 12-35.

brief Initialize the System PLL PFD.

This function initializes the System PLL PFD. During new value setting, the clock output is disabled to prevent glitch.

param pfd Which PFD clock to enable. param pfdFrac The PFD FRAC value. note It is recommended that PFD settings are kept between 12-35.

Definition at line 1075 of file fsl_clock.c.

◆ CLOCK_InitSysPll()

void CLOCK_InitSysPll ( const clock_sys_pll_config_t * config )

Initialize the System PLL.

This function initializes the System PLL with specific settings

Parameters

config Configuration to set to PLL.

brief Initialize the System PLL.

This function initializes the System PLL with specific settings

param config Configuration to set to PLL.

Definition at line 528 of file fsl_clock.c.

◆ CLOCK_InitUsb1Pfd()

void CLOCK_InitUsb1Pfd	(	clock_pfd_t	pfd,
		uint8_t	pfdFrac
	)

Initialize the USB1 PLL PFD.

This function initializes the USB1 PLL PFD. During new value setting, the clock output is disabled to prevent glitch.

Parameters

pfd	Which PFD clock to enable.
pfdFrac	The PFD FRAC value.

Note: It is recommended that PFD settings are kept between 12-35.

brief Initialize the USB1 PLL PFD.

This function initializes the USB1 PLL PFD. During new value setting, the clock output is disabled to prevent glitch.

param pfd Which PFD clock to enable. param pfdFrac The PFD FRAC value. note It is recommended that PFD settings are kept between 12-35.

Definition at line 1113 of file fsl_clock.c.

◆ CLOCK_InitUsb1Pll()

void CLOCK_InitUsb1Pll ( const clock_usb_pll_config_t * config )

Initialize the USB1 PLL.

This function initializes the USB1 PLL with specific settings

Parameters

config Configuration to set to PLL.

brief Initialize the USB1 PLL.

This function initializes the USB1 PLL with specific settings

param config Configuration to set to PLL.

Definition at line 570 of file fsl_clock.c.

◆ CLOCK_InitUsb2Pll()

void CLOCK_InitUsb2Pll ( const clock_usb_pll_config_t * config )

Initialize the USB2 PLL.

This function initializes the USB2 PLL with specific settings

Parameters

config Configuration to set to PLL.

brief Initialize the USB2 PLL.

This function initializes the USB2 PLL with specific settings

param config Configuration to set to PLL.

Definition at line 603 of file fsl_clock.c.

◆ CLOCK_InitVideoPll()

void CLOCK_InitVideoPll ( const clock_video_pll_config_t * config )

Initialize the video PLL.

This function configures the Video PLL with specific settings

Parameters

config configuration to set to PLL.

brief Initialize the video PLL.

This function configures the Video PLL with specific settings

param config configuration to set to PLL.

Definition at line 723 of file fsl_clock.c.

◆ CLOCK_IsPllBypassed()

static bool CLOCK_IsPllBypassed	(	CCM_ANALOG_Type *	base,
		clock_pll_t	pll
	)

inlinestatic

Check if PLL is bypassed.

Parameters

base	CCM_ANALOG base pointer.
pll	PLL control name (see ccm_analog_pll_control_t enumeration)

Returns

PLL bypass status.

true: The PLL is bypassed.
false: The PLL is not bypassed.

Definition at line 1289 of file fsl_clock.h.

◆ CLOCK_IsPllEnabled()

static bool CLOCK_IsPllEnabled	(	CCM_ANALOG_Type *	base,
		clock_pll_t	pll
	)

inlinestatic

Check if PLL is enabled.

Parameters

base	CCM_ANALOG base pointer.
pll	PLL control name (see ccm_analog_pll_control_t enumeration)

Returns

PLL bypass status.

true: The PLL is enabled.
false: The PLL is not enabled.

Definition at line 1303 of file fsl_clock.h.

◆ CLOCK_SetDiv()

static void CLOCK_SetDiv	(	clock_div_t	divider,
		uint32_t	value
	)

inlinestatic

Set CCM DIV node to certain value.

Parameters

divider	Which div node to set, see clock_div_t.
value	Clock div value to set, different divider has different value range.

Definition at line 1006 of file fsl_clock.h.

◆ CLOCK_SetMode()

static void CLOCK_SetMode ( clock_mode_t mode )

inlinestatic

Setting the low power mode that system will enter on next assertion of dsm_request signal.

Parameters

mode	Which mode to enter, see clock_mode_t.

Definition at line 1079 of file fsl_clock.h.

◆ CLOCK_SetMux()

static void CLOCK_SetMux	(	clock_mux_t	mux,
		uint32_t	value
	)

inlinestatic

Set CCM MUX node to certain value.

Parameters

mux	Which mux node to set, see clock_mux_t.
value	Clock mux value to set, different mux has different value range.

Definition at line 969 of file fsl_clock.h.

◆ CLOCK_SetPllBypass()

static void CLOCK_SetPllBypass	(	CCM_ANALOG_Type *	base,
		clock_pll_t	pll,
		bool	bypass
	)

inlinestatic

PLL bypass setting.

Parameters

base	CCM_ANALOG base pointer.
pll	PLL control name (see ccm_analog_pll_control_t enumeration)
bypass	Bypass the PLL. true: Bypass the PLL. false:Not bypass the PLL.

Definition at line 1268 of file fsl_clock.h.

◆ CLOCK_SetPllBypassRefClkSrc()

static void CLOCK_SetPllBypassRefClkSrc	(	CCM_ANALOG_Type *	base,
		clock_pll_t	pll,
		uint32_t	src
	)

inlinestatic

PLL bypass clock source setting. Note: change the bypass clock source also change the pll reference clock source.

Parameters

base	CCM_ANALOG base pointer.
pll	PLL control name (see ccm_analog_pll_control_t enumeration)
src	Bypass clock source, reference _clock_pll_bypass_clk_src.

Definition at line 1316 of file fsl_clock.h.

◆ CLOCK_SetRtcXtalFreq()

static void CLOCK_SetRtcXtalFreq ( uint32_t freq )

inlinestatic

Set the RTC XTAL (32K OSC) frequency based on board setting.

Parameters

freq	The RTC XTAL input clock frequency in Hz.

Definition at line 1211 of file fsl_clock.h.

◆ CLOCK_SetXtalFreq()

static void CLOCK_SetXtalFreq ( uint32_t freq )

inlinestatic

Set the XTAL (24M OSC) frequency based on board setting.

Parameters

freq	The XTAL input clock frequency in Hz.

Definition at line 1201 of file fsl_clock.h.

◆ CLOCK_SwitchOsc()

void CLOCK_SwitchOsc ( clock_osc_t osc )

Switch the OSC.

This function switches the OSC source for SoC.

Parameters

osc	OSC source to switch to.

brief Switch the OSC.

This function switches the OSC source for SoC.

param osc OSC source to switch to.

Definition at line 194 of file fsl_clock.c.

Variable Documentation

◆ denominator [1/3]

uint32_t _clock_sys_pll_config::denominator

30 bit denominator of fractional loop divider

Definition at line 885 of file fsl_clock.h.

◆ denominator [2/3]

uint32_t _clock_audio_pll_config::denominator

30 bit denominator of fractional loop divider

Definition at line 899 of file fsl_clock.h.

◆ denominator [3/3]

uint32_t _clock_video_pll_config::denominator

30 bit denominator of fractional loop divider

Definition at line 909 of file fsl_clock.h.

◆ enableClkOutput

bool _clock_enet_pll_config::enableClkOutput

Power on and enable PLL clock output for ENET0 (ref_enetpll0).

Definition at line 917 of file fsl_clock.h.

◆ enableClkOutput25M

bool _clock_enet_pll_config::enableClkOutput25M

Power on and enable PLL clock output for ENET1 (ref_enetpll1).

Definition at line 919 of file fsl_clock.h.

◆ g_rtcXtalFreq

volatile uint32_t g_rtcXtalFreq

External RTC XTAL (32K OSC) clock frequency.

The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the function CLOCK_SetRtcXtalFreq to set the value in to clock driver.

Definition at line 61 of file fsl_clock.c.

◆ g_xtalFreq

volatile uint32_t g_xtalFreq

External XTAL (24M OSC/SYSOSC) clock frequency.

The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the function CLOCK_SetXtalFreq to set the value in to clock driver. For example, if XTAL is 24MHz,

CLOCK_InitExternalClk(false);

CLOCK_SetXtalFreq(240000000);

Definition at line 59 of file fsl_clock.c.

◆ loopDivider [1/6]

uint32_t _clock_arm_pll_config::loopDivider

PLL loop divider. Valid range for divider value: 54-108. Fout=Fin*loopDivider/2.

Definition at line 864 of file fsl_clock.h.

◆ loopDivider [2/6]

uint8_t _clock_usb_pll_config::loopDivider

PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22

Definition at line 871 of file fsl_clock.h.

◆ loopDivider [3/6]

uint8_t _clock_sys_pll_config::loopDivider

PLL loop divider. Intended to be 1 (528M). 0 - Fout=Fref*20; 1 - Fout=Fref*22

Definition at line 881 of file fsl_clock.h.

◆ loopDivider [4/6]

uint8_t _clock_audio_pll_config::loopDivider

PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.

Definition at line 896 of file fsl_clock.h.

◆ loopDivider [5/6]

uint8_t _clock_video_pll_config::loopDivider

PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.

Definition at line 906 of file fsl_clock.h.

◆ loopDivider [6/6]

uint8_t _clock_enet_pll_config::loopDivider

Controls the frequency of the ENET0 reference clock. b00 25MHz b01 50MHz b10 100MHz (not 50% duty cycle) b11 125MHz

Definition at line 920 of file fsl_clock.h.

◆ numerator [1/3]

uint32_t _clock_sys_pll_config::numerator

30 bit numerator of fractional loop divider.

Definition at line 884 of file fsl_clock.h.

◆ numerator [2/3]

uint32_t _clock_audio_pll_config::numerator

30 bit numerator of fractional loop divider.

Definition at line 898 of file fsl_clock.h.

◆ numerator [3/3]

uint32_t _clock_video_pll_config::numerator

30 bit numerator of fractional loop divider.

Definition at line 908 of file fsl_clock.h.

◆ postDivider [1/2]

uint8_t _clock_audio_pll_config::postDivider

Divider after the PLL, should only be 1, 2, 4, 8, 16.

Definition at line 897 of file fsl_clock.h.

◆ postDivider [2/2]

uint8_t _clock_video_pll_config::postDivider

Divider after the PLL, should only be 1, 2, 4, 8, 16.

Definition at line 907 of file fsl_clock.h.