fsl_clock.h File Reference

#include "fsl_common.h"

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Go to the source code of this file.

Classes
struct	_clock_arm_pll_config
	PLL configuration for ARM. More...
struct	_clock_audio_pll_config
	PLL configuration for AUDIO and VIDEO. More...
struct	_clock_enet_pll_config
	PLL configuration for ENET. More...
struct	_clock_sys_pll_config
	PLL configuration for System. More...
struct	_clock_usb_pll_config
	PLL configuration for USB. More...
struct	_clock_video_pll_config
	PLL configuration for AUDIO and VIDEO. More...

Functions
OSC operations
void	CLOCK_DeinitExternalClk (void)
	Deinitialize the external 24MHz clock. More...
void	CLOCK_DeinitRcOsc24M (void)
	Power down the RCOSC 24M clock. More...
bool	CLOCK_EnableUsbhs0Clock (clock_usb_src_t src, uint32_t freq)
	Enable USB HS clock. More...
bool	CLOCK_EnableUsbhs1Clock (clock_usb_src_t src, uint32_t freq)
	Enable USB HS clock. More...
static uint32_t	CLOCK_GetRtcFreq (void)
	Gets the RTC clock frequency. More...
void	CLOCK_InitExternalClk (bool bypassXtalOsc)
	Initialize the external 24MHz clock. More...
void	CLOCK_InitRcOsc24M (void)
	Initialize the RC oscillator 24MHz clock. More...
static void	CLOCK_SetRtcXtalFreq (uint32_t freq)
	Set the RTC XTAL (32K OSC) frequency based on board setting. More...
static void	CLOCK_SetXtalFreq (uint32_t freq)
	Set the XTAL (24M OSC) frequency based on board setting. More...
void	CLOCK_SwitchOsc (clock_osc_t osc)
	Switch the OSC. More...
PLL/PFD operations
void	CLOCK_DeinitArmPll (void)
	De-initialize the ARM PLL. More...
void	CLOCK_DeinitAudioPll (void)
	De-initialize the Audio PLL. More...
void	CLOCK_DeinitEnetPll (void)
	Deinitialize the ENET PLL. More...
void	CLOCK_DeinitSysPfd (clock_pfd_t pfd)
	De-initialize the System PLL PFD. More...
void	CLOCK_DeinitSysPll (void)
	De-initialize the System PLL. More...
void	CLOCK_DeinitUsb1Pfd (clock_pfd_t pfd)
	De-initialize the USB1 PLL PFD. More...
void	CLOCK_DeinitUsb1Pll (void)
	Deinitialize the USB1 PLL. More...
void	CLOCK_DeinitUsb2Pll (void)
	Deinitialize the USB2 PLL. More...
void	CLOCK_DeinitVideoPll (void)
	De-initialize the Video PLL. More...
void	CLOCK_DisableUsbhs0PhyPllClock (void)
	Disable USB HS PHY PLL clock. More...
void	CLOCK_DisableUsbhs1PhyPllClock (void)
	Disable USB HS PHY PLL clock. More...
bool	CLOCK_EnableUsbhs0PhyPllClock (clock_usb_phy_src_t src, uint32_t freq)
	Enable USB HS PHY PLL clock. More...
bool	CLOCK_EnableUsbhs1PhyPllClock (clock_usb_phy_src_t src, uint32_t freq)
	Enable USB HS PHY PLL clock. More...
static uint32_t	CLOCK_GetPllBypassRefClk (CCM_ANALOG_Type *base, clock_pll_t pll)
	Get PLL bypass clock value, it is PLL reference clock actually. If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 will be returned. More...
uint32_t	CLOCK_GetPllFreq (clock_pll_t pll)
	Get current PLL output frequency. More...
uint32_t	CLOCK_GetSysPfdFreq (clock_pfd_t pfd)
	Get current System PLL PFD output frequency. More...
uint32_t	CLOCK_GetUsb1PfdFreq (clock_pfd_t pfd)
	Get current USB1 PLL PFD output frequency. More...
void	CLOCK_InitArmPll (const clock_arm_pll_config_t *config)
	Initialize the ARM PLL. More...
void	CLOCK_InitAudioPll (const clock_audio_pll_config_t *config)
	Initializes the Audio PLL. More...
void	CLOCK_InitEnetPll (const clock_enet_pll_config_t *config)
	Initialize the ENET PLL. More...
void	CLOCK_InitSysPfd (clock_pfd_t pfd, uint8_t pfdFrac)
	Initialize the System PLL PFD. More...
void	CLOCK_InitSysPll (const clock_sys_pll_config_t *config)
	Initialize the System PLL. More...
void	CLOCK_InitUsb1Pfd (clock_pfd_t pfd, uint8_t pfdFrac)
	Initialize the USB1 PLL PFD. More...
void	CLOCK_InitUsb1Pll (const clock_usb_pll_config_t *config)
	Initialize the USB1 PLL. More...
void	CLOCK_InitUsb2Pll (const clock_usb_pll_config_t *config)
	Initialize the USB2 PLL. More...
void	CLOCK_InitVideoPll (const clock_video_pll_config_t *config)
	Initialize the video PLL. More...
static bool	CLOCK_IsPllBypassed (CCM_ANALOG_Type *base, clock_pll_t pll)
	Check if PLL is bypassed. More...
static bool	CLOCK_IsPllEnabled (CCM_ANALOG_Type *base, clock_pll_t pll)
	Check if PLL is enabled. More...
static void	CLOCK_SetPllBypass (CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass)
	PLL bypass setting. More...
static void	CLOCK_SetPllBypassRefClkSrc (CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src)
	PLL bypass clock source setting. Note: change the bypass clock source also change the pll reference clock source. More...

Driver version
Configure whether driver controls clock When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver. Note All drivers share this feature switcher. If it is set to 1, application should handle clock enable and disable for all drivers.
enum	_clock_div {   kCLOCK_ArmDiv, kCLOCK_PeriphClk2Div, kCLOCK_SemcDiv, kCLOCK_AhbDiv,   kCLOCK_IpgDiv, kCLOCK_LpspiDiv, kCLOCK_LcdifDiv, kCLOCK_FlexspiDiv,   kCLOCK_PerclkDiv, kCLOCK_CanDiv, kCLOCK_TraceDiv, kCLOCK_Usdhc2Div,   kCLOCK_Usdhc1Div, kCLOCK_UartDiv, kCLOCK_Flexio2Div, kCLOCK_Sai3PreDiv,   kCLOCK_Sai3Div, kCLOCK_Flexio2PreDiv, kCLOCK_Sai1PreDiv, kCLOCK_Sai1Div,   kCLOCK_Sai2PreDiv, kCLOCK_Sai2Div, kCLOCK_Spdif0PreDiv, kCLOCK_Spdif0Div,   kCLOCK_Flexio1PreDiv, kCLOCK_Flexio1Div, kCLOCK_Lpi2cDiv, kCLOCK_LcdifPreDiv,   kCLOCK_CsiDiv }
	DIV control names for clock div setting. More...
enum	_clock_gate_value { kCLOCK_ClockNotNeeded = 0U, kCLOCK_ClockNeededRun = 1U, kCLOCK_ClockNeededRunWait = 3U }
	Clock gate value. More...
enum	_clock_ip_name {   kCLOCK_IpInvalid = -1, kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT,   kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT, kCLOCK_Sim_M_Main = (0U << 8U) | CCM_CCGR0_CG4_SHIFT, kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT,   kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT, kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT, kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT, kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT,   kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT,   kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG2_SHIFT,   kCLOCK_Lpspi4 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT, kCLOCK_Adc2 = (1U << 8U) | CCM_CCGR1_CG4_SHIFT, kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT, kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT,   kCLOCK_Aoi2 = (1U << 8U) | CCM_CCGR1_CG7_SHIFT, kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT, kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT,   kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT,   kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT, kCLOCK_Csi = (2U << 8U) | CCM_CCGR2_CG1_SHIFT, kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT,   kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT, kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT,   kCLOCK_Xbar3 = (2U << 8U) | CCM_CCGR2_CG7_SHIFT, kCLOCK_Ipmux1 = (2U << 8U) | CCM_CCGR2_CG8_SHIFT, kCLOCK_Ipmux2 = (2U << 8U) | CCM_CCGR2_CG9_SHIFT, kCLOCK_Ipmux3 = (2U << 8U) | CCM_CCGR2_CG10_SHIFT,   kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, kCLOCK_Lcd = (2U << 8U) | CCM_CCGR2_CG14_SHIFT,   kCLOCK_Pxp = (2U << 8U) | CCM_CCGR2_CG15_SHIFT, kCLOCK_Flexio2 = (3U << 8U) | CCM_CCGR3_CG0_SHIFT, kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT, kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT,   kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT, kCLOCK_Aoi1 = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, kCLOCK_LcdPixel = (3U << 8U) | CCM_CCGR3_CG5_SHIFT, kCLOCK_Gpio4 = (3U << 8U) | CCM_CCGR3_CG6_SHIFT,   kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT,   kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT, kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT, kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT, kCLOCK_Ocram = (3U << 8U) | CCM_CCGR3_CG14_SHIFT,   kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT,   kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT, kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT,   kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT, kCLOCK_Pwm3 = (4U << 8U) | CCM_CCGR4_CG10_SHIFT, kCLOCK_Pwm4 = (4U << 8U) | CCM_CCGR4_CG11_SHIFT,   kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT, kCLOCK_Enc3 = (4U << 8U) | CCM_CCGR4_CG14_SHIFT, kCLOCK_Enc4 = (4U << 8U) | CCM_CCGR4_CG15_SHIFT,   kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT,   kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT, kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT, kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT,   kCLOCK_SimMain = (5U << 8U) | CCM_CCGR5_CG8_SHIFT, kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT,   kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT, kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT,   kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT, kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT, kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT,   kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT, kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT,   kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT, kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT, kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT,   kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT, kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT, kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT }
	CCM CCGR gate control for each module independently. More...
enum	_clock_mode_t { kCLOCK_ModeRun = 0U, kCLOCK_ModeWait = 1U, kCLOCK_ModeStop = 2U }
	System clock mode. More...
enum	_clock_mux {   kCLOCK_Pll3SwMux, kCLOCK_PeriphMux, kCLOCK_SemcAltMux, kCLOCK_SemcMux,   kCLOCK_PrePeriphMux, kCLOCK_TraceMux, kCLOCK_PeriphClk2Mux, kCLOCK_LpspiMux,   kCLOCK_FlexspiMux, kCLOCK_Usdhc2Mux, kCLOCK_Usdhc1Mux, kCLOCK_Sai3Mux,   kCLOCK_Sai2Mux, kCLOCK_Sai1Mux, kCLOCK_PerclkMux, kCLOCK_Flexio2Mux,   kCLOCK_CanMux, kCLOCK_UartMux, kCLOCK_SpdifMux, kCLOCK_Flexio1Mux,   kCLOCK_Lpi2cMux, kCLOCK_LcdifPreMux, kCLOCK_CsiMux }
	MUX control names for clock mux setting. More...
enum	_clock_name {   kCLOCK_CpuClk = 0x0U, kCLOCK_AhbClk = 0x1U, kCLOCK_SemcClk = 0x2U, kCLOCK_IpgClk = 0x3U,   kCLOCK_PerClk = 0x4U, kCLOCK_OscClk = 0x5U, kCLOCK_RtcClk = 0x6U, kCLOCK_ArmPllClk = 0x7U,   kCLOCK_Usb1PllClk = 0x8U, kCLOCK_Usb1PllPfd0Clk = 0x9U, kCLOCK_Usb1PllPfd1Clk = 0xAU, kCLOCK_Usb1PllPfd2Clk = 0xBU,   kCLOCK_Usb1PllPfd3Clk = 0xCU, kCLOCK_Usb2PllClk = 0xDU, kCLOCK_SysPllClk = 0xEU, kCLOCK_SysPllPfd0Clk = 0xFU,   kCLOCK_SysPllPfd1Clk = 0x10U, kCLOCK_SysPllPfd2Clk = 0x11U, kCLOCK_SysPllPfd3Clk = 0x12U, kCLOCK_EnetPll0Clk = 0x13U,   kCLOCK_EnetPll1Clk = 0x14U, kCLOCK_AudioPllClk = 0x15U, kCLOCK_VideoPllClk = 0x16U }
	Clock name used to get clock frequency. More...
enum	_clock_osc { kCLOCK_RcOsc = 0U, kCLOCK_XtalOsc = 1U }
	OSC 24M sorce select. More...
enum	_clock_pfd { kCLOCK_Pfd0 = 0U, kCLOCK_Pfd1 = 1U, kCLOCK_Pfd2 = 2U, kCLOCK_Pfd3 = 3U }
	PLL PFD name. More...
enum	_clock_pll {   kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM_OFFSET, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT), kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT),   kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO_OFFSET, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT), kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT), kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT), kCLOCK_PllUsb2 = CCM_ANALOG_TUPLE(PLL_USB2_OFFSET, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT) }
	PLL name. More...
enum	_clock_pll_clk_src { kCLOCK_PllClkSrc24M = 0U, kCLOCK_PllSrcClkPN = 1U }
	PLL clock source, bypass cloco source also. More...
enum	_clock_usb_phy_src { kCLOCK_Usbphy480M = 0 }
	Source of the USB HS PHY. More...
enum	_clock_usb_src { kCLOCK_Usb480M = 0, kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU }
	USB clock source definition. More...
#define	ADC_CLOCKS
	Clock ip name array for ADC. More...
#define	AOI_CLOCKS
	Clock ip name array for AOI. More...
#define	BEE_CLOCKS
	Clock ip name array for BEE. More...
#define	CACRR_OFFSET   0x10
#define	CBCDR_OFFSET   0x14
#define	CBCMR_OFFSET   0x18
#define	CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK   (0xC000U)
#define	CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT   (14U)
#define	CCM_ANALOG_PLL_BYPASS_SHIFT   (16U)
#define	CCM_ANALOG_TUPLE(reg, shift)   ((((reg)&0xFFFU) << 16U) | (shift))
	CCM ANALOG tuple macros to map corresponding registers and bit fields. More...
#define	CCM_ANALOG_TUPLE_REG(base, tuple)   CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
#define	CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off)   (*((volatile uint32_t *)((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFU) + (off))))
#define	CCM_ANALOG_TUPLE_SHIFT(tuple)   (((uint32_t)tuple) & 0x1FU)
#define	CCM_NO_BUSY_WAIT   (0x20U)
#define	CCM_TUPLE(reg, shift, mask, busyShift)   (int)(((reg)&0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
#define	CCM_TUPLE_BUSY_SHIFT(tuple)   ((((uint32_t)tuple) >> 26U) & 0x3FU)
#define	CCM_TUPLE_MASK(tuple)   ((uint32_t)((((uint32_t)(tuple) >> 13U) & 0x1FFFU) << (((((uint32_t)tuple) >> 8U) & 0x1FU))))
#define	CCM_TUPLE_REG(base, tuple)   (*((volatile uint32_t *)(((uint32_t)(base)) + ((uint32_t)(tuple)&0xFFU))))
#define	CCM_TUPLE_SHIFT(tuple)   ((((uint32_t)tuple) >> 8U) & 0x1FU)
#define	CCSR_OFFSET   0x0C
	CCM registers offset. More...
#define	CDCDR_OFFSET   0x30
#define	CLKPN_FREQ   0U
	clock1PN frequency. More...
typedef struct _clock_arm_pll_config	clock_arm_pll_config_t
	PLL configuration for ARM. More...
typedef struct _clock_audio_pll_config	clock_audio_pll_config_t
	PLL configuration for AUDIO and VIDEO. More...
static void	CLOCK_ControlGate (clock_ip_name_t name, clock_gate_value_t value)
	Control the clock gate for specific IP. More...
static void	CLOCK_DisableClock (clock_ip_name_t name)
	Disable the clock for specific IP. More...
typedef enum _clock_div	clock_div_t
	DIV control names for clock div setting. More...
static void	CLOCK_EnableClock (clock_ip_name_t name)
	Enable the clock for specific IP. More...
typedef struct _clock_enet_pll_config	clock_enet_pll_config_t
	PLL configuration for ENET. More...
typedef enum _clock_gate_value	clock_gate_value_t
	Clock gate value. More...
uint32_t	CLOCK_GetAhbFreq (void)
	Gets the AHB clock frequency. More...
#define	CLOCK_GetCoreSysClkFreq   CLOCK_GetCpuClkFreq
static uint32_t	CLOCK_GetCpuClkFreq (void)
	Get the CCM CPU/core/system frequency. More...
static uint32_t	CLOCK_GetDiv (clock_div_t divider)
	Get CCM DIV node value. More...
uint32_t	CLOCK_GetFreq (clock_name_t name)
	Gets the clock frequency for a specific clock name. More...
uint32_t	CLOCK_GetIpgFreq (void)
	Gets the IPG clock frequency. More...
static uint32_t	CLOCK_GetMux (clock_mux_t mux)
	Get CCM MUX value. More...
static uint32_t	CLOCK_GetOscFreq (void)
	Gets the OSC clock frequency. More...
uint32_t	CLOCK_GetPerClkFreq (void)
	Gets the PER clock frequency. More...
uint32_t	CLOCK_GetSemcFreq (void)
	Gets the SEMC clock frequency. More...
typedef enum _clock_ip_name	clock_ip_name_t
	CCM CCGR gate control for each module independently. More...
typedef enum _clock_mode_t	clock_mode_t
	System clock mode. More...
typedef enum _clock_mux	clock_mux_t
	MUX control names for clock mux setting. More...
typedef enum _clock_name	clock_name_t
	Clock name used to get clock frequency. More...
typedef enum _clock_osc	clock_osc_t
	OSC 24M sorce select. More...
typedef enum _clock_pfd	clock_pfd_t
	PLL PFD name. More...
typedef enum _clock_pll	clock_pll_t
	PLL name. More...
static void	CLOCK_SetDiv (clock_div_t divider, uint32_t value)
	Set CCM DIV node to certain value. More...
static void	CLOCK_SetMode (clock_mode_t mode)
	Setting the low power mode that system will enter on next assertion of dsm_request signal. More...
static void	CLOCK_SetMux (clock_mux_t mux, uint32_t value)
	Set CCM MUX node to certain value. More...
#define	CLOCK_SetXtal0Freq   CLOCK_SetXtalFreq
#define	CLOCK_SetXtal32Freq   CLOCK_SetRtcXtalFreq
typedef struct _clock_sys_pll_config	clock_sys_pll_config_t
	PLL configuration for System. More...
typedef enum _clock_usb_phy_src	clock_usb_phy_src_t
	Source of the USB HS PHY. More...
typedef struct _clock_usb_pll_config	clock_usb_pll_config_t
	PLL configuration for USB. More...
typedef enum _clock_usb_src	clock_usb_src_t
	USB clock source definition. More...
typedef struct _clock_video_pll_config	clock_video_pll_config_t
	PLL configuration for AUDIO and VIDEO. More...
#define	CMP_CLOCKS
	Clock ip name array for CMP. More...
#define	CS1CDR_OFFSET   0x28
#define	CS2CDR_OFFSET   0x2C
#define	CSCDR1_OFFSET   0x24
#define	CSCDR2_OFFSET   0x38
#define	CSCDR3_OFFSET   0x3C
#define	CSCMR1_OFFSET   0x1C
#define	CSCMR2_OFFSET   0x20
#define	CSI_CLOCKS
	Clock ip name array for CSI. More...
#define	DCDC_CLOCKS
	Clock ip name array for DCDC. More...
#define	DCP_CLOCKS
	Clock ip name array for DCP. More...
#define	DMAMUX_CLOCKS
	Clock ip name array for DMAMUX_CLOCKS. More...
#define	EDMA_CLOCKS
	Clock ip name array for DMA. More...
#define	ENC_CLOCKS
	Clock ip name array for ENC. More...
#define	ENET_CLOCKS
	Clock ip name array for ENET. More...
#define	EWM_CLOCKS
	Clock ip name array for EWM. More...
#define	FLEXCAN_CLOCKS
	Clock ip name array for FLEXCAN. More...
#define	FLEXCAN_PERIPH_CLOCKS
	Clock ip name array for FLEXCAN Peripheral clock. More...
#define	FLEXIO_CLOCKS
	Clock ip name array for FLEXIO. More...
#define	FLEXRAM_CLOCKS
	Clock ip name array for FLEXRAM. More...
#define	FLEXSPI_CLOCKS
	Clock ip name array for FLEXSPI. More...
#define	FLEXSPI_EXSC_CLOCKS
	Clock ip name array for FLEXSPI EXSC. More...
#define	FSL_CLOCK_DRIVER_VERSION   (MAKE_VERSION(2, 3, 2))
	CLOCK driver version 2.3.2. More...
volatile uint32_t	g_rtcXtalFreq
	External RTC XTAL (32K OSC) clock frequency. More...
volatile uint32_t	g_xtalFreq
	External XTAL (24M OSC/SYSOSC) clock frequency. More...
#define	GPIO_CLOCKS
	Clock ip name array for GPIO. More...
#define	GPT_CLOCKS
	Clock ip name array for GPT. More...
#define	kCLOCK_CoreSysClk   kCLOCK_CpuClk
#define	KPP_CLOCKS
	Clock ip name array for KPP. More...
#define	LCDIF_CLOCKS
	Clock ip name array for LCDIF. More...
#define	LCDIF_PERIPH_CLOCKS
	Clock ip name array for LCDIF PIXEL. More...
#define	LPI2C_CLOCKS
	Clock ip name array for LPI2C. More...
#define	LPSPI_CLOCKS
	Clock ip name array for LPSPI. More...
#define	LPUART_CLOCKS
	Clock ip name array for LPUART. More...
#define	MQS_CLOCKS
	Clock ip name array for MQS. More...
#define	OCRAM_EXSC_CLOCKS
	Clock ip name array for OCRAM EXSC. More...
#define	PIT_CLOCKS
	Clock ip name array for PIT. More...
#define	PLL_ARM_OFFSET   0x00
	CCM Analog registers offset. More...
#define	PLL_AUDIO_OFFSET   0x70
#define	PLL_ENET_OFFSET   0xE0
#define	PLL_SYS_OFFSET   0x30
#define	PLL_USB1_OFFSET   0x10
#define	PLL_USB2_OFFSET   0x20
#define	PLL_VIDEO_OFFSET   0xA0
#define	PWM_CLOCKS
	Clock ip name array for PWM. More...
#define	PXP_CLOCKS
	Clock ip name array for PXP. More...
#define	RTWDOG_CLOCKS
	Clock ip name array for RTWDOG. More...
#define	SAI_CLOCKS
	Clock ip name array for SAI. More...
#define	SEMC_CLOCKS
	Clock ip name array for SEMC. More...
#define	SEMC_EXSC_CLOCKS
	Clock ip name array for SEMC EXSC. More...
#define	SPDIF_CLOCKS
	Clock ip name array for SPDIF. More...
#define	TMR_CLOCKS
	Clock ip name array for QTIMER. More...
#define	TRNG_CLOCKS
	Clock ip name array for TRNG. More...
#define	TSC_CLOCKS
	Clock ip name array for TSC. More...
#define	USDHC_CLOCKS
	Clock ip name array for USDHC. More...
#define	WDOG_CLOCKS
	Clock ip name array for WDOG. More...
#define	XBARA_CLOCKS
	Clock ip name array for XBARA. More...
#define	XBARB_CLOCKS
	Clock ip name array for XBARB. More...