startup_gcc.c
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1 //*****************************************************************************
2 //
3 // startup_gcc.c - Startup code for use with GNU tools.
4 //
5 // Copyright (c) 2009-2012 Texas Instruments Incorporated. All rights reserved.
6 // Software License Agreement
7 //
8 // Redistribution and use in source and binary forms, with or without
9 // modification, are permitted provided that the following conditions
10 // are met:
11 //
12 // Redistributions of source code must retain the above copyright
13 // notice, this list of conditions and the following disclaimer.
14 //
15 // Redistributions in binary form must reproduce the above copyright
16 // notice, this list of conditions and the following disclaimer in the
17 // documentation and/or other materials provided with the
18 // distribution.
19 //
20 // Neither the name of Texas Instruments Incorporated nor the names of
21 // its contributors may be used to endorse or promote products derived
22 // from this software without specific prior written permission.
23 //
24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 //
36 //*****************************************************************************
37 
38 #include <stdint.h>
39 #include "inc/hw_nvic.h"
40 #include "inc/hw_types.h"
41 
42 //*****************************************************************************
43 //
44 // Forward declaration of the default fault handlers.
45 //
46 //*****************************************************************************
47 void ResetISR(void);
48 static void NmiSR(void);
49 static void FaultISR(void);
50 static void IntDefaultHandler(void);
51 
52 //*****************************************************************************
53 //
54 // The entry point for the application.
55 //
56 //*****************************************************************************
57 extern int main(void);
58 
59 //*****************************************************************************
60 // System stack start determined by ldscript, normally highest ram address
61 //*****************************************************************************
62 extern uint32_t _estack;
63 
64 //*****************************************************************************
65 //
66 // The vector table. Note that the proper constructs must be placed on this to
67 // ensure that it ends up at physical address 0x0000.0000.
68 //
69 //*****************************************************************************
70 #ifdef TM4C123GXL
71 __attribute__ ((section(".isr_vector")))
72 void (* const g_pfnVectors[])(void) =
73 {
74  (void (*)(void))((uint32_t)&_estack), // The initial stack pointer, 0x20008000 32K
75  ResetISR, // The reset handler
76  NmiSR, // The NMI handler
77  FaultISR, // The hard fault handler
78  IntDefaultHandler, // The MPU fault handler
79  IntDefaultHandler, // The bus fault handler
80  IntDefaultHandler, // The usage fault handler
81  0, // Reserved
82  0, // Reserved
83  0, // Reserved
84  0, // Reserved
85  IntDefaultHandler, // SVCall handler
86  IntDefaultHandler, // Debug monitor handler
87  0, // Reserved
88  IntDefaultHandler, // The PendSV handler
89  IntDefaultHandler, // The SysTick handler
90  IntDefaultHandler, // GPIO Port A
91  IntDefaultHandler, // GPIO Port B
92  IntDefaultHandler, // GPIO Port C
93  IntDefaultHandler, // GPIO Port D
94  IntDefaultHandler, // GPIO Port E
95  IntDefaultHandler, // UART0 Rx and Tx
96  IntDefaultHandler, // UART1 Rx and Tx
97  IntDefaultHandler, // SSI0 Rx and Tx
98  IntDefaultHandler, // I2C0 Master and Slave
99  IntDefaultHandler, // PWM Fault
100  IntDefaultHandler, // PWM Generator 0
101  IntDefaultHandler, // PWM Generator 1
102  IntDefaultHandler, // PWM Generator 2
103  IntDefaultHandler, // Quadrature Encoder 0
104  IntDefaultHandler, // ADC Sequence 0
105  IntDefaultHandler, // ADC Sequence 1
106  IntDefaultHandler, // ADC Sequence 2
107  IntDefaultHandler, // ADC Sequence 3
108  IntDefaultHandler, // Watchdog timer
109  IntDefaultHandler, // Timer 0 subtimer A
110  IntDefaultHandler, // Timer 0 subtimer B
111  IntDefaultHandler, // Timer 1 subtimer A
112  IntDefaultHandler, // Timer 1 subtimer B
113  IntDefaultHandler, // Timer 2 subtimer A
114  IntDefaultHandler, // Timer 2 subtimer B
115  IntDefaultHandler, // Analog Comparator 0
116  IntDefaultHandler, // Analog Comparator 1
117  IntDefaultHandler, // Analog Comparator 2
118  IntDefaultHandler, // System Control (PLL, OSC, BO)
119  IntDefaultHandler, // FLASH Control
120  IntDefaultHandler, // GPIO Port F
121  IntDefaultHandler, // GPIO Port G
122  IntDefaultHandler, // GPIO Port H
123  IntDefaultHandler, // UART2 Rx and Tx
124  IntDefaultHandler, // SSI1 Rx and Tx
125  IntDefaultHandler, // Timer 3 subtimer A
126  IntDefaultHandler, // Timer 3 subtimer B
127  IntDefaultHandler, // I2C1 Master and Slave
128  IntDefaultHandler, // Quadrature Encoder 1
129  IntDefaultHandler, // CAN0
130  IntDefaultHandler, // CAN1
131  0, // Reserved
132  0, // Reserved
133  IntDefaultHandler, // Hibernate
134  IntDefaultHandler, // USB0
135  IntDefaultHandler, // PWM Generator 3
136  IntDefaultHandler, // uDMA Software Transfer
137  IntDefaultHandler, // uDMA Error
138  IntDefaultHandler, // ADC1 Sequence 0
139  IntDefaultHandler, // ADC1 Sequence 1
140  IntDefaultHandler, // ADC1 Sequence 2
141  IntDefaultHandler, // ADC1 Sequence 3
142  0, // Reserved
143  0, // Reserved
144  IntDefaultHandler, // GPIO Port J
145  IntDefaultHandler, // GPIO Port K
146  IntDefaultHandler, // GPIO Port L
147  IntDefaultHandler, // SSI2 Rx and Tx
148  IntDefaultHandler, // SSI3 Rx and Tx
149  IntDefaultHandler, // UART3 Rx and Tx
150  IntDefaultHandler, // UART4 Rx and Tx
151  IntDefaultHandler, // UART5 Rx and Tx
152  IntDefaultHandler, // UART6 Rx and Tx
153  IntDefaultHandler, // UART7 Rx and Tx
154  0, // Reserved
155  0, // Reserved
156  0, // Reserved
157  0, // Reserved
158  IntDefaultHandler, // I2C2 Master and Slave
159  IntDefaultHandler, // I2C3 Master and Slave
160  IntDefaultHandler, // Timer 4 subtimer A
161  IntDefaultHandler, // Timer 4 subtimer B
162  0, // Reserved
163  0, // Reserved
164  0, // Reserved
165  0, // Reserved
166  0, // Reserved
167  0, // Reserved
168  0, // Reserved
169  0, // Reserved
170  0, // Reserved
171  0, // Reserved
172  0, // Reserved
173  0, // Reserved
174  0, // Reserved
175  0, // Reserved
176  0, // Reserved
177  0, // Reserved
178  0, // Reserved
179  0, // Reserved
180  0, // Reserved
181  0, // Reserved
182  IntDefaultHandler, // Timer 5 subtimer A
183  IntDefaultHandler, // Timer 5 subtimer B
184  IntDefaultHandler, // Wide Timer 0 subtimer A
185  IntDefaultHandler, // Wide Timer 0 subtimer B
186  IntDefaultHandler, // Wide Timer 1 subtimer A
187  IntDefaultHandler, // Wide Timer 1 subtimer B
188  IntDefaultHandler, // Wide Timer 2 subtimer A
189  IntDefaultHandler, // Wide Timer 2 subtimer B
190  IntDefaultHandler, // Wide Timer 3 subtimer A
191  IntDefaultHandler, // Wide Timer 3 subtimer B
192  IntDefaultHandler, // Wide Timer 4 subtimer A
193  IntDefaultHandler, // Wide Timer 4 subtimer B
194  IntDefaultHandler, // Wide Timer 5 subtimer A
195  IntDefaultHandler, // Wide Timer 5 subtimer B
196  IntDefaultHandler, // FPU
197  0, // Reserved
198  0, // Reserved
199  IntDefaultHandler, // I2C4 Master and Slave
200  IntDefaultHandler, // I2C5 Master and Slave
201  IntDefaultHandler, // GPIO Port M
202  IntDefaultHandler, // GPIO Port N
203  IntDefaultHandler, // Quadrature Encoder 2
204  0, // Reserved
205  0, // Reserved
206  IntDefaultHandler, // GPIO Port P (Summary or P0)
207  IntDefaultHandler, // GPIO Port P1
208  IntDefaultHandler, // GPIO Port P2
209  IntDefaultHandler, // GPIO Port P3
210  IntDefaultHandler, // GPIO Port P4
211  IntDefaultHandler, // GPIO Port P5
212  IntDefaultHandler, // GPIO Port P6
213  IntDefaultHandler, // GPIO Port P7
214  IntDefaultHandler, // GPIO Port Q (Summary or Q0)
215  IntDefaultHandler, // GPIO Port Q1
216  IntDefaultHandler, // GPIO Port Q2
217  IntDefaultHandler, // GPIO Port Q3
218  IntDefaultHandler, // GPIO Port Q4
219  IntDefaultHandler, // GPIO Port Q5
220  IntDefaultHandler, // GPIO Port Q6
221  IntDefaultHandler, // GPIO Port Q7
222  IntDefaultHandler, // GPIO Port R
223  IntDefaultHandler, // GPIO Port S
224  IntDefaultHandler, // PWM 1 Generator 0
225  IntDefaultHandler, // PWM 1 Generator 1
226  IntDefaultHandler, // PWM 1 Generator 2
227  IntDefaultHandler, // PWM 1 Generator 3
228  IntDefaultHandler // PWM 1 Fault
229 };
230 #endif
231 #ifdef TM4C1294XL
232 __attribute__ ((section(".isr_vector")))
233 void (* const g_pfnVectors[])(void) =
234 {
235  (void (*)(void))((uint32_t)&_estack), // The initial stack pointer
236  ResetISR, // The reset handler
237  NmiSR, // The NMI handler
238  FaultISR, // The hard fault handler
239  IntDefaultHandler, // The MPU fault handler
240  IntDefaultHandler, // The bus fault handler
241  IntDefaultHandler, // The usage fault handler
242  0, // Reserved
243  0, // Reserved
244  0, // Reserved
245  0, // Reserved
246  IntDefaultHandler, // SVCall handler
247  IntDefaultHandler, // Debug monitor handler
248  0, // Reserved
249  IntDefaultHandler, // The PendSV handler
250  IntDefaultHandler, // The SysTick handler
251  IntDefaultHandler, // GPIO Port A
252  IntDefaultHandler, // GPIO Port B
253  IntDefaultHandler, // GPIO Port C
254  IntDefaultHandler, // GPIO Port D
255  IntDefaultHandler, // GPIO Port E
256  IntDefaultHandler, // UART0 Rx and Tx
257  IntDefaultHandler, // UART1 Rx and Tx
258  IntDefaultHandler, // SSI0 Rx and Tx
259  IntDefaultHandler, // I2C0 Master and Slave
260  IntDefaultHandler, // PWM Fault
261  IntDefaultHandler, // PWM Generator 0
262  IntDefaultHandler, // PWM Generator 1
263  IntDefaultHandler, // PWM Generator 2
264  IntDefaultHandler, // Quadrature Encoder 0
265  IntDefaultHandler, // ADC Sequence 0
266  IntDefaultHandler, // ADC Sequence 1
267  IntDefaultHandler, // ADC Sequence 2
268  IntDefaultHandler, // ADC Sequence 3
269  IntDefaultHandler, // Watchdog timer
270  IntDefaultHandler, // Timer 0 subtimer A
271  IntDefaultHandler, // Timer 0 subtimer B
272  IntDefaultHandler, // Timer 1 subtimer A
273  IntDefaultHandler, // Timer 1 subtimer B
274  IntDefaultHandler, // Timer 2 subtimer A
275  IntDefaultHandler, // Timer 2 subtimer B
276  IntDefaultHandler, // Analog Comparator 0
277  IntDefaultHandler, // Analog Comparator 1
278  IntDefaultHandler, // Analog Comparator 2
279  IntDefaultHandler, // System Control (PLL, OSC, BO)
280  IntDefaultHandler, // FLASH Control
281  IntDefaultHandler, // GPIO Port F
282  IntDefaultHandler, // GPIO Port G
283  IntDefaultHandler, // GPIO Port H
284  IntDefaultHandler, // UART2 Rx and Tx
285  IntDefaultHandler, // SSI1 Rx and Tx
286  IntDefaultHandler, // Timer 3 subtimer A
287  IntDefaultHandler, // Timer 3 subtimer B
288  IntDefaultHandler, // I2C1 Master and Slave
289  IntDefaultHandler, // CAN0
290  IntDefaultHandler, // CAN1
291  IntDefaultHandler, // Ethernet
292  IntDefaultHandler, // Hibernate
293  IntDefaultHandler, // USB0
294  IntDefaultHandler, // PWM Generator 3
295  IntDefaultHandler, // uDMA Software Transfer
296  IntDefaultHandler, // uDMA Error
297  IntDefaultHandler, // ADC1 Sequence 0
298  IntDefaultHandler, // ADC1 Sequence 1
299  IntDefaultHandler, // ADC1 Sequence 2
300  IntDefaultHandler, // ADC1 Sequence 3
301  IntDefaultHandler, // External Bus Interface 0
302  IntDefaultHandler, // GPIO Port J
303  IntDefaultHandler, // GPIO Port K
304  IntDefaultHandler, // GPIO Port L
305  IntDefaultHandler, // SSI2 Rx and Tx
306  IntDefaultHandler, // SSI3 Rx and Tx
307  IntDefaultHandler, // UART3 Rx and Tx
308  IntDefaultHandler, // UART4 Rx and Tx
309  IntDefaultHandler, // UART5 Rx and Tx
310  IntDefaultHandler, // UART6 Rx and Tx
311  IntDefaultHandler, // UART7 Rx and Tx
312  IntDefaultHandler, // I2C2 Master and Slave
313  IntDefaultHandler, // I2C3 Master and Slave
314  IntDefaultHandler, // Timer 4 subtimer A
315  IntDefaultHandler, // Timer 4 subtimer B
316  IntDefaultHandler, // Timer 5 subtimer A
317  IntDefaultHandler, // Timer 5 subtimer B
318  IntDefaultHandler, // FPU
319  0, // Reserved
320  0, // Reserved
321  IntDefaultHandler, // I2C4 Master and Slave
322  IntDefaultHandler, // I2C5 Master and Slave
323  IntDefaultHandler, // GPIO Port M
324  IntDefaultHandler, // GPIO Port N
325  0, // Reserved
326  IntDefaultHandler, // Tamper
327  IntDefaultHandler, // GPIO Port P (Summary or P0)
328  IntDefaultHandler, // GPIO Port P1
329  IntDefaultHandler, // GPIO Port P2
330  IntDefaultHandler, // GPIO Port P3
331  IntDefaultHandler, // GPIO Port P4
332  IntDefaultHandler, // GPIO Port P5
333  IntDefaultHandler, // GPIO Port P6
334  IntDefaultHandler, // GPIO Port P7
335  IntDefaultHandler, // GPIO Port Q (Summary or Q0)
336  IntDefaultHandler, // GPIO Port Q1
337  IntDefaultHandler, // GPIO Port Q2
338  IntDefaultHandler, // GPIO Port Q3
339  IntDefaultHandler, // GPIO Port Q4
340  IntDefaultHandler, // GPIO Port Q5
341  IntDefaultHandler, // GPIO Port Q6
342  IntDefaultHandler, // GPIO Port Q7
343  IntDefaultHandler, // GPIO Port R
344  IntDefaultHandler, // GPIO Port S
345  IntDefaultHandler, // SHA/MD5 0
346  IntDefaultHandler, // AES 0
347  IntDefaultHandler, // DES3DES 0
348  IntDefaultHandler, // LCD Controller 0
349  IntDefaultHandler, // Timer 6 subtimer A
350  IntDefaultHandler, // Timer 6 subtimer B
351  IntDefaultHandler, // Timer 7 subtimer A
352  IntDefaultHandler, // Timer 7 subtimer B
353  IntDefaultHandler, // I2C6 Master and Slave
354  IntDefaultHandler, // I2C7 Master and Slave
355  IntDefaultHandler, // HIM Scan Matrix Keyboard 0
356  IntDefaultHandler, // One Wire 0
357  IntDefaultHandler, // HIM PS/2 0
358  IntDefaultHandler, // HIM LED Sequencer 0
359  IntDefaultHandler, // HIM Consumer IR 0
360  IntDefaultHandler, // I2C8 Master and Slave
361  IntDefaultHandler, // I2C9 Master and Slave
362  IntDefaultHandler // GPIO Port T
363 };
364 #endif
365 
366 //*****************************************************************************
367 //
368 // The following are constructs created by the linker, indicating where the
369 // the "data" and "bss" segments reside in memory. The initializers for the
370 // for the "data" segment resides immediately following the "text" segment.
371 //
372 //*****************************************************************************
373 extern uint32_t _etext;
374 extern uint32_t _data;
375 extern uint32_t _edata;
376 extern uint32_t _bss;
377 extern uint32_t _ebss;
378 extern void (*__preinit_array_start[])(void);
379 extern void (*__preinit_array_end[])(void);
380 extern void (*__init_array_start[])(void);
381 extern void (*__init_array_end[])(void);
382 
383 //*****************************************************************************
384 //
385 // This is the code that gets called when the processor first starts execution
386 // following a reset event. Only the absolutely necessary set is performed,
387 // after which the application supplied entry() routine is called. Any fancy
388 // actions (such as making decisions based on the reset cause register, and
389 // resetting the bits in that register) are left solely in the hands of the
390 // application.
391 //
392 //*****************************************************************************
393 void
394 ResetISR(void)
395 {
396  uint32_t *pui32Src, *pui32Dest;
397  uint32_t i, cnt;
398 
399  //
400  // Copy the data segment initializers from flash to SRAM.
401  //
402  pui32Src = &_etext;
403  for(pui32Dest = &_data; pui32Dest < &_edata; )
404  {
405  *pui32Dest++ = *pui32Src++;
406  }
407 
408  //
409  // Zero fill the bss segment.
410  //
411  __asm(" ldr r0, =_bss\n"
412  " ldr r1, =_ebss\n"
413  " mov r2, #0\n"
414  " .thumb_func\n"
415  "zero_loop:\n"
416  " cmp r0, r1\n"
417  " it lt\n"
418  " strlt r2, [r0], #4\n"
419  " blt zero_loop");
420 
421  //
422  // Enable the floating-point unit. This must be done here to handle the
423  // case where main() uses floating-point and the function prologue saves
424  // floating-point registers (which will fault if floating-point is not
425  // enabled). Any configuration of the floating-point unit using DriverLib
426  // APIs must be done here prior to the floating-point unit being enabled.
427  //
428  HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) &
429  ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) |
430  NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL);
431 
432  //
433  // call any global c++ ctors
434  //
435  cnt = __preinit_array_end - __preinit_array_start;
436  for (i = 0; i < cnt; i++)
437  __preinit_array_start[i]();
438  cnt = __init_array_end - __init_array_start;
439  for (i = 0; i < cnt; i++)
440  __init_array_start[i]();
441 
442  //
443  // Call the application's entry point.
444  //
445  main();
446 }
447 
448 //*****************************************************************************
449 //
450 // This is the code that gets called when the processor receives a NMI. This
451 // simply enters an infinite loop, preserving the system state for examination
452 // by a debugger.
453 //
454 //*****************************************************************************
455 static void
456 NmiSR(void)
457 {
458  //
459  // Enter an infinite loop.
460  //
461  while(1)
462  {
463  }
464 }
465 
466 //*****************************************************************************
467 //
468 // This is the code that gets called when the processor receives a fault
469 // interrupt. This simply enters an infinite loop, preserving the system state
470 // for examination by a debugger.
471 //
472 //*****************************************************************************
473 static void
474 FaultISR(void)
475 {
476  //
477  // Enter an infinite loop.
478  //
479  while(1)
480  {
481  }
482 }
483 
484 //*****************************************************************************
485 //
486 // This is the code that gets called when the processor receives an unexpected
487 // interrupt. This simply enters an infinite loop, preserving the system state
488 // for examination by a debugger.
489 //
490 //*****************************************************************************
491 static void
492 IntDefaultHandler(void)
493 {
494  //
495  // Go into an infinite loop.
496  //
497  while(1)
498  {
499  }
500 }
501 
502 /* syscall stuff */
503 void *__dso_handle = 0;
_data
uint32_t _data
_edata
uint32_t _edata
__init_array_end
void(* __init_array_end[])(void)
main
int main(void)
__preinit_array_end
void(* __preinit_array_end[])(void)
IntDefaultHandler
static void IntDefaultHandler(void)
Definition: startup_gcc.c:492
ResetISR
void ResetISR(void)
Definition: startup_gcc.c:394
_estack
uint32_t _estack
FaultISR
static void FaultISR(void)
Definition: startup_gcc.c:474
__dso_handle
void * __dso_handle
Definition: startup_gcc.c:503
NmiSR
static void NmiSR(void)
Definition: startup_gcc.c:456
__init_array_start
void(* __init_array_start[])(void)
_ebss
uint32_t _ebss
__preinit_array_start
void(* __preinit_array_start[])(void)
_bss
uint32_t _bss
_etext
uint32_t _etext

rosserial_tivac
Author(s): Vitor Matos, Vitor Matos
autogenerated on Wed Mar 2 2022 00:58:19