timer_11xx.h

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/*
 * @brief LPC11xx 16/32-bit Timer/PWM control functions
 *
 * @note
 * Copyright(C) NXP Semiconductors, 2012
 * All rights reserved.
 *
 * @par
 * Software that is described herein is for illustrative purposes only
 * which provides customers with programming information regarding the
 * LPC products.  This software is supplied "AS IS" without any warranties of
 * any kind, and NXP Semiconductors and its licensor disclaim any and
 * all warranties, express or implied, including all implied warranties of
 * merchantability, fitness for a particular purpose and non-infringement of
 * intellectual property rights.  NXP Semiconductors assumes no responsibility
 * or liability for the use of the software, conveys no license or rights under any
 * patent, copyright, mask work right, or any other intellectual property rights in
 * or to any products. NXP Semiconductors reserves the right to make changes
 * in the software without notification. NXP Semiconductors also makes no
 * representation or warranty that such application will be suitable for the
 * specified use without further testing or modification.
 *
 * @par
 * Permission to use, copy, modify, and distribute this software and its
 * documentation is hereby granted, under NXP Semiconductors' and its
 * licensor's relevant copyrights in the software, without fee, provided that it
 * is used in conjunction with NXP Semiconductors microcontrollers.  This
 * copyright, permission, and disclaimer notice must appear in all copies of
 * this code.
 */

#ifndef __TIMER_11XX_H_
#define __TIMER_11XX_H_

#ifdef __cplusplus
extern "C" {
#endif

typedef struct {                                        
        __IO uint32_t IR;                               
        __IO uint32_t TCR;                              
        __IO uint32_t TC;                               
        __IO uint32_t PR;                               
        __IO uint32_t PC;                               
        __IO uint32_t MCR;                              
        __IO uint32_t MR[4];                    
        __IO uint32_t CCR;                              
        __IO uint32_t CR[4];                    
        __IO uint32_t EMR;                              
        __I  uint32_t RESERVED0[12];
        __IO uint32_t CTCR;                             
        __IO uint32_t PWMC;
} LPC_TIMER_T;

#define TIMER_IR_CLR(n)         _BIT(n)

#define TIMER_MATCH_INT(n)      (_BIT((n) & 0x0F))

#define TIMER_CAP_INT(n)        (_BIT((((n) & 0x0F) + 4)))

#define TIMER_ENABLE            ((uint32_t) (1 << 0))

#define TIMER_RESET             ((uint32_t) (1 << 1))

#define TIMER_INT_ON_MATCH(n)   (_BIT(((n) * 3)))

#define TIMER_RESET_ON_MATCH(n) (_BIT((((n) * 3) + 1)))

#define TIMER_STOP_ON_MATCH(n)  (_BIT((((n) * 3) + 2)))

#define TIMER_CAP_RISING(n)     (_BIT(((n) * 3)))

#define TIMER_CAP_FALLING(n)    (_BIT((((n) * 3) + 1)))

#define TIMER_INT_ON_CAP(n)     (_BIT((((n) * 3) + 2)))

void Chip_TIMER_Init(LPC_TIMER_T *pTMR);

void Chip_TIMER_DeInit(LPC_TIMER_T *pTMR);

STATIC INLINE bool Chip_TIMER_MatchPending(LPC_TIMER_T *pTMR, int8_t matchnum)
{
        return (bool) ((pTMR->IR & TIMER_MATCH_INT(matchnum)) != 0);
}

STATIC INLINE bool Chip_TIMER_CapturePending(LPC_TIMER_T *pTMR, int8_t capnum)
{
        return (bool) ((pTMR->IR & TIMER_CAP_INT(capnum)) != 0);
}

STATIC INLINE void Chip_TIMER_ClearMatch(LPC_TIMER_T *pTMR, int8_t matchnum)
{
        pTMR->IR = TIMER_IR_CLR(matchnum);
}

STATIC INLINE void Chip_TIMER_ClearCapture(LPC_TIMER_T *pTMR, int8_t capnum)
{
        pTMR->IR = (0x10 << capnum);
}

STATIC INLINE void Chip_TIMER_Enable(LPC_TIMER_T *pTMR)
{
        pTMR->TCR |= TIMER_ENABLE;
}

STATIC INLINE void Chip_TIMER_Disable(LPC_TIMER_T *pTMR)
{
        pTMR->TCR &= ~TIMER_ENABLE;
}

STATIC INLINE uint32_t Chip_TIMER_ReadCount(LPC_TIMER_T *pTMR)
{
        return pTMR->TC;
}

STATIC INLINE uint32_t Chip_TIMER_ReadPrescale(LPC_TIMER_T *pTMR)
{
        return pTMR->PC;
}

STATIC INLINE void Chip_TIMER_PrescaleSet(LPC_TIMER_T *pTMR, uint32_t prescale)
{
        pTMR->PR = prescale;
}

STATIC INLINE void Chip_TIMER_SetMatch(LPC_TIMER_T *pTMR, int8_t matchnum, uint32_t matchval)
{
        pTMR->MR[matchnum] = matchval;
}

STATIC INLINE uint32_t Chip_TIMER_ReadCapture(LPC_TIMER_T *pTMR, int8_t capnum)
{
        return pTMR->CR[capnum];
}

void Chip_TIMER_Reset(LPC_TIMER_T *pTMR);

STATIC INLINE void Chip_TIMER_MatchEnableInt(LPC_TIMER_T *pTMR, int8_t matchnum)
{
        pTMR->MCR |= TIMER_INT_ON_MATCH(matchnum);
}

STATIC INLINE void Chip_TIMER_MatchDisableInt(LPC_TIMER_T *pTMR, int8_t matchnum)
{
        pTMR->MCR &= ~TIMER_INT_ON_MATCH(matchnum);
}

STATIC INLINE void Chip_TIMER_ResetOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum)
{
        pTMR->MCR |= TIMER_RESET_ON_MATCH(matchnum);
}

STATIC INLINE void Chip_TIMER_ResetOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum)
{
        pTMR->MCR &= ~TIMER_RESET_ON_MATCH(matchnum);
}

STATIC INLINE void Chip_TIMER_StopOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum)
{
        pTMR->MCR |= TIMER_STOP_ON_MATCH(matchnum);
}

STATIC INLINE void Chip_TIMER_StopOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum)
{
        pTMR->MCR &= ~TIMER_STOP_ON_MATCH(matchnum);
}

STATIC INLINE void Chip_TIMER_CaptureRisingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum)
{
        pTMR->CCR |= TIMER_CAP_RISING(capnum);
}

STATIC INLINE void Chip_TIMER_CaptureRisingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum)
{
        pTMR->CCR &= ~TIMER_CAP_RISING(capnum);
}

STATIC INLINE void Chip_TIMER_CaptureFallingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum)
{
        pTMR->CCR |= TIMER_CAP_FALLING(capnum);
}

STATIC INLINE void Chip_TIMER_CaptureFallingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum)
{
        pTMR->CCR &= ~TIMER_CAP_FALLING(capnum);
}

STATIC INLINE void Chip_TIMER_CaptureEnableInt(LPC_TIMER_T *pTMR, int8_t capnum)
{
        pTMR->CCR |= TIMER_INT_ON_CAP(capnum);
}

STATIC INLINE void Chip_TIMER_CaptureDisableInt(LPC_TIMER_T *pTMR, int8_t capnum)
{
        pTMR->CCR &= ~TIMER_INT_ON_CAP(capnum);
}

typedef enum IP_TIMER_PIN_MATCH_STATE {
        TIMER_EXTMATCH_DO_NOTHING = 0,  
        TIMER_EXTMATCH_CLEAR      = 1,  
        TIMER_EXTMATCH_SET        = 2,  
        TIMER_EXTMATCH_TOGGLE     = 3   
} TIMER_PIN_MATCH_STATE_T;

void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_T *pTMR, int8_t initial_state,
                                                                   TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum);

typedef enum IP_TIMER_CAP_SRC_STATE {
        TIMER_CAPSRC_RISING_PCLK  = 0,  
        TIMER_CAPSRC_RISING_CAPN  = 1,  
        TIMER_CAPSRC_FALLING_CAPN = 2,  
        TIMER_CAPSRC_BOTH_CAPN    = 3   
} TIMER_CAP_SRC_STATE_T;

STATIC INLINE void Chip_TIMER_TIMER_SetCountClockSrc(LPC_TIMER_T *pTMR,
                                                                                                         TIMER_CAP_SRC_STATE_T capSrc,
                                                                                                         int8_t capnum)
{
        pTMR->CTCR = (uint32_t) capSrc | ((uint32_t) capnum) << 2;
}

#ifdef __cplusplus
}
#endif

#endif /* __TIMER_11XX_H_ */