sysctl_11xx.h

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/*
 * @brief LPC11XX System Control registers and control functions
 *
 * @note
 * Copyright(C) NXP Semiconductors, 2012
 * All rights reserved.
 *
 * @par
 * Software that is described herein is for illustrative purposes only
 * which provides customers with programming information regarding the
 * LPC products.  This software is supplied "AS IS" without any warranties of
 * any kind, and NXP Semiconductors and its licensor disclaim any and
 * all warranties, express or implied, including all implied warranties of
 * merchantability, fitness for a particular purpose and non-infringement of
 * intellectual property rights.  NXP Semiconductors assumes no responsibility
 * or liability for the use of the software, conveys no license or rights under any
 * patent, copyright, mask work right, or any other intellectual property rights in
 * or to any products. NXP Semiconductors reserves the right to make changes
 * in the software without notification. NXP Semiconductors also makes no
 * representation or warranty that such application will be suitable for the
 * specified use without further testing or modification.
 *
 * @par
 * Permission to use, copy, modify, and distribute this software and its
 * documentation is hereby granted, under NXP Semiconductors' and its
 * licensor's relevant copyrights in the software, without fee, provided that it
 * is used in conjunction with NXP Semiconductors microcontrollers.  This
 * copyright, permission, and disclaimer notice must appear in all copies of
 * this code.
 */

#ifndef __SYSCTL_11XX_H_
#define __SYSCTL_11XX_H_

#ifdef __cplusplus
extern "C" {
#endif

typedef struct {                        
        __IO uint32_t  SYSMEMREMAP;             
        __IO uint32_t  PRESETCTRL;              
        __IO uint32_t  SYSPLLCTRL;              
        __I  uint32_t  SYSPLLSTAT;              
        __IO uint32_t  USBPLLCTRL;              
        __I  uint32_t  USBPLLSTAT;              
        __I  uint32_t  RESERVED1[2];
        __IO uint32_t  SYSOSCCTRL;              
        __IO uint32_t  WDTOSCCTRL;              
        __IO uint32_t  IRCCTRL;                 
        __IO uint32_t  LFOSCCTRL;               
        __IO uint32_t  SYSRSTSTAT;              
        __I  uint32_t  RESERVED2[3];
        __IO uint32_t  SYSPLLCLKSEL;    
        __IO uint32_t  SYSPLLCLKUEN;    
        __IO uint32_t  USBPLLCLKSEL;    
        __IO uint32_t  USBPLLCLKUEN;    
        __I  uint32_t  RESERVED3[8];
        __IO uint32_t  MAINCLKSEL;      
        __IO uint32_t  MAINCLKUEN;      
        __IO uint32_t  SYSAHBCLKDIV;    
        __I  uint32_t  RESERVED4;
        __IO uint32_t  SYSAHBCLKCTRL;   
        __I  uint32_t  RESERVED5[4];
        __IO uint32_t  SSP0CLKDIV;      
        __IO uint32_t  USARTCLKDIV;     
        __IO uint32_t  SSP1CLKDIV;      
        __I  uint32_t  RESERVED6[8];
        __IO uint32_t  USBCLKSEL;       
        __IO uint32_t  USBCLKUEN;       
        __IO uint32_t  USBCLKDIV;       
        __I  uint32_t  RESERVED7;
        __IO uint32_t  WDTCLKSEL;       
        __IO uint32_t  WDTCLKUEN;       
        __IO uint32_t  WDTCLKDIV;       
        __I  uint32_t  RESERVED8;
        __IO uint32_t  CLKOUTSEL;       
        __IO uint32_t  CLKOUTUEN;       
        __IO uint32_t  CLKOUTDIV;       
        __I  uint32_t  RESERVED9[5];
        __I  uint32_t  PIOPORCAP[2];
        __I  uint32_t  RESERVED10[18];
        __IO uint32_t  BODCTRL;         
        __IO uint32_t  SYSTCKCAL;       
        __I  uint32_t  RESERVED11[6];
        __IO uint32_t  IRQLATENCY;      
        __IO uint32_t  NMISRC;          
        __IO uint32_t  PINTSEL[8];      
        __IO uint32_t  USBCLKCTRL;      
        __I  uint32_t  USBCLKST;        
        __I  uint32_t  RESERVED12[24];
        __IO uint32_t  STARTAPRP0;      
        __IO uint32_t  STARTERP0;       
        __IO uint32_t  STARTRSRP0CLR;   
        __IO uint32_t  STARTSRP0;               
        __I  uint32_t  RESERVED13;
        __IO uint32_t  STARTERP1;       
        __I  uint32_t  RESERVED14[6];
        __IO uint32_t  PDSLEEPCFG;      
        __IO uint32_t  PDWAKECFG;       
        __IO uint32_t  PDRUNCFG;        
        __I  uint32_t  RESERVED15[110];
        __I  uint32_t  DEVICEID;        
} LPC_SYSCTL_T;

typedef enum CHIP_SYSCTL_BOOT_MODE_REMAP {
        REMAP_BOOT_LOADER_MODE, 
        REMAP_USER_RAM_MODE,    
        REMAP_USER_FLASH_MODE   
} CHIP_SYSCTL_BOOT_MODE_REMAP_T;

STATIC INLINE void Chip_SYSCTL_Map(CHIP_SYSCTL_BOOT_MODE_REMAP_T remap)
{
        LPC_SYSCTL->SYSMEMREMAP = (uint32_t) remap;
}

typedef enum {
        RESET_SSP0,                     
        RESET_I2C0,                     
        RESET_SSP1,                     
#if !defined(CHIP_LPC1125)
        RESET_CAN0,                     
        RESET_UART0,            
        RESET_TIMER0_16,        
        RESET_TIMER1_16,        
        RESET_TIMER0_32,        
        RESET_TIMER1_32,        
        RESET_ACMP,                     
        RESET_DAC0,                     
        RESET_ADC0                      
#endif
} CHIP_SYSCTL_PERIPH_RESET_T;

STATIC INLINE void Chip_SYSCTL_AssertPeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
{
        LPC_SYSCTL->PRESETCTRL &= ~(1 << (uint32_t) periph);
}

STATIC INLINE void Chip_SYSCTL_DeassertPeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
{
        LPC_SYSCTL->PRESETCTRL |= (1 << (uint32_t) periph);
}

STATIC INLINE void Chip_SYSCTL_PeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
{
        Chip_SYSCTL_AssertPeriphReset(periph);
        Chip_SYSCTL_DeassertPeriphReset(periph);
}

#define SYSCTL_RST_POR    (1 << 0)      
#define SYSCTL_RST_EXTRST (1 << 1)      
#define SYSCTL_RST_WDT    (1 << 2)      
#define SYSCTL_RST_BOD    (1 << 3)      
#define SYSCTL_RST_SYSRST (1 << 4)      
#define SYSCTL_NMISRC_ENABLE   ((uint32_t) 1 << 31)     
STATIC INLINE uint32_t Chip_SYSCTL_GetSystemRSTStatus(void)
{
        return LPC_SYSCTL->SYSRSTSTAT;
}

STATIC INLINE void Chip_SYSCTL_ClearSystemRSTStatus(uint32_t reset)
{
        LPC_SYSCTL->SYSRSTSTAT = reset;
}

STATIC INLINE uint32_t Chip_SYSCTL_GetPORPIOStatus(int index)
{
        return LPC_SYSCTL->PIOPORCAP[index];
}

typedef enum CHIP_SYSCTL_BODRSTLVL {
#if defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) || defined(CHIP_LPC11XXLV) || defined(CHIP_LPC1125)
        SYSCTL_BODRSTLVL_1_46V, 
#else
        SYSCTL_BODRSTLVL_RESERVED1,     
#endif
#if defined(CHIP_LPC11XXLV)
        SYSCTL_BODRSTLVL_RESERVED1,
        SYSCTL_BODRSTLVL_RESERVED2,
        SYSCTL_BODRSTLVL_RESERVED3,
#elif defined(CHIP_LPC11AXX)
        SYSCTL_BODRSTLVL_RESERVED2,
        SYSCTL_BODRSTLVL_2_52V, 
        SYSCTL_BODRSTLVL_2_80V, 
#else
        SYSCTL_BODRSTLVL_2_06V, 
        SYSCTL_BODRSTLVL_2_35V, 
        SYSCTL_BODRSTLVL_2_63V, 
#endif
} CHIP_SYSCTL_BODRSTLVL_T;

typedef enum CHIP_SYSCTL_BODRINTVAL {
        SYSCTL_BODINTVAL_RESERVED1,
#if defined(CHIP_LPC110X) || defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) || defined(CHIP_LPC1125)
        SYSCTL_BODINTVAL_2_22V, 
        SYSCTL_BODINTVAL_2_52V, 
        SYSCTL_BODINTVAL_2_80V, 
#endif
} CHIP_SYSCTL_BODRINTVAL_T;

STATIC INLINE void Chip_SYSCTL_SetBODLevels(CHIP_SYSCTL_BODRSTLVL_T rstlvl,
                                                                                        CHIP_SYSCTL_BODRINTVAL_T intlvl)
{
        LPC_SYSCTL->BODCTRL = ((uint32_t) rstlvl) | (((uint32_t) intlvl) << 2);
}

#if defined(CHIP_LPC11AXX)

STATIC INLINE bool Chip_SYSCTL_GetBODIntStatus(void)
{
        return (bool) ((LPC_SYSCTL->BODCTRL & (1 << 6)) != 0);
}

#else

STATIC INLINE void Chip_SYSCTL_EnableBODReset(void)
{
        LPC_SYSCTL->BODCTRL |= (1 << 4);
}

STATIC INLINE void Chip_SYSCTL_DisableBODReset(void)
{
        LPC_SYSCTL->BODCTRL &= ~(1 << 4);
}

#endif

STATIC INLINE void Chip_SYSCTL_SetSYSTCKCAL(uint32_t sysCalVal)
{
        LPC_SYSCTL->SYSTCKCAL = sysCalVal;
}

#if defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) || defined(CHIP_LPC1125)

STATIC INLINE void Chip_SYSCTL_SetIRQLatency(uint32_t latency)
{
        LPC_SYSCTL->IRQLATENCY = latency;
}

STATIC INLINE uint32_t Chip_SYSCTL_GetIRQLatency(void)
{
        return LPC_SYSCTL->IRQLATENCY;
}

#endif

#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) || defined(CHIP_LPC1125)

STATIC INLINE void Chip_SYSCTL_SetNMISource(uint32_t intsrc)
{
        LPC_SYSCTL->NMISRC = intsrc;
}

STATIC INLINE void Chip_SYSCTL_EnableNMISource(void)
{
        LPC_SYSCTL->NMISRC |= SYSCTL_NMISRC_ENABLE;
}

STATIC INLINE void Chip_SYSCTL_DisableNMISource(void)
{
        LPC_SYSCTL->NMISRC &= ~(SYSCTL_NMISRC_ENABLE);
}

#endif

#if defined(CHIP_LPC11AXX)

STATIC INLINE void Chip_SYSCTL_SetPinInterrupt(uint32_t intno, uint8_t port, uint8_t pin)
{
        LPC_SYSCTL->PINTSEL[intno] = (uint32_t) ((port << 5) | pin);
}

#elif defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)

STATIC INLINE void Chip_SYSCTL_SetPinInterrupt(uint32_t intno, uint8_t port, uint8_t pin)
{
        LPC_SYSCTL->PINTSEL[intno] = (uint32_t) (port * 24 + pin);
}

#endif

#if defined(CHIP_LPC11UXX)

STATIC INLINE void Chip_SYSCTL_SetUSBCLKCTRL(uint32_t ap_clk, uint32_t pol_clk)
{
        LPC_SYSCTL->USBCLKCTRL = ap_clk | (pol_clk << 1);
}

STATIC INLINE bool Chip_SYSCTL_GetUSBCLKStatus(void)
{
        return (bool) ((LPC_SYSCTL->USBCLKST & 0x1) != 0);
}

#endif

#if defined(CHIP_LPC110X) || defined(CHIP_LPC11XXLV) || defined(CHIP_LPC11CXX) || defined(CHIP_LPC1125)

STATIC INLINE void Chip_SYSCTL_SetStartPin(uint32_t pin, uint32_t edge)
{
        if (edge) {
                LPC_SYSCTL->STARTAPRP0 |= (1 << pin);
        }
        else {
                LPC_SYSCTL->STARTAPRP0 &= ~(1 << pin);
        }
}

STATIC INLINE void Chip_SYSCTL_EnableStartPin(uint32_t pin)
{
        LPC_SYSCTL->STARTERP0 |= (1 << pin);
}

STATIC INLINE void Chip_SYSCTL_DisableStartPin(uint32_t pin)
{
        LPC_SYSCTL->STARTERP0 &= ~(1 << pin);
}

STATIC INLINE void Chip_SYSCTL_ResetStartPin(uint32_t pin)
{
        LPC_SYSCTL->STARTRSRP0CLR = (1 << pin);
}

STATIC INLINE bool Chip_SYSCTL_GetStartPinStatus(uint32_t pin)
{
        return (bool) ((LPC_SYSCTL->STARTSRP0 & (1 << pin)) != 0);
}

#endif

#if defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)

STATIC INLINE void Chip_SYSCTL_EnablePINTWakeup(uint32_t pin)
{
        LPC_SYSCTL->STARTERP0 |= (1 << pin);
}

STATIC INLINE void Chip_SYSCTL_DisablePINTWakeup(uint32_t pin)
{
        LPC_SYSCTL->STARTERP0 &= ~(1 << pin);
}

#define SYSCTL_WAKEUP_WWDTINT    (1 << 12)      
#define SYSCTL_WAKEUP_BODINT     (1 << 13)      
#define SYSCTL_WAKEUP_USB_WAKEUP (1 << 19)      
#define SYSCTL_WAKEUP_GPIOINT0   (1 << 20)      
#define SYSCTL_WAKEUP_GPIOINT1   (1 << 21)      
STATIC INLINE void Chip_SYSCTL_EnablePeriphWakeup(uint32_t periphmask)
{
        LPC_SYSCTL->STARTERP1 |= periphmask;
}

STATIC INLINE void Chip_SYSCTL_DisablePeriphWakeup(uint32_t periphmask)
{
        LPC_SYSCTL->STARTERP1 &= ~periphmask;
}

#endif

#if !defined(LPC11AXX)

#define SYSCTL_DEEPSLP_BOD_PD    (1 << 3)       
#define SYSCTL_DEEPSLP_WDTOSC_PD (1 << 6)       
#if defined(CHIP_LPC11XXLV)
#define SYSCTL_DEEPSLP_IRCOUT_PD (1 << 0)       
#define SYSCTL_DEEPSLP_IRC_PD    (1 << 1)       
#endif

void Chip_SYSCTL_SetDeepSleepPD(uint32_t sleepmask);

STATIC INLINE uint32_t Chip_SYSCTL_GetDeepSleepPD(void)
{
        return LPC_SYSCTL->PDSLEEPCFG;
}

#define SYSCTL_SLPWAKE_IRCOUT_PD (1 << 0)       
#define SYSCTL_SLPWAKE_IRC_PD    (1 << 1)       
#define SYSCTL_SLPWAKE_FLASH_PD  (1 << 2)       
#define SYSCTL_SLPWAKE_BOD_PD    (1 << 3)       
#define SYSCTL_SLPWAKE_ADC_PD    (1 << 4)       
#define SYSCTL_SLPWAKE_SYSOSC_PD (1 << 5)       
#define SYSCTL_SLPWAKE_WDTOSC_PD (1 << 6)       
#define SYSCTL_SLPWAKE_SYSPLL_PD (1 << 7)       
#if defined(CHIP_LPC11UXX)
#define SYSCTL_SLPWAKE_USBPLL_PD (1 << 8)       
#define SYSCTL_SLPWAKE_USBPAD_PD (1 << 10)      
#endif

void Chip_SYSCTL_SetWakeup(uint32_t wakeupmask);

STATIC INLINE uint32_t Chip_SYSCTL_GetWakeup(void)
{
        return LPC_SYSCTL->PDWAKECFG;
}

#endif

#define SYSCTL_POWERDOWN_IRCOUT_PD (1 << 0)     
#define SYSCTL_POWERDOWN_IRC_PD    (1 << 1)     
#define SYSCTL_POWERDOWN_FLASH_PD  (1 << 2)     
#if !defined(CHIP_LPC11AXX)
#define SYSCTL_POWERDOWN_BOD_PD    (1 << 3)     
#endif
#define SYSCTL_POWERDOWN_ADC_PD    (1 << 4)     
#define SYSCTL_POWERDOWN_SYSOSC_PD (1 << 5)     
#define SYSCTL_POWERDOWN_WDTOSC_PD (1 << 6)     
#define SYSCTL_POWERDOWN_SYSPLL_PD (1 << 7)     
#if defined(CHIP_LPC11UXX)
#define SYSCTL_POWERDOWN_USBPLL_PD (1 << 8)     
#define SYSCTL_POWERDOWN_USBPAD_PD (1 << 10)
#endif
#if defined(CHIP_LPC11AXX)
#define SYSCTL_POWERDOWN_LFOSC_PD (1 << 13)     
#define SYSCTL_POWERDOWN_DAC_PD   (1 << 14)     
#define SYSCTL_POWERDOWN_TS_PD    (1 << 15)     
#define SYSCTL_POWERDOWN_ACOMP_PD (1 << 16)     
#endif

void Chip_SYSCTL_PowerDown(uint32_t powerdownmask);

void Chip_SYSCTL_PowerUp(uint32_t powerupmask);

STATIC INLINE uint32_t Chip_SYSCTL_GetPowerStates(void)
{
        return LPC_SYSCTL->PDRUNCFG;
}

STATIC INLINE uint32_t Chip_SYSCTL_GetDeviceID(void)
{
        return LPC_SYSCTL->DEVICEID;
}

#ifdef __cplusplus
}
#endif

#endif