adc_11xx.h

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/*
 * @brief  LPC11xx A/D conversion driver (except LPC1125)
 *
 * @note
 * Copyright(C) NXP Semiconductors, 2012
 * All rights reserved.
 *
 * @par
 * Software that is described herein is for illustrative purposes only
 * which provides customers with programming information regarding the
 * LPC products.  This software is supplied "AS IS" without any warranties of
 * any kind, and NXP Semiconductors and its licensor disclaim any and
 * all warranties, express or implied, including all implied warranties of
 * merchantability, fitness for a particular purpose and non-infringement of
 * intellectual property rights.  NXP Semiconductors assumes no responsibility
 * or liability for the use of the software, conveys no license or rights under any
 * patent, copyright, mask work right, or any other intellectual property rights in
 * or to any products. NXP Semiconductors reserves the right to make changes
 * in the software without notification. NXP Semiconductors also makes no
 * representation or warranty that such application will be suitable for the
 * specified use without further testing or modification.
 *
 * @par
 * Permission to use, copy, modify, and distribute this software and its
 * documentation is hereby granted, under NXP Semiconductors' and its
 * licensor's relevant copyrights in the software, without fee, provided that it
 * is used in conjunction with NXP Semiconductors microcontrollers.  This
 * copyright, permission, and disclaimer notice must appear in all copies of
 * this code.
 */

#ifndef __ADC_11XX_H_
#define __ADC_11XX_H_

#if !defined(CHIP_LPC1125)

#ifdef __cplusplus
extern "C" {
#endif

#define ADC_MAX_SAMPLE_RATE 400000

typedef struct {                                        
        __IO uint32_t CR;                               
        __I  uint32_t GDR;                              
        __I  uint32_t RESERVED0;
        __IO uint32_t INTEN;                    
        __I  uint32_t DR[8];                    
        __I  uint32_t STAT;                             
} LPC_ADC_T;

 #define ADC_DR_RESULT(n)        ((((n) >> 6) & 0x3FF)) 
 #define ADC_CR_BITACC(n)        ((((n) & 0x7) << 17))  
#define ADC_DR_DONE(n)          (((n) >> 31))                   
#define ADC_DR_OVERRUN(n)       ((((n) >> 30) & (1UL))) 
#define ADC_CR_CH_SEL(n)        ((1UL << (n)))                  
#define ADC_CR_CLKDIV(n)        ((((n) & 0xFF) << 8))   
#define ADC_CR_BURST            ((1UL << 16))                   
#define ADC_CR_PDN              ((1UL << 21))                   
#define ADC_CR_START_MASK       ((7UL << 24))                   
#define ADC_CR_START_MODE_SEL(SEL)  ((SEL << 24))               
#define ADC_CR_START_NOW        ((1UL << 24))                   
#define ADC_CR_START_CTOUT15    ((2UL << 24))                   
#define ADC_CR_START_CTOUT8     ((3UL << 24))                   
#define ADC_CR_START_ADCTRIG0   ((4UL << 24))                   
#define ADC_CR_START_ADCTRIG1   ((5UL << 24))                   
#define ADC_CR_START_MCOA2      ((6UL << 24))                   
#define ADC_CR_EDGE             ((1UL << 27))                   
#define ADC_SAMPLE_RATE_CONFIG_MASK         (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07))

typedef enum IP_ADC_STATUS {
        ADC_DR_DONE_STAT,       
        ADC_DR_OVERRUN_STAT,
        ADC_DR_ADINT_STAT       
} ADC_STATUS_T;

typedef enum CHIP_ADC_CHANNEL {
        ADC_CH0 = 0,    
        ADC_CH1,                
        ADC_CH2,                
        ADC_CH3,                
        ADC_CH4,                
        ADC_CH5,                
        ADC_CH6,                
        ADC_CH7,                
} ADC_CHANNEL_T;

typedef enum CHIP_ADC_RESOLUTION {
        ADC_10BITS = 0,         
        ADC_9BITS,                      
        ADC_8BITS,                      
        ADC_7BITS,                      
        ADC_6BITS,                      
        ADC_5BITS,                      
        ADC_4BITS,                      
        ADC_3BITS,                      
} ADC_RESOLUTION_T;

typedef enum CHIP_ADC_EDGE_CFG {
        ADC_TRIGGERMODE_RISING = 0,             
        ADC_TRIGGERMODE_FALLING,                
} ADC_EDGE_CFG_T;

typedef enum CHIP_ADC_START_MODE {
        ADC_NO_START = 0,
        ADC_START_NOW,                  
        ADC_START_ON_CTOUT15,   
        ADC_START_ON_CTOUT8,    
        ADC_START_ON_ADCTRIG0,  
        ADC_START_ON_ADCTRIG1,  
        ADC_START_ON_MCOA2              
} ADC_START_MODE_T;

typedef struct {
        uint32_t adcRate;               
        uint8_t  bitsAccuracy;  
        bool     burstMode;             
} ADC_CLOCK_SETUP_T;

void Chip_ADC_Init(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup);

void Chip_ADC_DeInit(LPC_ADC_T *pADC);

Status Chip_ADC_ReadValue(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data);

Status Chip_ADC_ReadByte(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, uint8_t *data);

FlagStatus Chip_ADC_ReadStatus(LPC_ADC_T *pADC, uint8_t channel, uint32_t StatusType);

void Chip_ADC_Int_SetChannelCmd(LPC_ADC_T *pADC, uint8_t channel, FunctionalState NewState);

STATIC INLINE void Chip_ADC_Int_SetGlobalCmd(LPC_ADC_T *pADC, FunctionalState NewState)
{
        Chip_ADC_Int_SetChannelCmd(pADC, 8, NewState);
}

void Chip_ADC_SetStartMode(LPC_ADC_T *pADC, ADC_START_MODE_T mode, ADC_EDGE_CFG_T EdgeOption);

void Chip_ADC_SetSampleRate(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, uint32_t rate);

void Chip_ADC_SetResolution(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, ADC_RESOLUTION_T resolution);

void Chip_ADC_EnableChannel(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, FunctionalState NewState);

void Chip_ADC_SetBurstCmd(LPC_ADC_T *pADC, FunctionalState NewState);

#ifdef __cplusplus
}
#endif

#endif /* !defined(CHIP_LPC1125) */

#endif /* __ADC_11XX_H_ */