utils/cmsis/same70/include/component/hsmci.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_HSMCI_COMPONENT_
36 #define _SAME70_HSMCI_COMPONENT_
37 
38 /* ============================================================================= */
40 /* ============================================================================= */
43 
44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
45 
46 typedef struct {
47  __O uint32_t HSMCI_CR;
48  __IO uint32_t HSMCI_MR;
49  __IO uint32_t HSMCI_DTOR;
50  __IO uint32_t HSMCI_SDCR;
51  __IO uint32_t HSMCI_ARGR;
52  __O uint32_t HSMCI_CMDR;
53  __IO uint32_t HSMCI_BLKR;
54  __IO uint32_t HSMCI_CSTOR;
55  __I uint32_t HSMCI_RSPR[4];
56  __I uint32_t HSMCI_RDR;
57  __O uint32_t HSMCI_TDR;
58  __I uint32_t Reserved1[2];
59  __I uint32_t HSMCI_SR;
60  __O uint32_t HSMCI_IER;
61  __O uint32_t HSMCI_IDR;
62  __I uint32_t HSMCI_IMR;
63  __IO uint32_t HSMCI_DMA;
64  __IO uint32_t HSMCI_CFG;
65  __I uint32_t Reserved2[35];
66  __IO uint32_t HSMCI_WPMR;
67  __I uint32_t HSMCI_WPSR;
68  __I uint32_t Reserved3[4];
69  __I uint32_t HSMCI_VERSION;
70  __I uint32_t Reserved4[64];
71  __IO uint32_t HSMCI_FIFO[256];
72 } Hsmci;
73 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
74 /* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */
75 #define HSMCI_CR_MCIEN (0x1u << 0)
76 #define HSMCI_CR_MCIDIS (0x1u << 1)
77 #define HSMCI_CR_PWSEN (0x1u << 2)
78 #define HSMCI_CR_PWSDIS (0x1u << 3)
79 #define HSMCI_CR_SWRST (0x1u << 7)
80 /* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */
81 #define HSMCI_MR_CLKDIV_Pos 0
82 #define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos)
83 #define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))
84 #define HSMCI_MR_PWSDIV_Pos 8
85 #define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos)
86 #define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))
87 #define HSMCI_MR_RDPROOF (0x1u << 11)
88 #define HSMCI_MR_WRPROOF (0x1u << 12)
89 #define HSMCI_MR_FBYTE (0x1u << 13)
90 #define HSMCI_MR_PADV (0x1u << 14)
91 #define HSMCI_MR_CLKODD (0x1u << 16)
92 /* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */
93 #define HSMCI_DTOR_DTOCYC_Pos 0
94 #define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos)
95 #define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))
96 #define HSMCI_DTOR_DTOMUL_Pos 4
97 #define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos)
98 #define HSMCI_DTOR_DTOMUL(value) ((HSMCI_DTOR_DTOMUL_Msk & ((value) << HSMCI_DTOR_DTOMUL_Pos)))
99 #define HSMCI_DTOR_DTOMUL_1 (0x0u << 4)
100 #define HSMCI_DTOR_DTOMUL_16 (0x1u << 4)
101 #define HSMCI_DTOR_DTOMUL_128 (0x2u << 4)
102 #define HSMCI_DTOR_DTOMUL_256 (0x3u << 4)
103 #define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4)
104 #define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4)
105 #define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4)
106 #define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4)
107 /* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */
108 #define HSMCI_SDCR_SDCSEL_Pos 0
109 #define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos)
110 #define HSMCI_SDCR_SDCSEL(value) ((HSMCI_SDCR_SDCSEL_Msk & ((value) << HSMCI_SDCR_SDCSEL_Pos)))
111 #define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0)
112 #define HSMCI_SDCR_SDCBUS_Pos 6
113 #define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos)
114 #define HSMCI_SDCR_SDCBUS(value) ((HSMCI_SDCR_SDCBUS_Msk & ((value) << HSMCI_SDCR_SDCBUS_Pos)))
115 #define HSMCI_SDCR_SDCBUS_1 (0x0u << 6)
116 #define HSMCI_SDCR_SDCBUS_4 (0x2u << 6)
117 #define HSMCI_SDCR_SDCBUS_8 (0x3u << 6)
118 /* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */
119 #define HSMCI_ARGR_ARG_Pos 0
120 #define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos)
121 #define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))
122 /* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */
123 #define HSMCI_CMDR_CMDNB_Pos 0
124 #define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos)
125 #define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))
126 #define HSMCI_CMDR_RSPTYP_Pos 6
127 #define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos)
128 #define HSMCI_CMDR_RSPTYP(value) ((HSMCI_CMDR_RSPTYP_Msk & ((value) << HSMCI_CMDR_RSPTYP_Pos)))
129 #define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6)
130 #define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6)
131 #define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6)
132 #define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6)
133 #define HSMCI_CMDR_SPCMD_Pos 8
134 #define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos)
135 #define HSMCI_CMDR_SPCMD(value) ((HSMCI_CMDR_SPCMD_Msk & ((value) << HSMCI_CMDR_SPCMD_Pos)))
136 #define HSMCI_CMDR_SPCMD_STD (0x0u << 8)
137 #define HSMCI_CMDR_SPCMD_INIT (0x1u << 8)
138 #define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8)
139 #define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8)
140 #define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8)
141 #define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8)
142 #define HSMCI_CMDR_SPCMD_BOR (0x6u << 8)
143 #define HSMCI_CMDR_SPCMD_EBO (0x7u << 8)
144 #define HSMCI_CMDR_OPDCMD (0x1u << 11)
145 #define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11)
146 #define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11)
147 #define HSMCI_CMDR_MAXLAT (0x1u << 12)
148 #define HSMCI_CMDR_MAXLAT_5 (0x0u << 12)
149 #define HSMCI_CMDR_MAXLAT_64 (0x1u << 12)
150 #define HSMCI_CMDR_TRCMD_Pos 16
151 #define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos)
152 #define HSMCI_CMDR_TRCMD(value) ((HSMCI_CMDR_TRCMD_Msk & ((value) << HSMCI_CMDR_TRCMD_Pos)))
153 #define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16)
154 #define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16)
155 #define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16)
156 #define HSMCI_CMDR_TRDIR (0x1u << 18)
157 #define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18)
158 #define HSMCI_CMDR_TRDIR_READ (0x1u << 18)
159 #define HSMCI_CMDR_TRTYP_Pos 19
160 #define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos)
161 #define HSMCI_CMDR_TRTYP(value) ((HSMCI_CMDR_TRTYP_Msk & ((value) << HSMCI_CMDR_TRTYP_Pos)))
162 #define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19)
163 #define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19)
164 #define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19)
165 #define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19)
166 #define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19)
167 #define HSMCI_CMDR_IOSPCMD_Pos 24
168 #define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos)
169 #define HSMCI_CMDR_IOSPCMD(value) ((HSMCI_CMDR_IOSPCMD_Msk & ((value) << HSMCI_CMDR_IOSPCMD_Pos)))
170 #define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24)
171 #define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24)
172 #define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24)
173 #define HSMCI_CMDR_ATACS (0x1u << 26)
174 #define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26)
175 #define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26)
176 #define HSMCI_CMDR_BOOT_ACK (0x1u << 27)
177 /* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */
178 #define HSMCI_BLKR_BCNT_Pos 0
179 #define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos)
180 #define HSMCI_BLKR_BCNT(value) ((HSMCI_BLKR_BCNT_Msk & ((value) << HSMCI_BLKR_BCNT_Pos)))
181 #define HSMCI_BLKR_BLKLEN_Pos 16
182 #define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos)
183 #define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))
184 /* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */
185 #define HSMCI_CSTOR_CSTOCYC_Pos 0
186 #define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos)
187 #define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))
188 #define HSMCI_CSTOR_CSTOMUL_Pos 4
189 #define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos)
190 #define HSMCI_CSTOR_CSTOMUL(value) ((HSMCI_CSTOR_CSTOMUL_Msk & ((value) << HSMCI_CSTOR_CSTOMUL_Pos)))
191 #define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4)
192 #define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4)
193 #define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4)
194 #define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4)
195 #define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4)
196 #define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4)
197 #define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4)
198 #define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4)
199 /* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */
200 #define HSMCI_RSPR_RSP_Pos 0
201 #define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos)
202 /* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */
203 #define HSMCI_RDR_DATA_Pos 0
204 #define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos)
205 /* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */
206 #define HSMCI_TDR_DATA_Pos 0
207 #define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos)
208 #define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))
209 /* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */
210 #define HSMCI_SR_CMDRDY (0x1u << 0)
211 #define HSMCI_SR_RXRDY (0x1u << 1)
212 #define HSMCI_SR_TXRDY (0x1u << 2)
213 #define HSMCI_SR_BLKE (0x1u << 3)
214 #define HSMCI_SR_DTIP (0x1u << 4)
215 #define HSMCI_SR_NOTBUSY (0x1u << 5)
216 #define HSMCI_SR_SDIOIRQA (0x1u << 8)
217 #define HSMCI_SR_SDIOWAIT (0x1u << 12)
218 #define HSMCI_SR_CSRCV (0x1u << 13)
219 #define HSMCI_SR_RINDE (0x1u << 16)
220 #define HSMCI_SR_RDIRE (0x1u << 17)
221 #define HSMCI_SR_RCRCE (0x1u << 18)
222 #define HSMCI_SR_RENDE (0x1u << 19)
223 #define HSMCI_SR_RTOE (0x1u << 20)
224 #define HSMCI_SR_DCRCE (0x1u << 21)
225 #define HSMCI_SR_DTOE (0x1u << 22)
226 #define HSMCI_SR_CSTOE (0x1u << 23)
227 #define HSMCI_SR_BLKOVRE (0x1u << 24)
228 #define HSMCI_SR_FIFOEMPTY (0x1u << 26)
229 #define HSMCI_SR_XFRDONE (0x1u << 27)
230 #define HSMCI_SR_ACKRCV (0x1u << 28)
231 #define HSMCI_SR_ACKRCVE (0x1u << 29)
232 #define HSMCI_SR_OVRE (0x1u << 30)
233 #define HSMCI_SR_UNRE (0x1u << 31)
234 /* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */
235 #define HSMCI_IER_CMDRDY (0x1u << 0)
236 #define HSMCI_IER_RXRDY (0x1u << 1)
237 #define HSMCI_IER_TXRDY (0x1u << 2)
238 #define HSMCI_IER_BLKE (0x1u << 3)
239 #define HSMCI_IER_DTIP (0x1u << 4)
240 #define HSMCI_IER_NOTBUSY (0x1u << 5)
241 #define HSMCI_IER_SDIOIRQA (0x1u << 8)
242 #define HSMCI_IER_SDIOWAIT (0x1u << 12)
243 #define HSMCI_IER_CSRCV (0x1u << 13)
244 #define HSMCI_IER_RINDE (0x1u << 16)
245 #define HSMCI_IER_RDIRE (0x1u << 17)
246 #define HSMCI_IER_RCRCE (0x1u << 18)
247 #define HSMCI_IER_RENDE (0x1u << 19)
248 #define HSMCI_IER_RTOE (0x1u << 20)
249 #define HSMCI_IER_DCRCE (0x1u << 21)
250 #define HSMCI_IER_DTOE (0x1u << 22)
251 #define HSMCI_IER_CSTOE (0x1u << 23)
252 #define HSMCI_IER_BLKOVRE (0x1u << 24)
253 #define HSMCI_IER_FIFOEMPTY (0x1u << 26)
254 #define HSMCI_IER_XFRDONE (0x1u << 27)
255 #define HSMCI_IER_ACKRCV (0x1u << 28)
256 #define HSMCI_IER_ACKRCVE (0x1u << 29)
257 #define HSMCI_IER_OVRE (0x1u << 30)
258 #define HSMCI_IER_UNRE (0x1u << 31)
259 /* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */
260 #define HSMCI_IDR_CMDRDY (0x1u << 0)
261 #define HSMCI_IDR_RXRDY (0x1u << 1)
262 #define HSMCI_IDR_TXRDY (0x1u << 2)
263 #define HSMCI_IDR_BLKE (0x1u << 3)
264 #define HSMCI_IDR_DTIP (0x1u << 4)
265 #define HSMCI_IDR_NOTBUSY (0x1u << 5)
266 #define HSMCI_IDR_SDIOIRQA (0x1u << 8)
267 #define HSMCI_IDR_SDIOWAIT (0x1u << 12)
268 #define HSMCI_IDR_CSRCV (0x1u << 13)
269 #define HSMCI_IDR_RINDE (0x1u << 16)
270 #define HSMCI_IDR_RDIRE (0x1u << 17)
271 #define HSMCI_IDR_RCRCE (0x1u << 18)
272 #define HSMCI_IDR_RENDE (0x1u << 19)
273 #define HSMCI_IDR_RTOE (0x1u << 20)
274 #define HSMCI_IDR_DCRCE (0x1u << 21)
275 #define HSMCI_IDR_DTOE (0x1u << 22)
276 #define HSMCI_IDR_CSTOE (0x1u << 23)
277 #define HSMCI_IDR_BLKOVRE (0x1u << 24)
278 #define HSMCI_IDR_FIFOEMPTY (0x1u << 26)
279 #define HSMCI_IDR_XFRDONE (0x1u << 27)
280 #define HSMCI_IDR_ACKRCV (0x1u << 28)
281 #define HSMCI_IDR_ACKRCVE (0x1u << 29)
282 #define HSMCI_IDR_OVRE (0x1u << 30)
283 #define HSMCI_IDR_UNRE (0x1u << 31)
284 /* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */
285 #define HSMCI_IMR_CMDRDY (0x1u << 0)
286 #define HSMCI_IMR_RXRDY (0x1u << 1)
287 #define HSMCI_IMR_TXRDY (0x1u << 2)
288 #define HSMCI_IMR_BLKE (0x1u << 3)
289 #define HSMCI_IMR_DTIP (0x1u << 4)
290 #define HSMCI_IMR_NOTBUSY (0x1u << 5)
291 #define HSMCI_IMR_SDIOIRQA (0x1u << 8)
292 #define HSMCI_IMR_SDIOWAIT (0x1u << 12)
293 #define HSMCI_IMR_CSRCV (0x1u << 13)
294 #define HSMCI_IMR_RINDE (0x1u << 16)
295 #define HSMCI_IMR_RDIRE (0x1u << 17)
296 #define HSMCI_IMR_RCRCE (0x1u << 18)
297 #define HSMCI_IMR_RENDE (0x1u << 19)
298 #define HSMCI_IMR_RTOE (0x1u << 20)
299 #define HSMCI_IMR_DCRCE (0x1u << 21)
300 #define HSMCI_IMR_DTOE (0x1u << 22)
301 #define HSMCI_IMR_CSTOE (0x1u << 23)
302 #define HSMCI_IMR_BLKOVRE (0x1u << 24)
303 #define HSMCI_IMR_FIFOEMPTY (0x1u << 26)
304 #define HSMCI_IMR_XFRDONE (0x1u << 27)
305 #define HSMCI_IMR_ACKRCV (0x1u << 28)
306 #define HSMCI_IMR_ACKRCVE (0x1u << 29)
307 #define HSMCI_IMR_OVRE (0x1u << 30)
308 #define HSMCI_IMR_UNRE (0x1u << 31)
309 /* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */
310 #define HSMCI_DMA_CHKSIZE_Pos 4
311 #define HSMCI_DMA_CHKSIZE_Msk (0x7u << HSMCI_DMA_CHKSIZE_Pos)
312 #define HSMCI_DMA_CHKSIZE(value) ((HSMCI_DMA_CHKSIZE_Msk & ((value) << HSMCI_DMA_CHKSIZE_Pos)))
313 #define HSMCI_DMA_CHKSIZE_1 (0x0u << 4)
314 #define HSMCI_DMA_CHKSIZE_2 (0x1u << 4)
315 #define HSMCI_DMA_CHKSIZE_4 (0x2u << 4)
316 #define HSMCI_DMA_CHKSIZE_8 (0x3u << 4)
317 #define HSMCI_DMA_CHKSIZE_16 (0x4u << 4)
318 #define HSMCI_DMA_DMAEN (0x1u << 8)
319 /* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */
320 #define HSMCI_CFG_FIFOMODE (0x1u << 0)
321 #define HSMCI_CFG_FERRCTRL (0x1u << 4)
322 #define HSMCI_CFG_HSMODE (0x1u << 8)
323 #define HSMCI_CFG_LSYNC (0x1u << 12)
324 /* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */
325 #define HSMCI_WPMR_WPEN (0x1u << 0)
326 #define HSMCI_WPMR_WPKEY_Pos 8
327 #define HSMCI_WPMR_WPKEY_Msk (0xffffffu << HSMCI_WPMR_WPKEY_Pos)
328 #define HSMCI_WPMR_WPKEY(value) ((HSMCI_WPMR_WPKEY_Msk & ((value) << HSMCI_WPMR_WPKEY_Pos)))
329 #define HSMCI_WPMR_WPKEY_PASSWD (0x4D4349u << 8)
330 /* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */
331 #define HSMCI_WPSR_WPVS (0x1u << 0)
332 #define HSMCI_WPSR_WPVSRC_Pos 8
333 #define HSMCI_WPSR_WPVSRC_Msk (0xffffu << HSMCI_WPSR_WPVSRC_Pos)
334 /* -------- HSMCI_VERSION : (HSMCI Offset: 0xFC) Version Register -------- */
335 #define HSMCI_VERSION_VERSION_Pos 0
336 #define HSMCI_VERSION_VERSION_Msk (0xfffu << HSMCI_VERSION_VERSION_Pos)
337 #define HSMCI_VERSION_MFN_Pos 16
338 #define HSMCI_VERSION_MFN_Msk (0x7u << HSMCI_VERSION_MFN_Pos)
339 /* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */
340 #define HSMCI_FIFO_DATA_Pos 0
341 #define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos)
342 #define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos)))
343 
347 #endif /* _SAME70_HSMCI_COMPONENT_ */
__O uint32_t HSMCI_IER
(Hsmci Offset: 0x44) Interrupt Enable Register
__IO uint32_t HSMCI_DTOR
(Hsmci Offset: 0x08) Data Timeout Register
#define __IO
Definition: core_cm7.h:266
__IO uint32_t HSMCI_WPMR
(Hsmci Offset: 0xE4) Write Protection Mode Register
#define __O
Definition: core_cm7.h:265
__I uint32_t HSMCI_WPSR
(Hsmci Offset: 0xE8) Write Protection Status Register
__IO uint32_t HSMCI_BLKR
(Hsmci Offset: 0x18) Block Register
__O uint32_t HSMCI_IDR
(Hsmci Offset: 0x48) Interrupt Disable Register
__I uint32_t HSMCI_RDR
(Hsmci Offset: 0x30) Receive Data Register
__IO uint32_t HSMCI_ARGR
(Hsmci Offset: 0x10) Argument Register
__O uint32_t HSMCI_CR
(Hsmci Offset: 0x00) Control Register
__I uint32_t HSMCI_SR
(Hsmci Offset: 0x40) Status Register
__I uint32_t HSMCI_IMR
(Hsmci Offset: 0x4C) Interrupt Mask Register
__IO uint32_t HSMCI_SDCR
(Hsmci Offset: 0x0C) SD/SDIO Card Register
__IO uint32_t HSMCI_CSTOR
(Hsmci Offset: 0x1C) Completion Signal Timeout Register
__IO uint32_t HSMCI_CFG
(Hsmci Offset: 0x54) Configuration Register
__O uint32_t HSMCI_CMDR
(Hsmci Offset: 0x14) Command Register
__IO uint32_t HSMCI_DMA
(Hsmci Offset: 0x50) DMA Configuration Register
__IO uint32_t HSMCI_MR
(Hsmci Offset: 0x04) Mode Register
Hsmci hardware registers.
__O uint32_t HSMCI_TDR
(Hsmci Offset: 0x34) Transmit Data Register
__I uint32_t HSMCI_VERSION
(Hsmci Offset: 0xFC) Version Register
#define __I
Definition: core_cm7.h:263


inertial_sense_ros
Author(s):
autogenerated on Sat Sep 19 2020 03:19:04