Ssc hardware registers. More...

#include <ssc.h>

Public Attributes
__I uint32_t	Reserved1 [2]

__I uint32_t	Reserved2 [2]

__I uint32_t	Reserved3 [37]

__I uint32_t	Reserved4 [4]

__IO uint32_t	SSC_CMR
	(Ssc Offset: 0x4) Clock Mode Register More...

__O uint32_t	SSC_CR
	(Ssc Offset: 0x0) Control Register More...

__O uint32_t	SSC_IDR
	(Ssc Offset: 0x48) Interrupt Disable Register More...

__O uint32_t	SSC_IER
	(Ssc Offset: 0x44) Interrupt Enable Register More...

__I uint32_t	SSC_IMR
	(Ssc Offset: 0x4C) Interrupt Mask Register More...

__IO uint32_t	SSC_RC0R
	(Ssc Offset: 0x38) Receive Compare 0 Register More...

__IO uint32_t	SSC_RC1R
	(Ssc Offset: 0x3C) Receive Compare 1 Register More...

__IO uint32_t	SSC_RCMR
	(Ssc Offset: 0x10) Receive Clock Mode Register More...

__IO uint32_t	SSC_RFMR
	(Ssc Offset: 0x14) Receive Frame Mode Register More...

__I uint32_t	SSC_RHR
	(Ssc Offset: 0x20) Receive Holding Register More...

__I uint32_t	SSC_RSHR
	(Ssc Offset: 0x30) Receive Sync. Holding Register More...

__I uint32_t	SSC_SR
	(Ssc Offset: 0x40) Status Register More...

__IO uint32_t	SSC_TCMR
	(Ssc Offset: 0x18) Transmit Clock Mode Register More...

__IO uint32_t	SSC_TFMR
	(Ssc Offset: 0x1C) Transmit Frame Mode Register More...

__O uint32_t	SSC_THR
	(Ssc Offset: 0x24) Transmit Holding Register More...

__IO uint32_t	SSC_TSHR
	(Ssc Offset: 0x34) Transmit Sync. Holding Register More...

__I uint32_t	SSC_VERSION
	(Ssc Offset: 0xFC) Version Register More...

__IO uint32_t	SSC_WPMR
	(Ssc Offset: 0xE4) Write Protection Mode Register More...

__I uint32_t	SSC_WPSR
	(Ssc Offset: 0xE8) Write Protection Status Register More...

Detailed Description

Ssc hardware registers.

Definition at line 46 of file component/ssc.h.

Member Data Documentation

◆ Reserved1

__I uint32_t Ssc::Reserved1[2]

Definition at line 49 of file component/ssc.h.

◆ Reserved2

__I uint32_t Ssc::Reserved2[2]

Definition at line 56 of file component/ssc.h.

◆ Reserved3

__I uint32_t Ssc::Reserved3[37]

Definition at line 65 of file component/ssc.h.

◆ Reserved4

__I uint32_t Ssc::Reserved4[4]

Definition at line 68 of file component/ssc.h.

◆ SSC_CMR

__IO uint32_t Ssc::SSC_CMR

(Ssc Offset: 0x4) Clock Mode Register

Definition at line 48 of file component/ssc.h.

◆ SSC_CR

__O uint32_t Ssc::SSC_CR

(Ssc Offset: 0x0) Control Register

Definition at line 47 of file component/ssc.h.

◆ SSC_IDR

__O uint32_t Ssc::SSC_IDR

(Ssc Offset: 0x48) Interrupt Disable Register

Definition at line 63 of file component/ssc.h.

◆ SSC_IER

__O uint32_t Ssc::SSC_IER

(Ssc Offset: 0x44) Interrupt Enable Register

Definition at line 62 of file component/ssc.h.

◆ SSC_IMR

__I uint32_t Ssc::SSC_IMR

(Ssc Offset: 0x4C) Interrupt Mask Register

Definition at line 64 of file component/ssc.h.

◆ SSC_RC0R

__IO uint32_t Ssc::SSC_RC0R

(Ssc Offset: 0x38) Receive Compare 0 Register

Definition at line 59 of file component/ssc.h.

◆ SSC_RC1R

__IO uint32_t Ssc::SSC_RC1R

(Ssc Offset: 0x3C) Receive Compare 1 Register

Definition at line 60 of file component/ssc.h.

◆ SSC_RCMR

__IO uint32_t Ssc::SSC_RCMR

(Ssc Offset: 0x10) Receive Clock Mode Register

Definition at line 50 of file component/ssc.h.

◆ SSC_RFMR

__IO uint32_t Ssc::SSC_RFMR

(Ssc Offset: 0x14) Receive Frame Mode Register

Definition at line 51 of file component/ssc.h.

◆ SSC_RHR

__I uint32_t Ssc::SSC_RHR

(Ssc Offset: 0x20) Receive Holding Register

Definition at line 54 of file component/ssc.h.

◆ SSC_RSHR

__I uint32_t Ssc::SSC_RSHR

(Ssc Offset: 0x30) Receive Sync. Holding Register

Definition at line 57 of file component/ssc.h.

◆ SSC_SR

__I uint32_t Ssc::SSC_SR

(Ssc Offset: 0x40) Status Register

Definition at line 61 of file component/ssc.h.

◆ SSC_TCMR

__IO uint32_t Ssc::SSC_TCMR

(Ssc Offset: 0x18) Transmit Clock Mode Register

Definition at line 52 of file component/ssc.h.

◆ SSC_TFMR

__IO uint32_t Ssc::SSC_TFMR

(Ssc Offset: 0x1C) Transmit Frame Mode Register

Definition at line 53 of file component/ssc.h.

◆ SSC_THR

__O uint32_t Ssc::SSC_THR

(Ssc Offset: 0x24) Transmit Holding Register

Definition at line 55 of file component/ssc.h.

◆ SSC_TSHR

__IO uint32_t Ssc::SSC_TSHR

(Ssc Offset: 0x34) Transmit Sync. Holding Register

Definition at line 58 of file component/ssc.h.

◆ SSC_VERSION

__I uint32_t Ssc::SSC_VERSION

(Ssc Offset: 0xFC) Version Register

Definition at line 69 of file component/ssc.h.

◆ SSC_WPMR

__IO uint32_t Ssc::SSC_WPMR

(Ssc Offset: 0xE4) Write Protection Mode Register

Definition at line 66 of file component/ssc.h.

◆ SSC_WPSR

__I uint32_t Ssc::SSC_WPSR

(Ssc Offset: 0xE8) Write Protection Status Register

Definition at line 67 of file component/ssc.h.

The documentation for this struct was generated from the following file:

component/ssc.h

Public Attributes