sd_mmc_protocol.h

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/*
 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
 */

#ifndef SD_MMC_PROTOCOL_H_INCLUDED
#define SD_MMC_PROTOCOL_H_INCLUDED

#include  "compiler.h"

#ifdef __cplusplus
extern "C" {
#endif

// SD/MMC/SDIO default clock frequency for initialization (400KHz)
#define SDMMC_CLOCK_INIT   400000


typedef uint32_t sdmmc_cmd_def_t;

#define SDMMC_CMD_GET_INDEX(cmd) (cmd & 0x3F)
#define SDMMC_RESP_PRESENT      (1lu << 8)
#define SDMMC_RESP_8            (1lu << 9)
#define SDMMC_RESP_32           (1lu << 10)
#define SDMMC_RESP_136          (1lu << 11)
#define SDMMC_RESP_CRC          (1lu << 12)
#define SDMMC_RESP_BUSY         (1lu << 13)
// Open drain for a braodcast command (bc)
// or to enter in inactive state (MCI only)
#define SDMMC_CMD_OPENDRAIN     (1lu << 14)
#define SDMMC_CMD_WRITE         (1lu << 15)
#define SDMMC_CMD_SDIO_BYTE     (1lu << 16)
#define SDMMC_CMD_SDIO_BLOCK    (1lu << 17)
#define SDMMC_CMD_STREAM        (1lu << 18)
#define SDMMC_CMD_SINGLE_BLOCK  (1lu << 19)
#define SDMMC_CMD_MULTI_BLOCK   (1lu << 20)

#define SDMMC_CMD_NO_RESP (0)
#define SDMMC_CMD_R1      (SDMMC_RESP_PRESENT | SDMMC_RESP_CRC)
#define SDMMC_CMD_R1B     (SDMMC_RESP_PRESENT | SDMMC_RESP_CRC | SDMMC_RESP_BUSY)
#define SDMMC_CMD_R2      (SDMMC_RESP_PRESENT | SDMMC_RESP_8 | SDMMC_RESP_136 | SDMMC_RESP_CRC)
#define SDMMC_CMD_R3      (SDMMC_RESP_PRESENT | SDMMC_RESP_32)
#define SDMMC_CMD_R4      (SDMMC_RESP_PRESENT | SDMMC_RESP_32)
#define SDMMC_CMD_R5      (SDMMC_RESP_PRESENT | SDMMC_RESP_8 | SDMMC_RESP_CRC)
#define SDMMC_CMD_R6      (SDMMC_RESP_PRESENT | SDMMC_RESP_CRC)
#define SDMMC_CMD_R7      (SDMMC_RESP_PRESENT | SDMMC_RESP_32 | SDMMC_RESP_CRC)


/*
 * --- Basic commands and read-stream command (class 0 and class 1) ---
 */

#define SDMMC_SPI_CMD0_GO_IDLE_STATE     (0 | SDMMC_CMD_R1)
#define SDMMC_MCI_CMD0_GO_IDLE_STATE     (0 | SDMMC_CMD_NO_RESP | SDMMC_CMD_OPENDRAIN)

#define MMC_SPI_CMD1_SEND_OP_COND        (1 | SDMMC_CMD_R1)
#define MMC_MCI_CMD1_SEND_OP_COND        (1 | SDMMC_CMD_R3 | SDMMC_CMD_OPENDRAIN)

#define SDMMC_CMD2_ALL_SEND_CID          (2 | SDMMC_CMD_R2 | SDMMC_CMD_OPENDRAIN)

#define SD_CMD3_SEND_RELATIVE_ADDR       (3 | SDMMC_CMD_R6 | SDMMC_CMD_OPENDRAIN)

#define MMC_CMD3_SET_RELATIVE_ADDR       (3 | SDMMC_CMD_R1)

#define SDMMC_CMD4_SET_DSR               (4 | SDMMC_CMD_NO_RESP)

#define MMC_CMD5_SLEEP_AWAKE             (5 | SDMMC_CMD_R1B)

#define SDMMC_CMD7_SELECT_CARD_CMD       (7 | SDMMC_CMD_R1B)
#define SDMMC_CMD7_DESELECT_CARD_CMD     (7 | SDMMC_CMD_R1)

#define MMC_CMD8_SEND_EXT_CSD            (8 | SDMMC_CMD_R1 | SDMMC_CMD_SINGLE_BLOCK)

#define SD_CMD8_SEND_IF_COND             (8 | SDMMC_CMD_R7 | SDMMC_CMD_OPENDRAIN)

#define SDMMC_SPI_CMD9_SEND_CSD          (9 | SDMMC_CMD_R1 | SDMMC_CMD_SINGLE_BLOCK)

#define SDMMC_MCI_CMD9_SEND_CSD          (9 | SDMMC_CMD_R2)

#define SDMMC_CMD10_SEND_CID             (10 | SDMMC_CMD_R2)

#define MMC_CMD11_READ_DAT_UNTIL_STOP    (11 | SDMMC_CMD_R1)
/* SD Cmd11 MCI (ac, R1): Voltage switching */
#define SD_CMD11_READ_DAT_UNTIL_STOP     (11 | SDMMC_CMD_R1)

#define SDMMC_CMD12_STOP_TRANSMISSION    (12 | SDMMC_CMD_R1B)

#define SDMMC_SPI_CMD13_SEND_STATUS      (13 | SDMMC_CMD_R2)

#define SDMMC_MCI_CMD13_SEND_STATUS      (13 | SDMMC_CMD_R1)

#define MMC_CMD14_BUSTEST_R              (14 | SDMMC_CMD_R1)

// Note: It is a ac cmd, but it must be send like bc cmd to open drain
#define SDMMC_CMD15_GO_INACTIVE_STATE    (15 | SDMMC_CMD_NO_RESP | SDMMC_CMD_OPENDRAIN)

#define MMC_CMD19_BUSTEST_W              (19 | SDMMC_CMD_R1)

#define SDMMC_SPI_CMD58_READ_OCR         (58 | SDMMC_CMD_R3)

#define SDMMC_SPI_CMD59_CRC_ON_OFF       (59 | SDMMC_CMD_R1)

/*
 * --- Block-oriented read commands (class 2) ---
 */
#define SDMMC_CMD16_SET_BLOCKLEN         (16 | SDMMC_CMD_R1)

#define SDMMC_CMD17_READ_SINGLE_BLOCK    (17 | SDMMC_CMD_R1 | SDMMC_CMD_SINGLE_BLOCK)

#define SDMMC_CMD18_READ_MULTIPLE_BLOCK  (18 | SDMMC_CMD_R1 | SDMMC_CMD_MULTI_BLOCK)

/*
 * --- Sequential write commands (class 3) ---
 */

#define MMC_CMD20_WRITE_DAT_UNTIL_STOP   (20 | SDMMC_CMD_R1)

/*
 * --- Block-oriented write commands (class 4) ---
 */
#define MMC_CMD23_SET_BLOCK_COUNT        (23 | SDMMC_CMD_R1)

#define SDMMC_CMD24_WRITE_BLOCK          (24 | SDMMC_CMD_R1 | SDMMC_CMD_WRITE | SDMMC_CMD_SINGLE_BLOCK)

#define SDMMC_CMD25_WRITE_MULTIPLE_BLOCK (25 | SDMMC_CMD_R1 | SDMMC_CMD_WRITE | SDMMC_CMD_MULTI_BLOCK)

#define MMC_CMD26_PROGRAM_CID            (26 | SDMMC_CMD_R1)

#define SDMMC_CMD27_PROGRAM_CSD          (27 | SDMMC_CMD_R1)

/*
 * --- Erase commands  (class 5) ---
 */
#define SD_CMD32_ERASE_WR_BLK_START      (32 | SDMMC_CMD_R1)

#define SD_CMD33_ERASE_WR_BLK_END        (33 | SDMMC_CMD_R1)

#define MMC_CMD35_ERASE_GROUP_START      (35 | SDMMC_CMD_R1)

#define MMC_CMD36_ERASE_GROUP_END        (36 | SDMMC_CMD_R1)

#define SDMMC_CMD38_ERASE                (38 | SDMMC_CMD_R1B)

/*
 * --- Block Oriented Write Protection Commands (class 6) ---
 */
#define SDMMC_CMD28_SET_WRITE_PROT       (28 | SDMMC_CMD_R1B)

#define SDMMC_CMD29_CLR_WRITE_PROT       (29 | SDMMC_CMD_R1B)

#define SDMMC_CMD30_SEND_WRITE_PROT      (30 | SDMMC_CMD_R1)

/*
 * --- Lock Card (class 7) ---
 */
#define SDMMC_CMD42_LOCK_UNLOCK          (42 | SDMMC_CMD_R1)

/*
 * --- Application-specific commands (class 8) ---
 */
#define SDMMC_CMD55_APP_CMD              (55 | SDMMC_CMD_R1)

#define SDMMC_CMD56_GEN_CMD              (56 | SDMMC_CMD_R1)

#define MMC_CMD6_SWITCH                  (6 | SDMMC_CMD_R1B)

#define SD_CMD6_SWITCH_FUNC              (6 | SDMMC_CMD_R1 | SDMMC_CMD_SINGLE_BLOCK)

#define SD_ACMD6_SET_BUS_WIDTH           (6 | SDMMC_CMD_R1)

#define SD_ACMD13_SD_STATUS              (13 | SDMMC_CMD_R1)

#define SD_ACMD22_SEND_NUM_WR_BLOCKS     (22 | SDMMC_CMD_R1)

#define SD_ACMD23_SET_WR_BLK_ERASE_COUNT (23 | SDMMC_CMD_R1)

#define SD_MCI_ACMD41_SD_SEND_OP_COND    (41 | SDMMC_CMD_R3 | SDMMC_CMD_OPENDRAIN)

#define SD_SPI_ACMD41_SD_SEND_OP_COND    (41 | SDMMC_CMD_R1)

#define SD_ACMD42_SET_CLR_CARD_DETECT    (42 | SDMMC_CMD_R1)

#define SD_ACMD51_SEND_SCR               (51 | SDMMC_CMD_R1 | SDMMC_CMD_SINGLE_BLOCK)

/*
 * --- I/O mode commands (class 9) ---
 */
#define MMC_CMD39_FAST_IO                (39 | SDMMC_CMD_R4)

#define MMC_CMD40_GO_IRQ_STATE           (40 | SDMMC_CMD_R5 | SDMMC_CMD_OPENDRAIN)

#define SDIO_CMD5_SEND_OP_COND           (5 | SDMMC_CMD_R4 | SDMMC_CMD_OPENDRAIN)

#define SDIO_CMD52_IO_RW_DIRECT          (52 | SDMMC_CMD_R5)

#define SDIO_CMD53_IO_R_BYTE_EXTENDED    (53 | SDMMC_CMD_R5 | SDMMC_CMD_SDIO_BYTE)
#define SDIO_CMD53_IO_W_BYTE_EXTENDED    (53 | SDMMC_CMD_R5 | SDMMC_CMD_SDIO_BYTE | SDMMC_CMD_WRITE)
#define SDIO_CMD53_IO_R_BLOCK_EXTENDED   (53 | SDMMC_CMD_R5 | SDMMC_CMD_SDIO_BLOCK)
#define SDIO_CMD53_IO_W_BLOCK_EXTENDED   (53 | SDMMC_CMD_R5 | SDMMC_CMD_SDIO_BLOCK | SDMMC_CMD_WRITE)



#define MMC_CMD6_ACCESS_COMMAND_SET (0lu << 24)
#define MMC_CMD6_ACCESS_SET_BITS    (1lu << 24)
#define MMC_CMD6_ACCESS_CLEAR_BITS  (2lu << 24)
#define MMC_CMD6_ACCESS_WRITE_BYTE  (3lu << 24)
#define MMC_CMD6_INDEX_CMD_SET         (EXT_CSD_CMD_SET_INDEX << 16)
#define MMC_CMD6_INDEX_CMD_SET_REV     (EXT_CSD_CMD_SET_REV_INDEX << 16)
#define MMC_CMD6_INDEX_POWER_CLASS     (EXT_CSD_POWER_CLASS_INDEX << 16)
#define MMC_CMD6_INDEX_HS_TIMING       (EXT_CSD_HS_TIMING_INDEX << 16)
#define MMC_CMD6_INDEX_BUS_WIDTH       (EXT_CSD_BUS_WIDTH_INDEX << 16)
#define MMC_CMD6_INDEX_ERASED_MEM_CONT (EXT_CSD_ERASED_MEM_CONT_INDEX << 16)
#define MMC_CMD6_INDEX_BOOT_CONFIG     (EXT_CSD_BOOT_CONFIG_INDEX << 16)
#define MMC_CMD6_INDEX_BOOT_BUS_WIDTH  (EXT_CSD_BOOT_BUS_WIDTH_INDEX << 16)
#define MMC_CMD6_INDEX_ERASE_GROUP_DEF (EXT_CSD_ERASE_GROUP_DEF_INDEX << 16)
#define MMC_CMD6_VALUE_BUS_WIDTH_1BIT    (0x0lu << 8)
#define MMC_CMD6_VALUE_BUS_WIDTH_4BIT    (0x1lu << 8)
#define MMC_CMD6_VALUE_BUS_WIDTH_8BIT    (0x2lu << 8)
#define MMC_CMD6_VALUE_HS_TIMING_ENABLE  (0x1lu << 8)
#define MMC_CMD6_VALUE_HS_TIMING_DISABLE (0x0lu << 8)

#define SD_CMD6_GRP1_HIGH_SPEED     (0x1lu << 0)
#define SD_CMD6_GRP1_DEFAULT        (0x0lu << 0)
#define SD_CMD6_GRP2_NO_INFLUENCE   (0xFlu << 4)
#define SD_CMD6_GRP2_DEFAULT        (0x0lu << 4)
#define SD_CMD6_GRP3_NO_INFLUENCE   (0xFlu << 8)
#define SD_CMD6_GRP3_DEFAULT        (0x0lu << 8)
#define SD_CMD6_GRP4_NO_INFLUENCE   (0xFlu << 12)
#define SD_CMD6_GRP4_DEFAULT        (0x0lu << 12)
#define SD_CMD6_GRP5_NO_INFLUENCE   (0xFlu << 16)
#define SD_CMD6_GRP5_DEFAULT        (0x0lu << 16)
#define SD_CMD6_GRP6_NO_INFLUENCE   (0xFlu << 20)
#define SD_CMD6_GRP6_DEFAULT        (0x0lu << 20)
#define SD_CMD6_MODE_CHECK          (0lu << 31)
#define SD_CMD6_MODE_SWITCH         (1lu << 31)

#define SD_CMD8_PATTERN       0xAA
#define SD_CMD8_MASK_PATTERN  0xFF
#define SD_CMD8_HIGH_VOLTAGE  0x100
#define SD_CMD8_MASK_VOLTAGE  0xF00

#define SD_ACMD41_HCS   (1lu << 30) 



#define SDIO_R5_COM_CRC_ERROR   (1lu << 15) 
#define SDIO_R5_ILLEGAL_COMMAND (1lu << 14) 
#define SDIO_R5_STATE           (3lu << 12) 
#define SDIO_R5_STATE_DIS       (0lu << 12) 
#define SDIO_R5_STATE_CMD       (1lu << 12) 
#define SDIO_R5_STATE_TRN       (2lu << 12) 
#define SDIO_R5_STATE_RFU       (3lu << 12) 
#define SDIO_R5_ERROR           (1lu << 11) 
#define SDIO_R5_FUNC_NUM        (1lu << 9)  
#define SDIO_R5_OUT_OF_RANGE    (1lu << 8)  
#define SDIO_R5_STATUS_ERR      (SDIO_R5_ERROR | SDIO_R5_FUNC_NUM \
                | SDIO_R5_OUT_OF_RANGE) 


#define SDIO_R6_COM_CRC_ERROR   (1lu << 15)

#define SDIO_R6_ILLEGAL_COMMAND (1lu << 14)

#define SDIO_R6_ERROR           (1lu << 13)

#define SDIO_STATUS_R6  (SDIO_R6_COM_CRC_ERROR \
                | SDIO_R6_ILLEGAL_COMMAND | SDIO_R6_ERROR)

#define SDIO_CMD52_WR_DATA      0
#define SDIO_CMD52_STUFF0       8
#define SDIO_CMD52_REG_ADRR     9
#define SDIO_CMD52_STUFF1       26
#define SDIO_CMD52_RAW_FLAG     27
#define SDIO_CMD52_FUNCTION_NUM 28
#define SDIO_CMD52_RW_FLAG      31
#  define SDIO_CMD52_READ_FLAG    0
#  define SDIO_CMD52_WRITE_FLAG   1


#define SDIO_CMD53_COUNT        0
#define SDIO_CMD53_REG_ADDR     9
#define SDIO_CMD53_OP_CODE      26
#define SDIO_CMD53_BLOCK_MODE   27
#define SDIO_CMD53_FUNCTION_NUM 28
#define SDIO_CMD53_RW_FLAG      31
#  define SDIO_CMD53_READ_FLAG    0
#  define SDIO_CMD53_WRITE_FLAG   1

#define SDIO_CIA  0 
#define SDIO_FN0  0 
#define SDIO_FN1  1 
#define SDIO_FN2  2 
#define SDIO_FN3  3 
#define SDIO_FN4  4 
#define SDIO_FN5  5 
#define SDIO_FN6  6 
#define SDIO_FN7  7 

#define SDIO_CCCR_SDIO_REV    0x00         
#define   SDIO_CCCR_REV_1_00    (0x0lu << 0)  
#define   SDIO_CCCR_REV_1_10    (0x1lu << 0)  
#define   SDIO_CCCR_REV_2_00    (0x2lu << 0)  
#define   SDIO_CCCR_REV_3_00    (0x3lu << 0)  
#define   SDIO_SDIO_REV_1_00    (0x0lu << 4)  
#define   SDIO_SDIO_REV_1_10    (0x1lu << 4)  
#define   SDIO_SDIO_REV_1_20    (0x2lu << 4)  
#define   SDIO_SDIO_REV_2_00    (0x3lu << 4)  
#define   SDIO_SDIO_REV_3_00    (0x4lu << 4)  
#define SDIO_CCCR_SD_REV      0x01         
#define   SDIO_SD_REV_1_01      (0x0lu << 0)  
#define   SDIO_SD_REV_1_10      (0x1lu << 0)  
#define   SDIO_SD_REV_2_00      (0x2lu << 0)  
#define   SDIO_SD_REV_3_00      (0x3lu << 0)  
#define SDIO_CCCR_IOE         0x02         
#define   SDIO_IOE_FN1          (0x1lu << 1)  
#define   SDIO_IOE_FN2          (0x1lu << 2)  
#define   SDIO_IOE_FN3          (0x1lu << 3)  
#define   SDIO_IOE_FN4          (0x1lu << 4)  
#define   SDIO_IOE_FN5          (0x1lu << 5)  
#define   SDIO_IOE_FN6          (0x1lu << 6)  
#define   SDIO_IOE_FN7          (0x1lu << 7)  
#define SDIO_CCCR_IOR         0x03         
#define   SDIO_IOR_FN1          (0x1lu << 1)  
#define   SDIO_IOR_FN2          (0x1lu << 2)  
#define   SDIO_IOR_FN3          (0x1lu << 3)  
#define   SDIO_IOR_FN4          (0x1lu << 4)  
#define   SDIO_IOR_FN5          (0x1lu << 5)  
#define   SDIO_IOR_FN6          (0x1lu << 6)  
#define   SDIO_IOR_FN7          (0x1lu << 7)  
#define SDIO_CCCR_IEN         0x04         
#define   SDIO_IENM             (0x1lu << 0)  
#define   SDIO_IEN_FN1          (0x1lu << 1)  
#define   SDIO_IEN_FN2          (0x1lu << 2)  
#define   SDIO_IEN_FN3          (0x1lu << 3)  
#define   SDIO_IEN_FN4          (0x1lu << 4)  
#define   SDIO_IEN_FN5          (0x1lu << 5)  
#define   SDIO_IEN_FN6          (0x1lu << 6)  
#define   SDIO_IEN_FN7          (0x1lu << 7)  
#define SDIO_CCCR_INT         0x05         
#define   SDIO_INT_FN1          (0x1lu << 1)  
#define   SDIO_INT_FN2          (0x1lu << 2)  
#define   SDIO_INT_FN3          (0x1lu << 3)  
#define   SDIO_INT_FN4          (0x1lu << 4)  
#define   SDIO_INT_FN5          (0x1lu << 5)  
#define   SDIO_INT_FN6          (0x1lu << 6)  
#define   SDIO_INT_FN7          (0x1lu << 7)  
#define SDIO_CCCR_IOA         0x06         
#define   SDIO_AS_FN1           (0x1lu << 0)  
#define   SDIO_AS_FN2           (0x2lu << 0)  
#define   SDIO_AS_FN3           (0x3lu << 0)  
#define   SDIO_AS_FN4           (0x4lu << 0)  
#define   SDIO_AS_FN5           (0x5lu << 0)  
#define   SDIO_AS_FN6           (0x6lu << 0)  
#define   SDIO_AS_FN7           (0x7lu << 0)  
#define   SDIO_RES              (0x1lu << 3)  
#define SDIO_CCCR_BUS_CTRL    0x07         
#define   SDIO_BUSWIDTH_1B      (0x0lu << 0)  
#define   SDIO_BUSWIDTH_4B      (0x2lu << 0)  
#define   SDIO_BUS_ECSI         (0x1lu << 5)

#define   SDIO_BUS_SCSI         (0x1lu << 6)

#define   SDIO_BUS_CD_DISABLE   (0x1lu << 7)
#define SDIO_CCCR_CAP         0x08         
#define   SDIO_CAP_SDC          (0x1lu << 0)

#define   SDIO_CAP_SMB          (0x1lu << 1)

#define   SDIO_CAP_SRW          (0x1lu << 2)

#define   SDIO_CAP_SBS          (0x1lu << 3)

#define   SDIO_CAP_S4MI         (0x1lu << 4)

#define   SDIO_CAP_E4MI         (0x1lu << 5)

#define   SDIO_CAP_LSC          (0x1lu << 6)

#define   SDIO_CAP_4BLS         (0x1lu << 7)

#define SDIO_CCCR_CIS_PTR     0x09

#define SDIO_CCCR_BUS_SUSPEND 0x0C

#define   SDIO_BS               (0x1lu << 0)

#define   SDIO_BR               (0x1lu << 1)
#define SDIO_CCCR_FUN_SEL     0x0D         
#define   SDIO_DF               (0x1lu << 7)  
#define   SDIO_FS_CIA           (0x0lu << 0)  
#define   SDIO_FS_FN1           (0x1lu << 0)  
#define   SDIO_FS_FN2           (0x2lu << 0)  
#define   SDIO_FS_FN3           (0x3lu << 0)  
#define   SDIO_FS_FN4           (0x4lu << 0)  
#define   SDIO_FS_FN5           (0x5lu << 0)  
#define   SDIO_FS_FN6           (0x6lu << 0)  
#define   SDIO_FS_FN7           (0x7lu << 0)  
#define   SDIO_FS_MEM           (0x8lu << 0)  
#define SDIO_CCCR_EXEC        0x0E         
#define   SDIO_EXM              (0x1lu << 0)  
#define   SDIO_EX_FN1           (0x1lu << 1)  
#define   SDIO_EX_FN2           (0x1lu << 2)  
#define   SDIO_EX_FN3           (0x1lu << 3)  
#define   SDIO_EX_FN4           (0x1lu << 4)  
#define   SDIO_EX_FN5           (0x1lu << 5)  
#define   SDIO_EX_FN6           (0x1lu << 6)  
#define   SDIO_EX_FN7           (0x1lu << 7)  
#define SDIO_CCCR_READY       0x0F         
#define   SDIO_RFM              (0x1lu << 0)  
#define   SDIO_RF_FN1           (0x1lu << 1)  
#define   SDIO_RF_FN2           (0x1lu << 2)  
#define   SDIO_RF_FN3           (0x1lu << 3)  
#define   SDIO_RF_FN4           (0x1lu << 4)  
#define   SDIO_RF_FN5           (0x1lu << 5)  
#define   SDIO_RF_FN6           (0x1lu << 6)  
#define   SDIO_RF_FN7           (0x1lu << 7)  
#define SDIO_CCCR_FN0_BLKSIZ  0x10  
#define SDIO_CCCR_POWER       0x12         
#define   SDIO_POWER_SMPC       (0x1lu << 0)  
#define   SDIO_POWER_EMPC       (0x1lu << 1)  
#define SDIO_CCCR_HS          0x13         
#define   SDIO_SHS              (0x1lu << 0)  
#define   SDIO_EHS              (0x1lu << 1)  


#define SDIO_CISTPL_NULL     0x00

#define SDIO_CISTPL_DEVICE   0x01

#define SDIO_CISTPL_CHECKSUM 0x10

#define SDIO_CISTPL_VERS_1   0x15

#define SDIO_CISTPL_ALTSTR   0x16

#define SDIO_CISTPL_MANFID   0x20

#define SDIO_CISTPL_FUNCID   0x21

#define SDIO_CISTPL_FUNCE    0x22

#define SDIO_CISTPL_SDIO_STD 0x91

#define SDIO_CISTPL_SDIO_EXT 0x92

#define SDIO_CISTPL_END      0xFF



static inline uint32_t SDMMC_UNSTUFF_BITS(uint8_t *reg, uint16_t reg_size,
                uint16_t pos, uint8_t size)
{
        uint32_t value;
        value = reg[((reg_size - pos + 7) / 8) - 1] >> (pos % 8);
        if (((pos % 8) + size) > 8) {
                value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 2] << (8 - (pos % 8));
        }
        if (((pos % 8) + size) > 16) {
                value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 3] << (16 - (pos % 8));
        }
        if (((pos % 8) + size) > 16) {
                value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 3] << (16 - (pos % 8));
        }
        value &=  ((uint32_t)1 << size) - 1;
        return value;
}

#define CSD_REG_BIT_SIZE            128 
#define CSD_REG_BSIZE               (CSD_REG_BIT_SIZE / 8) 
#define CSD_STRUCTURE(csd, pos, size) \
                SDMMC_UNSTUFF_BITS(csd, CSD_REG_BIT_SIZE, pos, size)
#define CSD_STRUCTURE_VERSION(csd)  CSD_STRUCTURE(csd, 126, 2)
#define   SD_CSD_VER_1_0            0
#define   SD_CSD_VER_2_0            1
#define   MMC_CSD_VER_1_0           0
#define   MMC_CSD_VER_1_1           1
#define   MMC_CSD_VER_1_2           2
#define CSD_TRAN_SPEED(csd)         CSD_STRUCTURE(csd, 96, 8)
#define SD_CSD_1_0_C_SIZE(csd)      CSD_STRUCTURE(csd, 62, 12)
#define SD_CSD_1_0_C_SIZE_MULT(csd) CSD_STRUCTURE(csd, 47, 3)
#define SD_CSD_1_0_READ_BL_LEN(csd) CSD_STRUCTURE(csd, 80, 4)
#define SD_CSD_2_0_C_SIZE(csd)      CSD_STRUCTURE(csd, 48, 22)
#define MMC_CSD_C_SIZE(csd)         CSD_STRUCTURE(csd, 62, 12)
#define MMC_CSD_C_SIZE_MULT(csd)    CSD_STRUCTURE(csd, 47, 3)
#define MMC_CSD_READ_BL_LEN(csd)    CSD_STRUCTURE(csd, 80, 4)
#define MMC_CSD_SPEC_VERS(csd)      CSD_STRUCTURE(csd, 122, 4)

#define OCR_REG_BSIZE          (32 / 8)    
#define OCR_VDD_170_195        (1lu << 7)
#define OCR_VDD_20_21          (1lu << 8)
#define OCR_VDD_21_22          (1lu << 9)
#define OCR_VDD_22_23          (1lu << 10)
#define OCR_VDD_23_24          (1lu << 11)
#define OCR_VDD_24_25          (1lu << 12)
#define OCR_VDD_25_26          (1lu << 13)
#define OCR_VDD_26_27          (1lu << 14)
#define OCR_VDD_27_28          (1lu << 15)
#define OCR_VDD_28_29          (1lu << 16)
#define OCR_VDD_29_30          (1lu << 17)
#define OCR_VDD_30_31          (1lu << 18)
#define OCR_VDD_31_32          (1lu << 19)
#define OCR_VDD_32_33          (1lu << 20)
#define OCR_VDD_33_34          (1lu << 21)
#define OCR_VDD_34_35          (1lu << 22)
#define OCR_VDD_35_36          (1lu << 23)
#define OCR_SDIO_S18R          (1lu << 24) 
#define OCR_SDIO_MP            (1lu << 27) 
#define OCR_SDIO_NF            (7lu << 28) 
#define OCR_ACCESS_MODE_MASK   (3lu << 29) 
#define OCR_ACCESS_MODE_BYTE   (0lu << 29) 
#define OCR_ACCESS_MODE_SECTOR (2lu << 29) 
#define OCR_CCS                (1lu << 30) 
#define OCR_POWER_UP_BUSY      (1lu << 31) 

#define SD_SCR_REG_BIT_SIZE    64 
#define SD_SCR_REG_BSIZE       (SD_SCR_REG_BIT_SIZE / 8) 
#define SD_SCR_STRUCTURE(scr, pos, size) \
                SDMMC_UNSTUFF_BITS(scr, SD_SCR_REG_BIT_SIZE, pos, size)
#define SD_SCR_SCR_STRUCTURE(scr)            SD_SCR_STRUCTURE(scr, 60, 4)
#define   SD_SCR_SCR_STRUCTURE_1_0             0
#define SD_SCR_SD_SPEC(scr)                  SD_SCR_STRUCTURE(scr, 56, 4)
#define   SD_SCR_SD_SPEC_1_0_01                0
#define   SD_SCR_SD_SPEC_1_10                  1
#define   SD_SCR_SD_SPEC_2_00                  2
#define SD_SCR_DATA_STATUS_AFTER_ERASE(scr)  SD_SCR_STRUCTURE(scr, 55, 1)
#define SD_SCR_SD_SECURITY(scr)              SD_SCR_STRUCTURE(scr, 52, 3)
#define   SD_SCR_SD_SECURITY_NO                0
#define   SD_SCR_SD_SECURITY_NOTUSED           1
#define   SD_SCR_SD_SECURITY_1_01              2
#define   SD_SCR_SD_SECURITY_2_00              3
#define   SD_SCR_SD_SECURITY_3_00              4
#define SD_SCR_SD_BUS_WIDTHS(scr)            SD_SCR_STRUCTURE(scr, 48, 4)
#define   SD_SCR_SD_BUS_WIDTH_1BITS            (1lu << 0)
#define   SD_SCR_SD_BUS_WIDTH_4BITS            (1lu << 2)
#define SD_SCR_SD_SPEC3(scr)                 SD_SCR_STRUCTURE(scr, 47, 1)
#define   SD_SCR_SD_SPEC_3_00                  1
#define SD_SCR_SD_EX_SECURITY(scr)           SD_SCR_STRUCTURE(scr, 43, 4)
#define SD_SCR_SD_CMD_SUPPORT(scr)           SD_SCR_STRUCTURE(scr, 32, 2)

#define SD_SW_STATUS_BIT_SIZE   512 
#define SD_SW_STATUS_BSIZE      (SD_SW_STATUS_BIT_SIZE / 8) 
#define SD_SW_STATUS_STRUCTURE(sd_sw_status, pos, size) \
                SDMMC_UNSTUFF_BITS(sd_sw_status, SD_SW_STATUS_BIT_SIZE, pos, size)
#define SD_SW_STATUS_MAX_CURRENT_CONSUMPTION(status) \
                SD_SW_STATUS_STRUCTURE(status, 496, 16)
#define SD_SW_STATUS_FUN_GRP6_INFO(status) \
                SD_SW_STATUS_STRUCTURE(status, 480, 16)
#define SD_SW_STATUS_FUN_GRP5_INFO(status) \
                SD_SW_STATUS_STRUCTURE(status, 464, 16)
#define SD_SW_STATUS_FUN_GRP4_INFO(status) \
                SD_SW_STATUS_STRUCTURE(status, 448, 16)
#define SD_SW_STATUS_FUN_GRP3_INFO(status) \
                SD_SW_STATUS_STRUCTURE(status, 432, 16)
#define SD_SW_STATUS_FUN_GRP2_INFO(status) \
                SD_SW_STATUS_STRUCTURE(status, 416, 16)
#define SD_SW_STATUS_FUN_GRP1_INFO(status) \
                SD_SW_STATUS_STRUCTURE(status, 400, 16)
#define SD_SW_STATUS_FUN_GRP6_RC(status) \
                SD_SW_STATUS_STRUCTURE(status, 396, 4)
#define SD_SW_STATUS_FUN_GRP5_RC(status) \
                SD_SW_STATUS_STRUCTURE(status, 392, 4)
#define SD_SW_STATUS_FUN_GRP4_RC(status) \
                SD_SW_STATUS_STRUCTURE(status, 388, 4)
#define SD_SW_STATUS_FUN_GRP3_RC(status) \
                SD_SW_STATUS_STRUCTURE(status, 384, 4)
#define SD_SW_STATUS_FUN_GRP2_RC(status) \
                SD_SW_STATUS_STRUCTURE(status, 380, 4)
#define SD_SW_STATUS_FUN_GRP1_RC(status) \
                SD_SW_STATUS_STRUCTURE(status, 376, 4)
#define SD_SW_STATUS_FUN_GRP_RC_ERROR   0xFU
#define SD_SW_STATUS_DATA_STRUCT_VER(status) \
                SD_SW_STATUS_STRUCTURE(status, 368, 8)
#define SD_SW_STATUS_FUN_GRP6_BUSY(status) \
                SD_SW_STATUS_STRUCTURE(status, 352, 16)
#define SD_SW_STATUS_FUN_GRP5_BUSY(status) \
                SD_SW_STATUS_STRUCTURE(status, 336, 16)
#define SD_SW_STATUS_FUN_GRP4_BUSY(status) \
                SD_SW_STATUS_STRUCTURE(status, 320, 16)
#define SD_SW_STATUS_FUN_GRP3_BUSY(status) \
                SD_SW_STATUS_STRUCTURE(status, 304, 16)
#define SD_SW_STATUS_FUN_GRP2_BUSY(status) \
                SD_SW_STATUS_STRUCTURE(status, 288, 16)
#define SD_SW_STATUS_FUN_GRP1_BUSY(status) \
                SD_SW_STATUS_STRUCTURE(status, 272, 16)

#define CARD_STATUS_APP_CMD           (1lu << 5)
#define CARD_STATUS_SWITCH_ERROR      (1lu << 7)
#define CARD_STATUS_READY_FOR_DATA    (1lu << 8)
#define CARD_STATUS_STATE_IDLE        (0lu << 9)
#define CARD_STATUS_STATE_READY       (1lu << 9)
#define CARD_STATUS_STATE_IDENT       (2lu << 9)
#define CARD_STATUS_STATE_STBY        (3lu << 9)
#define CARD_STATUS_STATE_TRAN        (4lu << 9)
#define CARD_STATUS_STATE_DATA        (5lu << 9)
#define CARD_STATUS_STATE_RCV         (6lu << 9)
#define CARD_STATUS_STATE_PRG         (7lu << 9)
#define CARD_STATUS_STATE_DIS         (8lu << 9)
#define CARD_STATUS_STATE             (0xFlu << 9)
#define CARD_STATUS_ERASE_RESET       (1lu << 13)
#define CARD_STATUS_WP_ERASE_SKIP     (1lu << 15)
#define CARD_STATUS_CIDCSD_OVERWRITE  (1lu << 16)
#define CARD_STATUS_OVERRUN           (1lu << 17)
#define CARD_STATUS_UNERRUN           (1lu << 18)
#define CARD_STATUS_ERROR             (1lu << 19)
#define CARD_STATUS_CC_ERROR          (1lu << 20)
#define CARD_STATUS_CARD_ECC_FAILED   (1lu << 21)
#define CARD_STATUS_ILLEGAL_COMMAND   (1lu << 22)
#define CARD_STATUS_COM_CRC_ERROR     (1lu << 23)
#define CARD_STATUS_UNLOCK_FAILED     (1lu << 24)
#define CARD_STATUS_CARD_IS_LOCKED    (1lu << 25)
#define CARD_STATUS_WP_VIOLATION      (1lu << 26)
#define CARD_STATUS_ERASE_PARAM       (1lu << 27)
#define CARD_STATUS_ERASE_SEQ_ERROR   (1lu << 28)
#define CARD_STATUS_BLOCK_LEN_ERROR   (1lu << 29)
#define CARD_STATUS_ADDRESS_MISALIGN  (1lu << 30)
#define CARD_STATUS_ADDR_OUT_OF_RANGE (1lu << 31)

#define CARD_STATUS_ERR_RD_WR    (CARD_STATUS_ADDR_OUT_OF_RANGE \
                | CARD_STATUS_ADDRESS_MISALIGN \
                | CARD_STATUS_BLOCK_LEN_ERROR \
                | CARD_STATUS_WP_VIOLATION \
                | CARD_STATUS_ILLEGAL_COMMAND \
                | CARD_STATUS_CC_ERROR \
                | CARD_STATUS_ERROR)

#define SD_STATUS_BSIZE    (512 / 8)  

#define EXT_CSD_BSIZE    512  
/* Below belongs to Properties Segment */
#define EXT_CSD_S_CMD_SET_INDEX              504lu
#define EXT_CSD_BOOT_INFO_INDEX              228lu
#define EXT_CSD_BOOT_SIZE_MULTI_INDEX        226lu
#define EXT_CSD_ACC_SIZE_INDEX               225lu
#define EXT_CSD_HC_ERASE_GRP_SIZE_INDEX      224lu
#define EXT_CSD_ERASE_TIMEOUT_MULT_INDEX     223lu
#define EXT_CSD_REL_WR_SEC_C_INDEX           222lu
#define EXT_CSD_HC_WP_GRP_SIZE_INDEX         221lu
#define EXT_CSD_S_C_VCC_INDEX                220lu
#define EXT_CSD_S_C_VCCQ_INDEX               219lu
#define EXT_CSD_S_A_TIMEOUT_INDEX            217lu
#define EXT_CSD_SEC_COUNT_INDEX              212lu
#define EXT_CSD_MIN_PERF_W_8_52_INDEX        210lu
#define EXT_CSD_MIN_PERF_R_8_52_INDEX        209lu
#define EXT_CSD_MIN_PERF_W_8_26_4_52_INDEX   208lu
#define EXT_CSD_MIN_PERF_R_8_26_4_52_INDEX   207lu
#define EXT_CSD_MIN_PERF_W_4_26_INDEX        206lu
#define EXT_CSD_MIN_PERF_R_4_26_INDEX        205lu
#define EXT_CSD_PWR_CL_26_360_INDEX          203lu
#define EXT_CSD_PWR_CL_52_360_INDEX          202lu
#define EXT_CSD_PWR_CL_26_195_INDEX          201lu
#define EXT_CSD_PWR_CL_52_195_INDEX          200lu
#define EXT_CSD_CARD_TYPE_INDEX              196lu
/* MMC card type */
#  define MMC_CTYPE_26MHZ    0x1
#  define MMC_CTYPE_52MHZ    0x2
#define EXT_CSD_CSD_STRUCTURE_INDEX          194lu
#define EXT_CSD_EXT_CSD_REV_INDEX            192lu

/* Below belongs to Mode Segment */
#define EXT_CSD_CMD_SET_INDEX                191lu
#define EXT_CSD_CMD_SET_REV_INDEX            189lu
#define EXT_CSD_POWER_CLASS_INDEX            187lu
#define EXT_CSD_HS_TIMING_INDEX              185lu
#define EXT_CSD_BUS_WIDTH_INDEX              183lu
#define EXT_CSD_ERASED_MEM_CONT_INDEX        181lu
#define EXT_CSD_BOOT_CONFIG_INDEX            179lu
#define EXT_CSD_BOOT_BUS_WIDTH_INDEX         177lu
#define EXT_CSD_ERASE_GROUP_DEF_INDEX        175lu



#define SPI_CMD_ENCODE(x) (0x40 | (x & 0x3F))

#define R1_SPI_IDLE                 (1lu << 0)
#define R1_SPI_ERASE_RESET          (1lu << 1)
#define R1_SPI_ILLEGAL_COMMAND      (1lu << 2)
#define R1_SPI_COM_CRC              (1lu << 3)
#define R1_SPI_ERASE_SEQ            (1lu << 4)
#define R1_SPI_ADDRESS              (1lu << 5)
#define R1_SPI_PARAMETER            (1lu << 6)
// R1 bit 7 is always zero, reuse this bit for error
#define R1_SPI_ERROR                (1lu << 7)

#define R2_SPI_CARD_LOCKED      (1lu << 0)
#define R2_SPI_WP_ERASE_SKIP    (1lu << 1)
#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
#define R2_SPI_ERROR            (1lu << 2)
#define R2_SPI_CC_ERROR         (1lu << 3)
#define R2_SPI_CARD_ECC_ERROR   (1lu << 4)
#define R2_SPI_WP_VIOLATION     (1lu << 5)
#define R2_SPI_ERASE_PARAM      (1lu << 6)
#define R2_SPI_OUT_OF_RANGE     (1lu << 7)
#define R2_SPI_CSD_OVERWRITE    R2_SPI_OUT_OF_RANGE

#define SPI_TOKEN_SINGLE_MULTI_READ       0xFE
#define SPI_TOKEN_DATA_ERROR_VALID(token) (((token) & 0xF0) == 0)
#define SPI_TOKEN_DATA_ERROR_ERRORS       (0x0F)
#define SPI_TOKEN_DATA_ERROR_ERROR        (1lu << 0)
#define SPI_TOKEN_DATA_ERROR_CC_ERROR     (1lu << 1)
#define SPI_TOKEN_DATA_ERROR_ECC_ERROR    (1lu << 2)
#define SPI_TOKEN_DATA_ERROR_OUT_RANGE    (1lu << 3)
#define SPI_TOKEN_SINGLE_WRITE            0xFE
#define SPI_TOKEN_MULTI_WRITE             0xFC
#define SPI_TOKEN_STOP_TRAN               0xFD
#define SPI_TOKEN_DATA_RESP_VALID(token)  \
                ((((token) & (1 << 4)) == 0) && (((token) & (1 << 0)) == 1))
#define SPI_TOKEN_DATA_RESP_CODE(token)   ((token) & 0x1E)
#define SPI_TOKEN_DATA_RESP_ACCEPTED      (2lu << 1)
#define SPI_TOKEN_DATA_RESP_CRC_ERR       (5lu << 1)
#define SPI_TOKEN_DATA_RESP_WRITE_ERR     (6lu << 1)



#ifdef __cplusplus
}
#endif

#endif /* SD_MMC_PROTOCOL_H_INCLUDED */