sd_mmc_protocol.h
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1 
33 /*
34  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
35  */
36 
37 #ifndef SD_MMC_PROTOCOL_H_INCLUDED
38 #define SD_MMC_PROTOCOL_H_INCLUDED
39 
40 #include "compiler.h"
41 
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45 
52 // SD/MMC/SDIO default clock frequency for initialization (400KHz)
53 #define SDMMC_CLOCK_INIT 400000
54 
55 
101 typedef uint32_t sdmmc_cmd_def_t;
103 
106 #define SDMMC_CMD_GET_INDEX(cmd) (cmd & 0x3F)
107 #define SDMMC_RESP_PRESENT (1lu << 8)
109 #define SDMMC_RESP_8 (1lu << 9)
111 #define SDMMC_RESP_32 (1lu << 10)
113 #define SDMMC_RESP_136 (1lu << 11)
115 #define SDMMC_RESP_CRC (1lu << 12)
117 #define SDMMC_RESP_BUSY (1lu << 13)
119 // Open drain for a braodcast command (bc)
120 // or to enter in inactive state (MCI only)
121 #define SDMMC_CMD_OPENDRAIN (1lu << 14)
122 #define SDMMC_CMD_WRITE (1lu << 15)
124 #define SDMMC_CMD_SDIO_BYTE (1lu << 16)
126 #define SDMMC_CMD_SDIO_BLOCK (1lu << 17)
128 #define SDMMC_CMD_STREAM (1lu << 18)
130 #define SDMMC_CMD_SINGLE_BLOCK (1lu << 19)
132 #define SDMMC_CMD_MULTI_BLOCK (1lu << 20)
134 
138 #define SDMMC_CMD_NO_RESP (0)
139 #define SDMMC_CMD_R1 (SDMMC_RESP_PRESENT | SDMMC_RESP_CRC)
140 #define SDMMC_CMD_R1B (SDMMC_RESP_PRESENT | SDMMC_RESP_CRC | SDMMC_RESP_BUSY)
141 #define SDMMC_CMD_R2 (SDMMC_RESP_PRESENT | SDMMC_RESP_8 | SDMMC_RESP_136 | SDMMC_RESP_CRC)
142 #define SDMMC_CMD_R3 (SDMMC_RESP_PRESENT | SDMMC_RESP_32)
143 #define SDMMC_CMD_R4 (SDMMC_RESP_PRESENT | SDMMC_RESP_32)
144 #define SDMMC_CMD_R5 (SDMMC_RESP_PRESENT | SDMMC_RESP_8 | SDMMC_RESP_CRC)
145 #define SDMMC_CMD_R6 (SDMMC_RESP_PRESENT | SDMMC_RESP_CRC)
146 #define SDMMC_CMD_R7 (SDMMC_RESP_PRESENT | SDMMC_RESP_32 | SDMMC_RESP_CRC)
147 
155 
156 /*
157  * --- Basic commands and read-stream command (class 0 and class 1) ---
158  */
159 
161 #define SDMMC_SPI_CMD0_GO_IDLE_STATE (0 | SDMMC_CMD_R1)
162 #define SDMMC_MCI_CMD0_GO_IDLE_STATE (0 | SDMMC_CMD_NO_RESP | SDMMC_CMD_OPENDRAIN)
163 
164 #define MMC_SPI_CMD1_SEND_OP_COND (1 | SDMMC_CMD_R1)
165 #define MMC_MCI_CMD1_SEND_OP_COND (1 | SDMMC_CMD_R3 | SDMMC_CMD_OPENDRAIN)
166 
167 #define SDMMC_CMD2_ALL_SEND_CID (2 | SDMMC_CMD_R2 | SDMMC_CMD_OPENDRAIN)
168 
169 #define SD_CMD3_SEND_RELATIVE_ADDR (3 | SDMMC_CMD_R6 | SDMMC_CMD_OPENDRAIN)
170 
171 #define MMC_CMD3_SET_RELATIVE_ADDR (3 | SDMMC_CMD_R1)
172 
173 #define SDMMC_CMD4_SET_DSR (4 | SDMMC_CMD_NO_RESP)
174 
175 #define MMC_CMD5_SLEEP_AWAKE (5 | SDMMC_CMD_R1B)
176 
181 #define SDMMC_CMD7_SELECT_CARD_CMD (7 | SDMMC_CMD_R1B)
182 #define SDMMC_CMD7_DESELECT_CARD_CMD (7 | SDMMC_CMD_R1)
183 
184 #define MMC_CMD8_SEND_EXT_CSD (8 | SDMMC_CMD_R1 | SDMMC_CMD_SINGLE_BLOCK)
185 
186 #define SD_CMD8_SEND_IF_COND (8 | SDMMC_CMD_R7 | SDMMC_CMD_OPENDRAIN)
187 
188 #define SDMMC_SPI_CMD9_SEND_CSD (9 | SDMMC_CMD_R1 | SDMMC_CMD_SINGLE_BLOCK)
189 
190 #define SDMMC_MCI_CMD9_SEND_CSD (9 | SDMMC_CMD_R2)
191 
192 #define SDMMC_CMD10_SEND_CID (10 | SDMMC_CMD_R2)
193 
197 #define MMC_CMD11_READ_DAT_UNTIL_STOP (11 | SDMMC_CMD_R1)
198 /* SD Cmd11 MCI (ac, R1): Voltage switching */
199 #define SD_CMD11_READ_DAT_UNTIL_STOP (11 | SDMMC_CMD_R1)
200 
201 #define SDMMC_CMD12_STOP_TRANSMISSION (12 | SDMMC_CMD_R1B)
202 
203 #define SDMMC_SPI_CMD13_SEND_STATUS (13 | SDMMC_CMD_R2)
204 
205 #define SDMMC_MCI_CMD13_SEND_STATUS (13 | SDMMC_CMD_R1)
206 
207 #define MMC_CMD14_BUSTEST_R (14 | SDMMC_CMD_R1)
208 
209 // Note: It is a ac cmd, but it must be send like bc cmd to open drain
210 #define SDMMC_CMD15_GO_INACTIVE_STATE (15 | SDMMC_CMD_NO_RESP | SDMMC_CMD_OPENDRAIN)
211 
212 #define MMC_CMD19_BUSTEST_W (19 | SDMMC_CMD_R1)
213 
214 #define SDMMC_SPI_CMD58_READ_OCR (58 | SDMMC_CMD_R3)
215 
216 #define SDMMC_SPI_CMD59_CRC_ON_OFF (59 | SDMMC_CMD_R1)
217 
218 /*
219  * --- Block-oriented read commands (class 2) ---
220  */
222 #define SDMMC_CMD16_SET_BLOCKLEN (16 | SDMMC_CMD_R1)
223 
224 #define SDMMC_CMD17_READ_SINGLE_BLOCK (17 | SDMMC_CMD_R1 | SDMMC_CMD_SINGLE_BLOCK)
225 
226 #define SDMMC_CMD18_READ_MULTIPLE_BLOCK (18 | SDMMC_CMD_R1 | SDMMC_CMD_MULTI_BLOCK)
227 
228 /*
229  * --- Sequential write commands (class 3) ---
230  */
231 
236 #define MMC_CMD20_WRITE_DAT_UNTIL_STOP (20 | SDMMC_CMD_R1)
237 
238 /*
239  * --- Block-oriented write commands (class 4) ---
240  */
242 #define MMC_CMD23_SET_BLOCK_COUNT (23 | SDMMC_CMD_R1)
243 
244 #define SDMMC_CMD24_WRITE_BLOCK (24 | SDMMC_CMD_R1 | SDMMC_CMD_WRITE | SDMMC_CMD_SINGLE_BLOCK)
245 
246 #define SDMMC_CMD25_WRITE_MULTIPLE_BLOCK (25 | SDMMC_CMD_R1 | SDMMC_CMD_WRITE | SDMMC_CMD_MULTI_BLOCK)
247 
248 #define MMC_CMD26_PROGRAM_CID (26 | SDMMC_CMD_R1)
249 
250 #define SDMMC_CMD27_PROGRAM_CSD (27 | SDMMC_CMD_R1)
251 
252 /*
253  * --- Erase commands (class 5) ---
254  */
256 #define SD_CMD32_ERASE_WR_BLK_START (32 | SDMMC_CMD_R1)
257 
258 #define SD_CMD33_ERASE_WR_BLK_END (33 | SDMMC_CMD_R1)
259 
260 #define MMC_CMD35_ERASE_GROUP_START (35 | SDMMC_CMD_R1)
261 
262 #define MMC_CMD36_ERASE_GROUP_END (36 | SDMMC_CMD_R1)
263 
264 #define SDMMC_CMD38_ERASE (38 | SDMMC_CMD_R1B)
265 
266 /*
267  * --- Block Oriented Write Protection Commands (class 6) ---
268  */
270 #define SDMMC_CMD28_SET_WRITE_PROT (28 | SDMMC_CMD_R1B)
271 
272 #define SDMMC_CMD29_CLR_WRITE_PROT (29 | SDMMC_CMD_R1B)
273 
274 #define SDMMC_CMD30_SEND_WRITE_PROT (30 | SDMMC_CMD_R1)
275 
276 /*
277  * --- Lock Card (class 7) ---
278  */
280 #define SDMMC_CMD42_LOCK_UNLOCK (42 | SDMMC_CMD_R1)
281 
282 /*
283  * --- Application-specific commands (class 8) ---
284  */
289 #define SDMMC_CMD55_APP_CMD (55 | SDMMC_CMD_R1)
290 
294 #define SDMMC_CMD56_GEN_CMD (56 | SDMMC_CMD_R1)
295 
300 #define MMC_CMD6_SWITCH (6 | SDMMC_CMD_R1B)
301 
305 #define SD_CMD6_SWITCH_FUNC (6 | SDMMC_CMD_R1 | SDMMC_CMD_SINGLE_BLOCK)
306 
307 #define SD_ACMD6_SET_BUS_WIDTH (6 | SDMMC_CMD_R1)
308 
309 #define SD_ACMD13_SD_STATUS (13 | SDMMC_CMD_R1)
310 
314 #define SD_ACMD22_SEND_NUM_WR_BLOCKS (22 | SDMMC_CMD_R1)
315 
319 #define SD_ACMD23_SET_WR_BLK_ERASE_COUNT (23 | SDMMC_CMD_R1)
320 
325 #define SD_MCI_ACMD41_SD_SEND_OP_COND (41 | SDMMC_CMD_R3 | SDMMC_CMD_OPENDRAIN)
326 
330 #define SD_SPI_ACMD41_SD_SEND_OP_COND (41 | SDMMC_CMD_R1)
331 
335 #define SD_ACMD42_SET_CLR_CARD_DETECT (42 | SDMMC_CMD_R1)
336 
337 #define SD_ACMD51_SEND_SCR (51 | SDMMC_CMD_R1 | SDMMC_CMD_SINGLE_BLOCK)
338 
339 /*
340  * --- I/O mode commands (class 9) ---
341  */
343 #define MMC_CMD39_FAST_IO (39 | SDMMC_CMD_R4)
344 
345 #define MMC_CMD40_GO_IRQ_STATE (40 | SDMMC_CMD_R5 | SDMMC_CMD_OPENDRAIN)
346 
347 #define SDIO_CMD5_SEND_OP_COND (5 | SDMMC_CMD_R4 | SDMMC_CMD_OPENDRAIN)
348 
349 #define SDIO_CMD52_IO_RW_DIRECT (52 | SDMMC_CMD_R5)
350 
351 #define SDIO_CMD53_IO_R_BYTE_EXTENDED (53 | SDMMC_CMD_R5 | SDMMC_CMD_SDIO_BYTE)
352 #define SDIO_CMD53_IO_W_BYTE_EXTENDED (53 | SDMMC_CMD_R5 | SDMMC_CMD_SDIO_BYTE | SDMMC_CMD_WRITE)
353 #define SDIO_CMD53_IO_R_BLOCK_EXTENDED (53 | SDMMC_CMD_R5 | SDMMC_CMD_SDIO_BLOCK)
354 #define SDIO_CMD53_IO_W_BLOCK_EXTENDED (53 | SDMMC_CMD_R5 | SDMMC_CMD_SDIO_BLOCK | SDMMC_CMD_WRITE)
355 
358 
361 
366 #define MMC_CMD6_ACCESS_COMMAND_SET (0lu << 24)
367 #define MMC_CMD6_ACCESS_SET_BITS (1lu << 24)
368 #define MMC_CMD6_ACCESS_CLEAR_BITS (2lu << 24)
369 #define MMC_CMD6_ACCESS_WRITE_BYTE (3lu << 24)
370 #define MMC_CMD6_INDEX_CMD_SET (EXT_CSD_CMD_SET_INDEX << 16)
372 #define MMC_CMD6_INDEX_CMD_SET_REV (EXT_CSD_CMD_SET_REV_INDEX << 16)
373 #define MMC_CMD6_INDEX_POWER_CLASS (EXT_CSD_POWER_CLASS_INDEX << 16)
374 #define MMC_CMD6_INDEX_HS_TIMING (EXT_CSD_HS_TIMING_INDEX << 16)
375 #define MMC_CMD6_INDEX_BUS_WIDTH (EXT_CSD_BUS_WIDTH_INDEX << 16)
376 #define MMC_CMD6_INDEX_ERASED_MEM_CONT (EXT_CSD_ERASED_MEM_CONT_INDEX << 16)
377 #define MMC_CMD6_INDEX_BOOT_CONFIG (EXT_CSD_BOOT_CONFIG_INDEX << 16)
378 #define MMC_CMD6_INDEX_BOOT_BUS_WIDTH (EXT_CSD_BOOT_BUS_WIDTH_INDEX << 16)
379 #define MMC_CMD6_INDEX_ERASE_GROUP_DEF (EXT_CSD_ERASE_GROUP_DEF_INDEX << 16)
380 #define MMC_CMD6_VALUE_BUS_WIDTH_1BIT (0x0lu << 8)
382 #define MMC_CMD6_VALUE_BUS_WIDTH_4BIT (0x1lu << 8)
383 #define MMC_CMD6_VALUE_BUS_WIDTH_8BIT (0x2lu << 8)
384 #define MMC_CMD6_VALUE_HS_TIMING_ENABLE (0x1lu << 8)
385 #define MMC_CMD6_VALUE_HS_TIMING_DISABLE (0x0lu << 8)
386 
393 #define SD_CMD6_GRP1_HIGH_SPEED (0x1lu << 0)
394 #define SD_CMD6_GRP1_DEFAULT (0x0lu << 0)
395 #define SD_CMD6_GRP2_NO_INFLUENCE (0xFlu << 4)
397 #define SD_CMD6_GRP2_DEFAULT (0x0lu << 4)
398 #define SD_CMD6_GRP3_NO_INFLUENCE (0xFlu << 8)
400 #define SD_CMD6_GRP3_DEFAULT (0x0lu << 8)
401 #define SD_CMD6_GRP4_NO_INFLUENCE (0xFlu << 12)
403 #define SD_CMD6_GRP4_DEFAULT (0x0lu << 12)
404 #define SD_CMD6_GRP5_NO_INFLUENCE (0xFlu << 16)
406 #define SD_CMD6_GRP5_DEFAULT (0x0lu << 16)
407 #define SD_CMD6_GRP6_NO_INFLUENCE (0xFlu << 20)
409 #define SD_CMD6_GRP6_DEFAULT (0x0lu << 20)
410 #define SD_CMD6_MODE_CHECK (0lu << 31)
413 #define SD_CMD6_MODE_SWITCH (1lu << 31)
414 
418 #define SD_CMD8_PATTERN 0xAA
419 #define SD_CMD8_MASK_PATTERN 0xFF
420 #define SD_CMD8_HIGH_VOLTAGE 0x100
421 #define SD_CMD8_MASK_VOLTAGE 0xF00
422 
426 #define SD_ACMD41_HCS (1lu << 30)
427 
430 
433 
436 #define SDIO_R5_COM_CRC_ERROR (1lu << 15)
437 #define SDIO_R5_ILLEGAL_COMMAND (1lu << 14)
438 #define SDIO_R5_STATE (3lu << 12)
439 #define SDIO_R5_STATE_DIS (0lu << 12)
440 #define SDIO_R5_STATE_CMD (1lu << 12)
441 #define SDIO_R5_STATE_TRN (2lu << 12)
442 #define SDIO_R5_STATE_RFU (3lu << 12)
443 #define SDIO_R5_ERROR (1lu << 11)
444 #define SDIO_R5_FUNC_NUM (1lu << 9)
445 #define SDIO_R5_OUT_OF_RANGE (1lu << 8)
446 #define SDIO_R5_STATUS_ERR (SDIO_R5_ERROR | SDIO_R5_FUNC_NUM \
447  | SDIO_R5_OUT_OF_RANGE)
448 
450 
453 #define SDIO_R6_COM_CRC_ERROR (1lu << 15)
454 
455 #define SDIO_R6_ILLEGAL_COMMAND (1lu << 14)
456 
457 #define SDIO_R6_ERROR (1lu << 13)
458 
459 #define SDIO_STATUS_R6 (SDIO_R6_COM_CRC_ERROR \
460  | SDIO_R6_ILLEGAL_COMMAND | SDIO_R6_ERROR)
461 
466 #define SDIO_CMD52_WR_DATA 0
467 #define SDIO_CMD52_STUFF0 8
469 #define SDIO_CMD52_REG_ADRR 9
471 #define SDIO_CMD52_STUFF1 26
473 #define SDIO_CMD52_RAW_FLAG 27
475 #define SDIO_CMD52_FUNCTION_NUM 28
477 #define SDIO_CMD52_RW_FLAG 31
479 # define SDIO_CMD52_READ_FLAG 0
480 # define SDIO_CMD52_WRITE_FLAG 1
481 
485 
491 #define SDIO_CMD53_COUNT 0
492 #define SDIO_CMD53_REG_ADDR 9
494 #define SDIO_CMD53_OP_CODE 26
496 #define SDIO_CMD53_BLOCK_MODE 27
498 #define SDIO_CMD53_FUNCTION_NUM 28
500 #define SDIO_CMD53_RW_FLAG 31
502 # define SDIO_CMD53_READ_FLAG 0
503 # define SDIO_CMD53_WRITE_FLAG 1
504 
508 #define SDIO_CIA 0
509 #define SDIO_FN0 0
510 #define SDIO_FN1 1
511 #define SDIO_FN2 2
512 #define SDIO_FN3 3
513 #define SDIO_FN4 4
514 #define SDIO_FN5 5
515 #define SDIO_FN6 6
516 #define SDIO_FN7 7
517 
519 #define SDIO_CCCR_SDIO_REV 0x00
522 #define SDIO_CCCR_REV_1_00 (0x0lu << 0)
523 #define SDIO_CCCR_REV_1_10 (0x1lu << 0)
524 #define SDIO_CCCR_REV_2_00 (0x2lu << 0)
525 #define SDIO_CCCR_REV_3_00 (0x3lu << 0)
526 #define SDIO_SDIO_REV_1_00 (0x0lu << 4)
527 #define SDIO_SDIO_REV_1_10 (0x1lu << 4)
528 #define SDIO_SDIO_REV_1_20 (0x2lu << 4)
529 #define SDIO_SDIO_REV_2_00 (0x3lu << 4)
530 #define SDIO_SDIO_REV_3_00 (0x4lu << 4)
531 #define SDIO_CCCR_SD_REV 0x01
532 #define SDIO_SD_REV_1_01 (0x0lu << 0)
533 #define SDIO_SD_REV_1_10 (0x1lu << 0)
534 #define SDIO_SD_REV_2_00 (0x2lu << 0)
535 #define SDIO_SD_REV_3_00 (0x3lu << 0)
536 #define SDIO_CCCR_IOE 0x02
537 #define SDIO_IOE_FN1 (0x1lu << 1)
538 #define SDIO_IOE_FN2 (0x1lu << 2)
539 #define SDIO_IOE_FN3 (0x1lu << 3)
540 #define SDIO_IOE_FN4 (0x1lu << 4)
541 #define SDIO_IOE_FN5 (0x1lu << 5)
542 #define SDIO_IOE_FN6 (0x1lu << 6)
543 #define SDIO_IOE_FN7 (0x1lu << 7)
544 #define SDIO_CCCR_IOR 0x03
545 #define SDIO_IOR_FN1 (0x1lu << 1)
546 #define SDIO_IOR_FN2 (0x1lu << 2)
547 #define SDIO_IOR_FN3 (0x1lu << 3)
548 #define SDIO_IOR_FN4 (0x1lu << 4)
549 #define SDIO_IOR_FN5 (0x1lu << 5)
550 #define SDIO_IOR_FN6 (0x1lu << 6)
551 #define SDIO_IOR_FN7 (0x1lu << 7)
552 #define SDIO_CCCR_IEN 0x04
553 #define SDIO_IENM (0x1lu << 0)
554 #define SDIO_IEN_FN1 (0x1lu << 1)
555 #define SDIO_IEN_FN2 (0x1lu << 2)
556 #define SDIO_IEN_FN3 (0x1lu << 3)
557 #define SDIO_IEN_FN4 (0x1lu << 4)
558 #define SDIO_IEN_FN5 (0x1lu << 5)
559 #define SDIO_IEN_FN6 (0x1lu << 6)
560 #define SDIO_IEN_FN7 (0x1lu << 7)
561 #define SDIO_CCCR_INT 0x05
562 #define SDIO_INT_FN1 (0x1lu << 1)
563 #define SDIO_INT_FN2 (0x1lu << 2)
564 #define SDIO_INT_FN3 (0x1lu << 3)
565 #define SDIO_INT_FN4 (0x1lu << 4)
566 #define SDIO_INT_FN5 (0x1lu << 5)
567 #define SDIO_INT_FN6 (0x1lu << 6)
568 #define SDIO_INT_FN7 (0x1lu << 7)
569 #define SDIO_CCCR_IOA 0x06
570 #define SDIO_AS_FN1 (0x1lu << 0)
571 #define SDIO_AS_FN2 (0x2lu << 0)
572 #define SDIO_AS_FN3 (0x3lu << 0)
573 #define SDIO_AS_FN4 (0x4lu << 0)
574 #define SDIO_AS_FN5 (0x5lu << 0)
575 #define SDIO_AS_FN6 (0x6lu << 0)
576 #define SDIO_AS_FN7 (0x7lu << 0)
577 #define SDIO_RES (0x1lu << 3)
578 #define SDIO_CCCR_BUS_CTRL 0x07
579 #define SDIO_BUSWIDTH_1B (0x0lu << 0)
580 #define SDIO_BUSWIDTH_4B (0x2lu << 0)
582 #define SDIO_BUS_ECSI (0x1lu << 5)
583 
584 #define SDIO_BUS_SCSI (0x1lu << 6)
585 
586 #define SDIO_BUS_CD_DISABLE (0x1lu << 7)
587 #define SDIO_CCCR_CAP 0x08
589 #define SDIO_CAP_SDC (0x1lu << 0)
590 
591 #define SDIO_CAP_SMB (0x1lu << 1)
592 
593 #define SDIO_CAP_SRW (0x1lu << 2)
594 
595 #define SDIO_CAP_SBS (0x1lu << 3)
596 
597 #define SDIO_CAP_S4MI (0x1lu << 4)
598 
599 #define SDIO_CAP_E4MI (0x1lu << 5)
600 
601 #define SDIO_CAP_LSC (0x1lu << 6)
602 
603 #define SDIO_CAP_4BLS (0x1lu << 7)
604 
605 #define SDIO_CCCR_CIS_PTR 0x09
606 
607 #define SDIO_CCCR_BUS_SUSPEND 0x0C
608 
609 #define SDIO_BS (0x1lu << 0)
610 
611 #define SDIO_BR (0x1lu << 1)
612 #define SDIO_CCCR_FUN_SEL 0x0D
613 #define SDIO_DF (0x1lu << 7)
614 #define SDIO_FS_CIA (0x0lu << 0)
615 #define SDIO_FS_FN1 (0x1lu << 0)
616 #define SDIO_FS_FN2 (0x2lu << 0)
617 #define SDIO_FS_FN3 (0x3lu << 0)
618 #define SDIO_FS_FN4 (0x4lu << 0)
619 #define SDIO_FS_FN5 (0x5lu << 0)
620 #define SDIO_FS_FN6 (0x6lu << 0)
621 #define SDIO_FS_FN7 (0x7lu << 0)
622 #define SDIO_FS_MEM (0x8lu << 0)
623 #define SDIO_CCCR_EXEC 0x0E
624 #define SDIO_EXM (0x1lu << 0)
625 #define SDIO_EX_FN1 (0x1lu << 1)
626 #define SDIO_EX_FN2 (0x1lu << 2)
627 #define SDIO_EX_FN3 (0x1lu << 3)
628 #define SDIO_EX_FN4 (0x1lu << 4)
629 #define SDIO_EX_FN5 (0x1lu << 5)
630 #define SDIO_EX_FN6 (0x1lu << 6)
631 #define SDIO_EX_FN7 (0x1lu << 7)
632 #define SDIO_CCCR_READY 0x0F
633 #define SDIO_RFM (0x1lu << 0)
634 #define SDIO_RF_FN1 (0x1lu << 1)
635 #define SDIO_RF_FN2 (0x1lu << 2)
636 #define SDIO_RF_FN3 (0x1lu << 3)
637 #define SDIO_RF_FN4 (0x1lu << 4)
638 #define SDIO_RF_FN5 (0x1lu << 5)
639 #define SDIO_RF_FN6 (0x1lu << 6)
640 #define SDIO_RF_FN7 (0x1lu << 7)
641 #define SDIO_CCCR_FN0_BLKSIZ 0x10
642 #define SDIO_CCCR_POWER 0x12
643 #define SDIO_POWER_SMPC (0x1lu << 0)
644 #define SDIO_POWER_EMPC (0x1lu << 1)
645 #define SDIO_CCCR_HS 0x13
646 #define SDIO_SHS (0x1lu << 0)
647 #define SDIO_EHS (0x1lu << 1)
648 
650 
653 #define SDIO_CISTPL_NULL 0x00
654 
655 #define SDIO_CISTPL_DEVICE 0x01
656 
657 #define SDIO_CISTPL_CHECKSUM 0x10
658 
659 #define SDIO_CISTPL_VERS_1 0x15
660 
661 #define SDIO_CISTPL_ALTSTR 0x16
662 
663 #define SDIO_CISTPL_MANFID 0x20
664 
665 #define SDIO_CISTPL_FUNCID 0x21
666 
667 #define SDIO_CISTPL_FUNCE 0x22
668 
669 #define SDIO_CISTPL_SDIO_STD 0x91
670 
671 #define SDIO_CISTPL_SDIO_EXT 0x92
672 
673 #define SDIO_CISTPL_END 0xFF
674 
677 
680 
685 static inline uint32_t SDMMC_UNSTUFF_BITS(uint8_t *reg, uint16_t reg_size,
686  uint16_t pos, uint8_t size)
687 {
688  uint32_t value;
689  value = reg[((reg_size - pos + 7) / 8) - 1] >> (pos % 8);
690  if (((pos % 8) + size) > 8) {
691  value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 2] << (8 - (pos % 8));
692  }
693  if (((pos % 8) + size) > 16) {
694  value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 3] << (16 - (pos % 8));
695  }
696  if (((pos % 8) + size) > 16) {
697  value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 3] << (16 - (pos % 8));
698  }
699  value &= ((uint32_t)1 << size) - 1;
700  return value;
701 }
702 
705 #define CSD_REG_BIT_SIZE 128
706 #define CSD_REG_BSIZE (CSD_REG_BIT_SIZE / 8)
707 #define CSD_STRUCTURE(csd, pos, size) \
708  SDMMC_UNSTUFF_BITS(csd, CSD_REG_BIT_SIZE, pos, size)
709 #define CSD_STRUCTURE_VERSION(csd) CSD_STRUCTURE(csd, 126, 2)
710 #define SD_CSD_VER_1_0 0
711 #define SD_CSD_VER_2_0 1
712 #define MMC_CSD_VER_1_0 0
713 #define MMC_CSD_VER_1_1 1
714 #define MMC_CSD_VER_1_2 2
715 #define CSD_TRAN_SPEED(csd) CSD_STRUCTURE(csd, 96, 8)
716 #define SD_CSD_1_0_C_SIZE(csd) CSD_STRUCTURE(csd, 62, 12)
717 #define SD_CSD_1_0_C_SIZE_MULT(csd) CSD_STRUCTURE(csd, 47, 3)
718 #define SD_CSD_1_0_READ_BL_LEN(csd) CSD_STRUCTURE(csd, 80, 4)
719 #define SD_CSD_2_0_C_SIZE(csd) CSD_STRUCTURE(csd, 48, 22)
720 #define MMC_CSD_C_SIZE(csd) CSD_STRUCTURE(csd, 62, 12)
721 #define MMC_CSD_C_SIZE_MULT(csd) CSD_STRUCTURE(csd, 47, 3)
722 #define MMC_CSD_READ_BL_LEN(csd) CSD_STRUCTURE(csd, 80, 4)
723 #define MMC_CSD_SPEC_VERS(csd) CSD_STRUCTURE(csd, 122, 4)
724 
728 #define OCR_REG_BSIZE (32 / 8)
729 #define OCR_VDD_170_195 (1lu << 7)
730 #define OCR_VDD_20_21 (1lu << 8)
731 #define OCR_VDD_21_22 (1lu << 9)
732 #define OCR_VDD_22_23 (1lu << 10)
733 #define OCR_VDD_23_24 (1lu << 11)
734 #define OCR_VDD_24_25 (1lu << 12)
735 #define OCR_VDD_25_26 (1lu << 13)
736 #define OCR_VDD_26_27 (1lu << 14)
737 #define OCR_VDD_27_28 (1lu << 15)
738 #define OCR_VDD_28_29 (1lu << 16)
739 #define OCR_VDD_29_30 (1lu << 17)
740 #define OCR_VDD_30_31 (1lu << 18)
741 #define OCR_VDD_31_32 (1lu << 19)
742 #define OCR_VDD_32_33 (1lu << 20)
743 #define OCR_VDD_33_34 (1lu << 21)
744 #define OCR_VDD_34_35 (1lu << 22)
745 #define OCR_VDD_35_36 (1lu << 23)
746 #define OCR_SDIO_S18R (1lu << 24)
747 #define OCR_SDIO_MP (1lu << 27)
748 #define OCR_SDIO_NF (7lu << 28)
749 #define OCR_ACCESS_MODE_MASK (3lu << 29)
750 #define OCR_ACCESS_MODE_BYTE (0lu << 29)
751 #define OCR_ACCESS_MODE_SECTOR (2lu << 29)
752 #define OCR_CCS (1lu << 30)
753 #define OCR_POWER_UP_BUSY (1lu << 31)
754 
756 #define SD_SCR_REG_BIT_SIZE 64
759 #define SD_SCR_REG_BSIZE (SD_SCR_REG_BIT_SIZE / 8)
760 #define SD_SCR_STRUCTURE(scr, pos, size) \
761  SDMMC_UNSTUFF_BITS(scr, SD_SCR_REG_BIT_SIZE, pos, size)
762 #define SD_SCR_SCR_STRUCTURE(scr) SD_SCR_STRUCTURE(scr, 60, 4)
763 #define SD_SCR_SCR_STRUCTURE_1_0 0
764 #define SD_SCR_SD_SPEC(scr) SD_SCR_STRUCTURE(scr, 56, 4)
765 #define SD_SCR_SD_SPEC_1_0_01 0
766 #define SD_SCR_SD_SPEC_1_10 1
767 #define SD_SCR_SD_SPEC_2_00 2
768 #define SD_SCR_DATA_STATUS_AFTER_ERASE(scr) SD_SCR_STRUCTURE(scr, 55, 1)
769 #define SD_SCR_SD_SECURITY(scr) SD_SCR_STRUCTURE(scr, 52, 3)
770 #define SD_SCR_SD_SECURITY_NO 0
771 #define SD_SCR_SD_SECURITY_NOTUSED 1
772 #define SD_SCR_SD_SECURITY_1_01 2
773 #define SD_SCR_SD_SECURITY_2_00 3
774 #define SD_SCR_SD_SECURITY_3_00 4
775 #define SD_SCR_SD_BUS_WIDTHS(scr) SD_SCR_STRUCTURE(scr, 48, 4)
776 #define SD_SCR_SD_BUS_WIDTH_1BITS (1lu << 0)
777 #define SD_SCR_SD_BUS_WIDTH_4BITS (1lu << 2)
778 #define SD_SCR_SD_SPEC3(scr) SD_SCR_STRUCTURE(scr, 47, 1)
779 #define SD_SCR_SD_SPEC_3_00 1
780 #define SD_SCR_SD_EX_SECURITY(scr) SD_SCR_STRUCTURE(scr, 43, 4)
781 #define SD_SCR_SD_CMD_SUPPORT(scr) SD_SCR_STRUCTURE(scr, 32, 2)
782 
786 #define SD_SW_STATUS_BIT_SIZE 512
787 #define SD_SW_STATUS_BSIZE (SD_SW_STATUS_BIT_SIZE / 8)
788 #define SD_SW_STATUS_STRUCTURE(sd_sw_status, pos, size) \
789  SDMMC_UNSTUFF_BITS(sd_sw_status, SD_SW_STATUS_BIT_SIZE, pos, size)
790 #define SD_SW_STATUS_MAX_CURRENT_CONSUMPTION(status) \
791  SD_SW_STATUS_STRUCTURE(status, 496, 16)
792 #define SD_SW_STATUS_FUN_GRP6_INFO(status) \
793  SD_SW_STATUS_STRUCTURE(status, 480, 16)
794 #define SD_SW_STATUS_FUN_GRP5_INFO(status) \
795  SD_SW_STATUS_STRUCTURE(status, 464, 16)
796 #define SD_SW_STATUS_FUN_GRP4_INFO(status) \
797  SD_SW_STATUS_STRUCTURE(status, 448, 16)
798 #define SD_SW_STATUS_FUN_GRP3_INFO(status) \
799  SD_SW_STATUS_STRUCTURE(status, 432, 16)
800 #define SD_SW_STATUS_FUN_GRP2_INFO(status) \
801  SD_SW_STATUS_STRUCTURE(status, 416, 16)
802 #define SD_SW_STATUS_FUN_GRP1_INFO(status) \
803  SD_SW_STATUS_STRUCTURE(status, 400, 16)
804 #define SD_SW_STATUS_FUN_GRP6_RC(status) \
805  SD_SW_STATUS_STRUCTURE(status, 396, 4)
806 #define SD_SW_STATUS_FUN_GRP5_RC(status) \
807  SD_SW_STATUS_STRUCTURE(status, 392, 4)
808 #define SD_SW_STATUS_FUN_GRP4_RC(status) \
809  SD_SW_STATUS_STRUCTURE(status, 388, 4)
810 #define SD_SW_STATUS_FUN_GRP3_RC(status) \
811  SD_SW_STATUS_STRUCTURE(status, 384, 4)
812 #define SD_SW_STATUS_FUN_GRP2_RC(status) \
813  SD_SW_STATUS_STRUCTURE(status, 380, 4)
814 #define SD_SW_STATUS_FUN_GRP1_RC(status) \
815  SD_SW_STATUS_STRUCTURE(status, 376, 4)
816 #define SD_SW_STATUS_FUN_GRP_RC_ERROR 0xFU
817 #define SD_SW_STATUS_DATA_STRUCT_VER(status) \
818  SD_SW_STATUS_STRUCTURE(status, 368, 8)
819 #define SD_SW_STATUS_FUN_GRP6_BUSY(status) \
820  SD_SW_STATUS_STRUCTURE(status, 352, 16)
821 #define SD_SW_STATUS_FUN_GRP5_BUSY(status) \
822  SD_SW_STATUS_STRUCTURE(status, 336, 16)
823 #define SD_SW_STATUS_FUN_GRP4_BUSY(status) \
824  SD_SW_STATUS_STRUCTURE(status, 320, 16)
825 #define SD_SW_STATUS_FUN_GRP3_BUSY(status) \
826  SD_SW_STATUS_STRUCTURE(status, 304, 16)
827 #define SD_SW_STATUS_FUN_GRP2_BUSY(status) \
828  SD_SW_STATUS_STRUCTURE(status, 288, 16)
829 #define SD_SW_STATUS_FUN_GRP1_BUSY(status) \
830  SD_SW_STATUS_STRUCTURE(status, 272, 16)
831 
835 #define CARD_STATUS_APP_CMD (1lu << 5)
836 #define CARD_STATUS_SWITCH_ERROR (1lu << 7)
837 #define CARD_STATUS_READY_FOR_DATA (1lu << 8)
838 #define CARD_STATUS_STATE_IDLE (0lu << 9)
839 #define CARD_STATUS_STATE_READY (1lu << 9)
840 #define CARD_STATUS_STATE_IDENT (2lu << 9)
841 #define CARD_STATUS_STATE_STBY (3lu << 9)
842 #define CARD_STATUS_STATE_TRAN (4lu << 9)
843 #define CARD_STATUS_STATE_DATA (5lu << 9)
844 #define CARD_STATUS_STATE_RCV (6lu << 9)
845 #define CARD_STATUS_STATE_PRG (7lu << 9)
846 #define CARD_STATUS_STATE_DIS (8lu << 9)
847 #define CARD_STATUS_STATE (0xFlu << 9)
848 #define CARD_STATUS_ERASE_RESET (1lu << 13)
849 #define CARD_STATUS_WP_ERASE_SKIP (1lu << 15)
850 #define CARD_STATUS_CIDCSD_OVERWRITE (1lu << 16)
851 #define CARD_STATUS_OVERRUN (1lu << 17)
852 #define CARD_STATUS_UNERRUN (1lu << 18)
853 #define CARD_STATUS_ERROR (1lu << 19)
854 #define CARD_STATUS_CC_ERROR (1lu << 20)
855 #define CARD_STATUS_CARD_ECC_FAILED (1lu << 21)
856 #define CARD_STATUS_ILLEGAL_COMMAND (1lu << 22)
857 #define CARD_STATUS_COM_CRC_ERROR (1lu << 23)
858 #define CARD_STATUS_UNLOCK_FAILED (1lu << 24)
859 #define CARD_STATUS_CARD_IS_LOCKED (1lu << 25)
860 #define CARD_STATUS_WP_VIOLATION (1lu << 26)
861 #define CARD_STATUS_ERASE_PARAM (1lu << 27)
862 #define CARD_STATUS_ERASE_SEQ_ERROR (1lu << 28)
863 #define CARD_STATUS_BLOCK_LEN_ERROR (1lu << 29)
864 #define CARD_STATUS_ADDRESS_MISALIGN (1lu << 30)
865 #define CARD_STATUS_ADDR_OUT_OF_RANGE (1lu << 31)
866 
867 #define CARD_STATUS_ERR_RD_WR (CARD_STATUS_ADDR_OUT_OF_RANGE \
868  | CARD_STATUS_ADDRESS_MISALIGN \
869  | CARD_STATUS_BLOCK_LEN_ERROR \
870  | CARD_STATUS_WP_VIOLATION \
871  | CARD_STATUS_ILLEGAL_COMMAND \
872  | CARD_STATUS_CC_ERROR \
873  | CARD_STATUS_ERROR)
874 
878 #define SD_STATUS_BSIZE (512 / 8)
879 
881 #define EXT_CSD_BSIZE 512
884 /* Below belongs to Properties Segment */
885 #define EXT_CSD_S_CMD_SET_INDEX 504lu
886 #define EXT_CSD_BOOT_INFO_INDEX 228lu
887 #define EXT_CSD_BOOT_SIZE_MULTI_INDEX 226lu
888 #define EXT_CSD_ACC_SIZE_INDEX 225lu
889 #define EXT_CSD_HC_ERASE_GRP_SIZE_INDEX 224lu
890 #define EXT_CSD_ERASE_TIMEOUT_MULT_INDEX 223lu
891 #define EXT_CSD_REL_WR_SEC_C_INDEX 222lu
892 #define EXT_CSD_HC_WP_GRP_SIZE_INDEX 221lu
893 #define EXT_CSD_S_C_VCC_INDEX 220lu
894 #define EXT_CSD_S_C_VCCQ_INDEX 219lu
895 #define EXT_CSD_S_A_TIMEOUT_INDEX 217lu
896 #define EXT_CSD_SEC_COUNT_INDEX 212lu
897 #define EXT_CSD_MIN_PERF_W_8_52_INDEX 210lu
898 #define EXT_CSD_MIN_PERF_R_8_52_INDEX 209lu
899 #define EXT_CSD_MIN_PERF_W_8_26_4_52_INDEX 208lu
900 #define EXT_CSD_MIN_PERF_R_8_26_4_52_INDEX 207lu
901 #define EXT_CSD_MIN_PERF_W_4_26_INDEX 206lu
902 #define EXT_CSD_MIN_PERF_R_4_26_INDEX 205lu
903 #define EXT_CSD_PWR_CL_26_360_INDEX 203lu
904 #define EXT_CSD_PWR_CL_52_360_INDEX 202lu
905 #define EXT_CSD_PWR_CL_26_195_INDEX 201lu
906 #define EXT_CSD_PWR_CL_52_195_INDEX 200lu
907 #define EXT_CSD_CARD_TYPE_INDEX 196lu
908 /* MMC card type */
909 # define MMC_CTYPE_26MHZ 0x1
910 # define MMC_CTYPE_52MHZ 0x2
911 #define EXT_CSD_CSD_STRUCTURE_INDEX 194lu
912 #define EXT_CSD_EXT_CSD_REV_INDEX 192lu
913 
914 /* Below belongs to Mode Segment */
915 #define EXT_CSD_CMD_SET_INDEX 191lu
916 #define EXT_CSD_CMD_SET_REV_INDEX 189lu
917 #define EXT_CSD_POWER_CLASS_INDEX 187lu
918 #define EXT_CSD_HS_TIMING_INDEX 185lu
919 #define EXT_CSD_BUS_WIDTH_INDEX 183lu
920 #define EXT_CSD_ERASED_MEM_CONT_INDEX 181lu
921 #define EXT_CSD_BOOT_CONFIG_INDEX 179lu
922 #define EXT_CSD_BOOT_BUS_WIDTH_INDEX 177lu
923 #define EXT_CSD_ERASE_GROUP_DEF_INDEX 175lu
924 
927 
930 
932 #define SPI_CMD_ENCODE(x) (0x40 | (x & 0x3F))
933 
937 #define R1_SPI_IDLE (1lu << 0)
938 #define R1_SPI_ERASE_RESET (1lu << 1)
939 #define R1_SPI_ILLEGAL_COMMAND (1lu << 2)
940 #define R1_SPI_COM_CRC (1lu << 3)
941 #define R1_SPI_ERASE_SEQ (1lu << 4)
942 #define R1_SPI_ADDRESS (1lu << 5)
943 #define R1_SPI_PARAMETER (1lu << 6)
944 // R1 bit 7 is always zero, reuse this bit for error
945 #define R1_SPI_ERROR (1lu << 7)
946 
951 #define R2_SPI_CARD_LOCKED (1lu << 0)
952 #define R2_SPI_WP_ERASE_SKIP (1lu << 1)
953 #define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
954 #define R2_SPI_ERROR (1lu << 2)
955 #define R2_SPI_CC_ERROR (1lu << 3)
956 #define R2_SPI_CARD_ECC_ERROR (1lu << 4)
957 #define R2_SPI_WP_VIOLATION (1lu << 5)
958 #define R2_SPI_ERASE_PARAM (1lu << 6)
959 #define R2_SPI_OUT_OF_RANGE (1lu << 7)
960 #define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE
961 
967 #define SPI_TOKEN_SINGLE_MULTI_READ 0xFE
968 #define SPI_TOKEN_DATA_ERROR_VALID(token) (((token) & 0xF0) == 0)
969 #define SPI_TOKEN_DATA_ERROR_ERRORS (0x0F)
970 #define SPI_TOKEN_DATA_ERROR_ERROR (1lu << 0)
971 #define SPI_TOKEN_DATA_ERROR_CC_ERROR (1lu << 1)
972 #define SPI_TOKEN_DATA_ERROR_ECC_ERROR (1lu << 2)
973 #define SPI_TOKEN_DATA_ERROR_OUT_RANGE (1lu << 3)
974 #define SPI_TOKEN_SINGLE_WRITE 0xFE
978 #define SPI_TOKEN_MULTI_WRITE 0xFC
979 #define SPI_TOKEN_STOP_TRAN 0xFD
980 #define SPI_TOKEN_DATA_RESP_VALID(token) \
981  ((((token) & (1 << 4)) == 0) && (((token) & (1 << 0)) == 1))
982 #define SPI_TOKEN_DATA_RESP_CODE(token) ((token) & 0x1E)
983 #define SPI_TOKEN_DATA_RESP_ACCEPTED (2lu << 1)
984 #define SPI_TOKEN_DATA_RESP_CRC_ERR (5lu << 1)
985 #define SPI_TOKEN_DATA_RESP_WRITE_ERR (6lu << 1)
986 
990 
992 
993 #ifdef __cplusplus
994 }
995 #endif
996 
997 #endif /* SD_MMC_PROTOCOL_H_INCLUDED */
static uint32_t SDMMC_UNSTUFF_BITS(uint8_t *reg, uint16_t reg_size, uint16_t pos, uint8_t size)
Macro function to extract a bits field from a large SD MMC register Used by : CSD, SCR, Switch status.
GeneratorWrapper< T > value(T &&value)
Definition: catch.hpp:3589
Commonly used includes, types and macros.
uint32_t sdmmc_cmd_def_t
Value to define a SD/MMC/SDIO command.


inertial_sense_ros
Author(s):
autogenerated on Sat Sep 19 2020 03:19:05