pio_handler.c
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1 
33 /*
34  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
35  */
36 
37 #include "pio.h"
38 #include "pio_handler.h"
39 
45 #define MAX_INTERRUPT_SOURCES 7
46 
52  uint32_t id;
53  uint32_t mask;
54  uint32_t attr;
55 
56  /* Interrupt handler. */
57  void (*handler) (const uint32_t, const uint32_t);
58 };
59 
60 
61 /* List of interrupt sources. */
63 
64 /* Number of currently defined interrupt sources. */
65 static uint32_t gs_ul_nb_sources = 0;
66 
67 #if (SAM3S || SAM4S || SAM4E)
68 /* PIO Capture handler */
69 static void (*pio_capture_handler)(Pio *) = NULL;
70 extern uint32_t pio_capture_enable_flag;
71 #endif
72 
79 void pio_handler_process(Pio *p_pio, uint32_t ul_id)
80 {
81  uint32_t status;
82  uint32_t i;
83 
84  /* Read PIO controller status */
85  status = pio_get_interrupt_status(p_pio);
86  status &= pio_get_interrupt_mask(p_pio);
87 
88  /* Check pending events */
89  if (status != 0) {
90  /* Find triggering source */
91  i = 0;
92  while (status != 0) {
93  /* Source is configured on the same controller */
94  if (gs_interrupt_sources[i].id == ul_id) {
95  /* Source has PIOs whose statuses have changed */
96  if ((status & gs_interrupt_sources[i].mask) != 0) {
98  gs_interrupt_sources[i].mask);
99  status &= ~(gs_interrupt_sources[i].mask);
100  }
101  }
102  i++;
103  if (i >= MAX_INTERRUPT_SOURCES) {
104  break;
105  }
106  }
107  }
108 
109  /* Check capture events */
110 #if (SAM3S || SAM4S || SAM4E)
111  if (pio_capture_enable_flag) {
112  if (pio_capture_handler) {
113  pio_capture_handler(p_pio);
114  }
115  }
116 #endif
117 }
118 
132 uint32_t pio_handler_set(Pio *p_pio, uint32_t ul_id, uint32_t ul_mask,
133  uint32_t ul_attr, void (*p_handler) (uint32_t, uint32_t))
134 {
135  uint8_t i;
136  struct s_interrupt_source *pSource;
137 
139  return 1;
140 
141  /* Check interrupt for this pin, if already defined, redefine it. */
142  for (i = 0; i <= gs_ul_nb_sources; i++) {
143  pSource = &(gs_interrupt_sources[i]);
144  if (pSource->id == ul_id && pSource->mask == ul_mask) {
145  break;
146  }
147  }
148 
149  /* Define new source */
150  pSource->id = ul_id;
151  pSource->mask = ul_mask;
152  pSource->attr = ul_attr;
153  pSource->handler = p_handler;
154  if (i == gs_ul_nb_sources + 1) {
156  }
157 
158  /* Configure interrupt mode */
159  pio_configure_interrupt(p_pio, ul_mask, ul_attr);
160 
161  return 0;
162 }
163 
164 #if (SAM3S || SAM4S || SAM4E)
165 
174 void pio_capture_handler_set(void (*p_handler)(Pio *))
175 {
176  pio_capture_handler = p_handler;
177 }
178 #endif
179 
180 #ifdef ID_PIOA
181 
192 uint32_t pio_handler_set_pin(uint32_t ul_pin, uint32_t ul_flag,
193  void (*p_handler) (uint32_t, uint32_t))
194 {
195  Pio *p_pio = pio_get_pin_group(ul_pin);
196  uint32_t group_id = pio_get_pin_group_id(ul_pin);
197  uint32_t group_mask = pio_get_pin_group_mask(ul_pin);
198 
199  return pio_handler_set(p_pio, group_id, group_mask, ul_flag, p_handler);
200 }
201 
206 void PIOA_Handler(void)
207 {
209 }
210 #endif
211 
212 #ifdef ID_PIOB
213 
217 void PIOB_Handler(void)
218 {
220 }
221 #endif
222 
223 #ifdef ID_PIOC
224 
228 void PIOC_Handler(void)
229 {
231 }
232 #endif
233 
234 #ifdef ID_PIOD
235 
239 void PIOD_Handler(void)
240 {
242 }
243 #endif
244 
245 #ifdef ID_PIOE
246 
250 void PIOE_Handler(void)
251 {
253 }
254 #endif
255 
256 #ifdef ID_PIOF
257 
261 void PIOF_Handler(void)
262 {
263  pio_handler_process(PIOF, ID_PIOF);
264 }
265 #endif
266 
274 void pio_handler_set_priority(Pio *p_pio, IRQn_Type ul_irqn, uint32_t ul_priority)
275 {
276  uint32_t bitmask = 0;
277 
278  bitmask = pio_get_interrupt_mask(p_pio);
279  pio_disable_interrupt(p_pio, 0xFFFFFFFF);
281  NVIC_DisableIRQ(ul_irqn);
282  NVIC_ClearPendingIRQ(ul_irqn);
283  NVIC_SetPriority(ul_irqn, ul_priority);
284  NVIC_EnableIRQ(ul_irqn);
285  pio_enable_interrupt(p_pio, bitmask);
286 }
void pio_configure_interrupt(Pio *p_pio, const uint32_t ul_mask, const uint32_t ul_attr)
Configure the given interrupt source. Interrupt can be configured to trigger on rising edge...
Definition: pio.c:538
#define MAX_INTERRUPT_SOURCES
Definition: pio_handler.c:45
#define PIOA
(PIOA ) Base Address
Definition: same70j19.h:529
static uint32_t gs_ul_nb_sources
Definition: pio_handler.c:65
void pio_handler_process(Pio *p_pio, uint32_t ul_id)
Process an interrupt request on the given PIO controller.
Definition: pio_handler.c:79
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm7.h:1766
#define NULL
Definition: nm_bsp.h:52
#define ID_PIOB
Parallel I/O Controller B (PIOB)
Definition: same70j19.h:417
void PIOE_Handler(void)
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Definition: core_cm7.h:1696
Parallel Input/Output (PIO) Controller driver for SAM.
uint32_t pio_get_pin_group_id(uint32_t ul_pin)
Return GPIO port peripheral ID for a GPIO pin.
Definition: pio.c:979
void PIOB_Handler(void)
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
Definition: core_cm7.h:1683
void pio_enable_interrupt(Pio *p_pio, const uint32_t ul_mask)
Enable the given interrupt source. The PIO must be configured as an NVIC interrupt source as well...
Definition: pio.c:578
void pio_disable_interrupt(Pio *p_pio, const uint32_t ul_mask)
Disable a given interrupt source, with no added side effects.
Definition: pio.c:589
uint32_t pio_handler_set_pin(uint32_t ul_pin, uint32_t ul_flag, void(*p_handler)(uint32_t, uint32_t))
#define ID_PIOA
Parallel I/O Controller A (PIOA)
Definition: same70j19.h:416
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm7.h:1736
Pio hardware registers.
#define PIOD
(PIOD ) Base Address
Definition: same70j19.h:531
Pio * pio_get_pin_group(uint32_t ul_pin)
Return GPIO port for a GPIO pin.
Definition: pio.c:944
uint32_t pio_get_interrupt_status(const Pio *p_pio)
Read and clear PIO interrupt status.
Definition: pio.c:601
void PIOD_Handler(void)
Parallel Input/Output (PIO) interrupt handler for SAM.
void pio_handler_set_priority(Pio *p_pio, IRQn_Type ul_irqn, uint32_t ul_priority)
Initialize PIO interrupt management logic.
Definition: pio_handler.c:274
#define ID_PIOD
Parallel I/O Controller D (PIOD)
Definition: same70j19.h:420
enum IRQn IRQn_Type
#define PIOB
(PIOB ) Base Address
Definition: same70j19.h:530
#define ID_PIOE
Parallel I/O Controller E (PIOE)
Definition: same70q19.h:477
void PIOC_Handler(void)
void(* handler)(const uint32_t, const uint32_t)
Definition: pio_handler.c:57
static struct s_interrupt_source gs_interrupt_sources[MAX_INTERRUPT_SOURCES]
Definition: pio_handler.c:62
void PIOA_Handler(void)
#define ID_PIOC
Parallel I/O Controller C (PIOC)
Definition: same70q19.h:472
#define PIOC
(PIOC ) Base Address
Definition: same70q19.h:626
uint32_t pio_get_interrupt_mask(const Pio *p_pio)
Read PIO interrupt mask.
Definition: pio.c:613
#define PIOE
(PIOE ) Base Address
Definition: same70q19.h:628
uint32_t pio_get_pin_group_mask(uint32_t ul_pin)
Return GPIO port pin mask for a GPIO pin.
Definition: pio.c:1025
uint32_t pio_handler_set(Pio *p_pio, uint32_t ul_id, uint32_t ul_mask, uint32_t ul_attr, void(*p_handler)(uint32_t, uint32_t))
Set an interrupt handler for the provided pins. The provided handler will be called with the triggeri...
Definition: pio_handler.c:132


inertial_sense_ros
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autogenerated on Sat Sep 19 2020 03:19:04